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1. 发明申请

US20110101511A1 POWER SEMICONDUCTOR PACKAGE 有权
标题翻译：功率半导体封装
公开(公告)号：US20110101511A1
公开(公告)日：2011-05-05
申请号：US12608853
申请日：2009-10-29
申请人： Jun Lu , François Hébert
发明人： Jun Lu , François Hébert
IPC分类号： H01L23/52 , H01L21/98 , H01L23/495
CPC分类号： H01L23/492 , H01L24/36 , H01L24/40 , H01L25/071 , H01L25/072 , H01L25/16 , H01L2224/32145 , H01L2224/32245 , H01L2224/40095 , H01L2224/40137 , H01L2224/73253 , H01L2224/83801 , H01L2224/8385 , H01L2224/84801 , H01L2224/8485 , H01L2924/00014 , H01L2924/01006 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/07802 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/00 , H01L2224/37099
摘要： The present invention features a power semiconductor package and a method of forming the same that includes forming, in the body, a stress relief region disposed between a pair of mounting regions and attaching a semiconductor die in each of the mounting regions. The semiconductor die has first and second sets of electrical contacts with the first set being on a first surface of the semiconductor die and the second set being disposed upon a second surface of the semiconductor die opposite to the first surface. The first set is in electrical communication with the mounting region. Walls are formed on outer sides of the pair of mounting regions, defining a shaped body, with the shaped body and walls defining an electrically conductive path that extends from the first set and terminates on side of the package common with the second set.
摘要翻译：本发明的特征在于功率半导体封装及其形成方法，其包括在主体中形成设置在一对安装区域之间的应力释放区域，并且在每个安装区域中安装半导体管芯。半导体管芯具有第一组和第二组电触点，第一组在半导体管芯的第一表面上，第二组设置在与第一表面相对的半导体管芯的第二表面上。第一组与安装区域电连通。壁形成在一对安装区域的外侧，限定成形体，成形体和壁限定从第一组延伸并终止于与第二组共同的包装侧的导电路径。

2. 发明申请

US20150076676A1 POWER SEMICONDUCTOR DEVICE PACKAGE AND FABRICATION METHOD 审中-公开
标题翻译：功率半导体器件封装和制造方法
公开(公告)号：US20150076676A1
公开(公告)日：2015-03-19
申请号：US14029555
申请日：2013-09-17
申请人： Jun Lu , François Hébert , Kai Liu , Xiaotian Zhang
发明人： Jun Lu , François Hébert , Kai Liu , Xiaotian Zhang
IPC分类号： H01L23/495 , H01L25/07
CPC分类号： H01L23/492 , H01L24/97 , H01L25/072 , H01L25/50 , H01L2224/0603 , H01L2224/06181 , H01L2224/291 , H01L2224/2919 , H01L2224/32245 , H01L2224/97 , H01L2924/13091 , H01L2924/15156 , H01L2224/83 , H01L2924/014 , H01L2924/00
摘要： A power semiconductor device package includes a conductive assembly including a connecting structure and a semiconductor die having an aperture formed therethrough, the aperture being sized and configured to spacedly receive the connecting structure. In an alternative embodiment, a power semiconductor device package includes a conductive assembly including a connecting structure and a pair of semiconductor die disposed on either side of the connecting structure in spaced relationship thereto.
摘要翻译：功率半导体器件封装包括导电组件，其包括连接结构和具有穿过其形成的孔的半导体管芯，所述孔的尺寸和构造为间隔地接收连接结构。在替代实施例中，功率半导体器件封装包括导电组件，该导电组件包括连接结构和设置在与之间隔开的连接结构的任一侧上的一对半导体管芯。

3. 发明授权

US07971340B2 Planar grooved power inductor structure and method 有权
标题翻译：平面沟槽功率电感结构及方法
公开(公告)号：US07971340B2
公开(公告)日：2011-07-05
申请号：US13007551
申请日：2011-01-14
申请人： François Hébert , Tao Feng , Jun Lu
发明人： François Hébert , Tao Feng , Jun Lu
IPC分类号： H01F7/02
CPC分类号： H01F17/0033 , H01F1/344 , H01F41/046 , H01F2017/002 , Y10T29/4902
摘要： An inductor may include a planar ferrite core. A first group of one or more grooves is formed in a first side of the ferrite core. A second group of two or more grooves is formed in a second side of the ferrite core. The grooves in the first and second groups are oriented such that each groove in the first group overlaps with two corresponding grooves in the second group. A first plurality of vias communicates through the ferrite core between the first and second sides of the ferrite core. Each via is located where a groove in the first group overlaps with a groove in the second group. A conductive material is disposed in the first and second groups of grooves and in the vias to form an inductor coil.
摘要翻译：电感器可以包括平面铁氧体磁芯。第一组一个或多个凹槽形成在铁氧体磁芯的第一侧。在铁氧体磁芯的第二侧形成有第二组两个或多个凹槽。第一组和第二组中的凹槽被定向成使得第一组中的每个凹槽与第二组中的两个相应的凹槽重叠。第一多个通孔在铁氧体磁芯的第一和第二侧之间通过铁氧体磁芯连通。每个通孔位于第一组中的凹槽与第二组中的凹槽重叠的位置。导电材料设置在第一和第二组沟槽和通孔中以形成电感线圈。

4. 发明授权

US07884696B2 Lead frame-based discrete power inductor 有权
公开(公告)号：US07884696B2
公开(公告)日：2011-02-08
申请号：US12011489
申请日：2008-01-25
申请人： François Hébert , Tao Feng , Xiaotian Zhang , Jun Lu
发明人： François Hébert , Tao Feng , Xiaotian Zhang , Jun Lu
IPC分类号： H01F5/00
CPC分类号： H01F17/062
摘要： A lead frame-based discrete power inductor is disclosed. The power inductor includes top and bottom lead frames, the leads of which form a coil around a single closed-loop magnetic core. The coil includes interconnections between inner and outer contact sections of the top and bottom lead frames, the magnetic core being sandwiched between the top and bottom lead frames. Ones of the leads of the top and bottom lead frames have a generally non-linear, stepped configuration such that the leads of the top lead frame couple adjacent leads of the bottom lead frame about the magnetic core to form the coil.

5. 发明授权

US07939370B1 Power semiconductor package 有权
标题翻译：功率半导体封装
公开(公告)号：US07939370B1
公开(公告)日：2011-05-10
申请号：US12608853
申请日：2009-10-29
申请人： Jun Lu , François Hébert
发明人： Jun Lu , François Hébert
IPC分类号： H01L21/00
CPC分类号： H01L23/492 , H01L24/36 , H01L24/40 , H01L25/071 , H01L25/072 , H01L25/16 , H01L2224/32145 , H01L2224/32245 , H01L2224/40095 , H01L2224/40137 , H01L2224/73253 , H01L2224/83801 , H01L2224/8385 , H01L2224/84801 , H01L2224/8485 , H01L2924/00014 , H01L2924/01006 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/07802 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/00 , H01L2224/37099
摘要： The present invention features a power semiconductor package and a method of forming the same that includes forming, in the body, a stress relief region disposed between a pair of mounting regions and attaching a semiconductor die in each of the mounting regions. The semiconductor die has first and second sets of electrical contacts with the first set being on a first surface of the semiconductor die and the second set being disposed upon a second surface of the semiconductor die opposite to the first surface. The first set is in electrical communication with the mounting region. Walls are formed on outer sides of the pair of mounting regions, defining a shaped body, with the shaped body and walls defining an electrically conductive path that extends from the first set and terminates on side of the package common with the second set.
摘要翻译：本发明的特征在于功率半导体封装及其形成方法，其包括在主体中形成设置在一对安装区域之间的应力释放区域，并且在每个安装区域中安装半导体管芯。半导体管芯具有第一组和第二组电触点，第一组在半导体管芯的第一表面上，第二组设置在与第一表面相对的半导体管芯的第二表面上。第一组与安装区域电连通。壁形成在一对安装区域的外侧，限定成形体，成形体和壁限定从第一组延伸并终止于与第二组共同的包装侧的导电路径。

6. 发明申请

US20110012701A1 MULTILAYER INDUCTOR 有权
标题翻译：多层电感器
公开(公告)号：US20110012701A1
公开(公告)日：2011-01-20
申请号：US12891105
申请日：2010-09-27
申请人： Jun Lu , François Hébert
发明人： Jun Lu , François Hébert
IPC分类号： H01F5/00 , H01F7/06
CPC分类号： H01F17/0013 , H01F27/29 , H01F41/046 , H01L2224/16235 , H01L2924/15311 , Y10T29/4902 , Y10T29/49069 , Y10T29/49073
摘要： A multilayer inductor is disclosed. The multilayer inductor includes a bottom magnetic layer having an external conductive pattern formed on a bottom surface thereof for connection to a substrate such as a printed circuit board. The bottom external conductive pattern includes signal/power contacts and first and second inductor electrodes. A top magnetic layer includes a top external conductive pattern having signal/power contacts and inductor electrode contacts. An inductor conductive pattern formed on the top surfaces of intermediate magnetic layers disposed between the top and bottom magnetic layers are electrically coupled to each other by means of through holes to form a spiral inductor element. The spiral inductor element is coupled to the first inductor electrode by means of a through hole formed in the bottom magnetic layer and to the second inductor electrode by means of power conductive traces formed on side surfaces of the multilayer inductor. Flux density reducing layers may be inserted directly above the bottom magnetic layer and directly below the top magnetic layer. Signal/power conductive traces formed on side surfaces of the multilayer inductor provide signal/power routing between the top magnetic layer signal/power contacts and the bottom magnetic layer signal/power contacts. The top external conductive pattern accommodates a semiconductor chip in a flip chip configuration.
摘要翻译：公开了一种多层电感器。多层电感器包括底部磁性层，其具有形成在其底表面上的外部导电图案，用于连接到诸如印刷电路板的基板。底部外部导电图案包括信号/电源触点和第一和第二电感器电极。顶部磁性层包括具有信号/功率触点和电感器电极触点的顶部外部导电图案。形成在设置在顶部和底部磁性层之间的中间磁性层的顶表面上的电感器导电图案通过通孔彼此电耦合以形成螺旋形电感器元件。螺旋电感器元件通过形成在底部磁性层中的通孔和形成在多层电感器的侧表面上的电力导电迹线耦合到第一电感器电极。磁通密度降低层可以直接插入底部磁性层的正上方，并且直接位于顶部磁性层的正下方。形成在多层电感器的侧表面上的信号/电力导电迹线提供顶层磁层信号/电源触点和底部磁层信号/电源触点之间的信号/功率布线。顶部外部导电图案以倒装芯片配置容纳半导体芯片。

7. 发明授权

US07843303B2 Multilayer inductor 有权
标题翻译：多层电感
公开(公告)号：US07843303B2
公开(公告)日：2010-11-30
申请号：US12315703
申请日：2008-12-08
申请人： Jun Lu , François Hébert
发明人： Jun Lu , François Hébert
IPC分类号： H01F5/00 , H01F27/04 , H01F27/29 , H01F27/28 , H01F7/06
CPC分类号： H01F17/0013 , H01F27/29 , H01F41/046 , H01L2224/16235 , H01L2924/15311 , Y10T29/4902 , Y10T29/49069 , Y10T29/49073
摘要： A multilayer inductor is disclosed. The multilayer inductor includes a bottom magnetic layer having an external conductive pattern formed on a bottom surface thereof for connection to a substrate such as a printed circuit board. The bottom external conductive pattern includes signal/power contacts and first and second inductor electrodes. A top magnetic layer includes a top external conductive pattern having signal/power contacts and inductor electrode contacts. An inductor conductive pattern formed on the top surfaces of intermediate magnetic layers disposed between the top and bottom magnetic layers are electrically coupled to each other by means of through holes to form a spiral inductor element. The spiral inductor element is coupled to the first inductor electrode by means of a through hole formed in the bottom magnetic layer and to the second inductor electrode by means of power conductive traces formed on side surfaces of the multilayer inductor. Flux density reducing layers may be inserted directly above the bottom magnetic layer and directly below the top magnetic layer. Signal/power conductive traces formed on side surfaces of the multilayer inductor provide signal/power routing between the top magnetic layer signal/power contacts and the bottom magnetic layer signal/power contacts. The top external conductive pattern accommodates a semiconductor chip in a flip chip configuration.
摘要翻译：公开了一种多层电感器。多层电感器包括底部磁性层，其具有形成在其底表面上的外部导电图案，用于连接到诸如印刷电路板的基板。底部外部导电图案包括信号/电源触点和第一和第二电感器电极。顶部磁性层包括具有信号/功率触点和电感器电极触点的顶部外部导电图案。形成在设置在顶部和底部磁性层之间的中间磁性层的顶表面上的电感器导电图案通过通孔彼此电耦合以形成螺旋形电感器元件。螺旋电感器元件通过形成在底部磁性层中的通孔和形成在多层电感器的侧表面上的电力导电迹线耦合到第一电感器电极。磁通密度降低层可以直接插入底部磁性层的正上方，并且直接位于顶部磁性层的正下方。形成在多层电感器的侧表面上的信号/电力导电迹线提供顶层磁层信号/电源触点和底部磁层信号/电源触点之间的信号/功率布线。顶部外部导电图案以倒装芯片配置容纳半导体芯片。

8. 发明授权

US08058961B2 Lead frame-based discrete power inductor 有权
标题翻译：引线框架分立功率电感
公开(公告)号：US08058961B2
公开(公告)日：2011-11-15
申请号：US13021347
申请日：2011-02-04
申请人： François Hébert , Tao Feng , Xiaotian Zhang , Jun Lu
发明人： François Hébert , Tao Feng , Xiaotian Zhang , Jun Lu
IPC分类号： H01F5/00
CPC分类号： H01F17/062
摘要： A lead frame-based discrete power inductor is disclosed. The power inductor includes top and bottom lead frames, the leads of which form a coil around a single closed-loop magnetic core. The coil includes interconnections between inner and outer contact sections of the top and bottom lead frames, the magnetic core being sandwiched between the top and bottom lead frames. Ones of the leads of the top and bottom lead frames have a generally non-linear, stepped configuration such that the leads of the top lead frame couple adjacent leads of the bottom lead frame about the magnetic core to form the coil.
摘要翻译：公开了一种基于引线框架的分立功率电感器。功率电感器包括顶部和底部引线框架，其引线围绕单个闭环磁芯形成线圈。线圈包括顶部和底部引线框架的内部和外部接触部分之间的互连，磁芯夹在顶部和底部引线框架之间。顶部引线框架和底部引线框架的引线的一部分具有大致非线性的阶梯状构造，使得顶部引线框架的引线将底部引线框架的相邻引线围绕磁芯耦合以形成线圈。

9. 发明授权

US08563360B2 Power semiconductor device package and fabrication method 有权
标题翻译：功率半导体器件封装及制造方法
公开(公告)号：US08563360B2
公开(公告)日：2013-10-22
申请号：US12479995
申请日：2009-06-08
申请人： Jun Lu , François Hébert , Kai Liu , Xiaotian Zhang
发明人： Jun Lu , François Hébert , Kai Liu , Xiaotian Zhang
IPC分类号： H01L21/00
CPC分类号： H01L23/492 , H01L23/04 , H01L24/37 , H01L24/40 , H01L25/072 , H01L29/0657 , H01L2224/37011 , H01L2224/40095 , H01L2224/40137 , H01L2224/40139 , H01L2224/73253 , H01L2224/84801 , H01L2224/8485 , H01L2224/97 , H01L2924/00014 , H01L2924/01006 , H01L2924/01015 , H01L2924/01027 , H01L2924/01033 , H01L2924/01074 , H01L2924/014 , H01L2924/12044 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/00 , H01L2224/83 , H01L2224/37099
摘要： A power semiconductor device package includes a conductive assembly including a connecting structure and a semiconductor die having an aperture formed therethrough, the aperture being sized and configured to spacedly receive the connecting structure. In an alternative embodiment, a power semiconductor device package includes a conductive assembly including a connecting structure and a pair of semiconductor die disposed on either side of the connecting structure in spaced relationship thereto.
摘要翻译：功率半导体器件封装包括导电组件，其包括连接结构和具有穿过其形成的孔的半导体管芯，所述孔的尺寸和构造为间隔地接收连接结构。在替代实施例中，功率半导体器件封装包括导电组件，该导电组件包括连接结构和设置在与之间隔开的连接结构的任一侧上的一对半导体管芯。

10. 发明授权

US08302287B2 Method of manufacturing a multilayer inductor 有权
标题翻译：制造多层电感器的方法
公开(公告)号：US08302287B2
公开(公告)日：2012-11-06
申请号：US12891105
申请日：2010-09-27
申请人： Jun Lu , François Hébert
发明人： Jun Lu , François Hébert
IPC分类号： H01F7/06
CPC分类号： H01F17/0013 , H01F27/29 , H01F41/046 , H01L2224/16235 , H01L2924/15311 , Y10T29/4902 , Y10T29/49069 , Y10T29/49073
摘要： A multilayer inductor includes a bottom magnetic layer having an external conductive pattern formed on a bottom surface thereof for connection to a substrate such as a printed circuit board. The bottom external conductive pattern includes signal/power contacts and first and second inductor electrodes. A top magnetic layer includes a top external conductive pattern having signal/power contacts and inductor electrode contacts. An inductor conductive pattern formed on the top surfaces of intermediate magnetic layers disposed between the top and bottom magnetic layers are electrically coupled to each other by means of through holes to form a spiral inductor element.
摘要翻译：多层电感器包括具有形成在其底表面上的外部导电图案的底部磁性层，用于连接到诸如印刷电路板的基板。底部外部导电图案包括信号/电源触点和第一和第二电感器电极。顶部磁性层包括具有信号/功率触点和电感器电极触点的顶部外部导电图案。形成在设置在顶部和底部磁性层之间的中间磁性层的顶表面上的电感器导电图案通过通孔彼此电耦合以形成螺旋形电感器元件。

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