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1. 发明授权

US08482963B1 Integrated circuits with asymmetric and stacked transistors 有权
标题翻译：具有不对称和堆叠晶体管的集成电路
公开(公告)号：US08482963B1
公开(公告)日：2013-07-09
申请号：US12629831
申请日：2009-12-02
申请人： Jun Liu , Yanzhong Xu , Shankar Sinha , Shih-Lin S. Lee , Jeffrey Xiaoqi Tung , Albert Ratnakumar , Qi Xiang , Irfan Rahim , Andy L. Lee , Jeffrey T. Watt , Srinivas Perisetty
发明人： Jun Liu , Yanzhong Xu , Shankar Sinha , Shih-Lin S. Lee , Jeffrey Xiaoqi Tung , Albert Ratnakumar , Qi Xiang , Irfan Rahim , Andy L. Lee , Jeffrey T. Watt , Srinivas Perisetty
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.
摘要翻译：不对称晶体管可以通过在晶体管的一个源极 - 漏极端子上而不是另一个产生凹穴注入来形成。也可以使用具有不同功函数的第一和第二栅极导体的双栅结构来形成非对称晶体管。可以通过堆叠相同通道类型的两个晶体管串联形成堆叠晶体管。两个晶体管中的每一个的源极 - 漏极端子之一连接到公共节点。两个晶体管的栅极也连接在一起。两个晶体管可以具有不同的阈值电压。位于堆叠晶体管中较高的晶体管的阈值电压可以具有比堆叠晶体管中的另一个晶体管更低的阈值电压。堆叠的晶体管可用于减少诸如存储器单元的电路中的漏电流。不对称晶体管也可用于存储器单元中以减少泄漏。

2. 发明授权

US08804407B1 PMOS pass gate 有权
标题翻译： PMOS通孔
公开(公告)号：US08804407B1
公开(公告)日：2014-08-12
申请号：US13181219
申请日：2011-07-12
申请人： Jun Liu , Albert Ratnakumar , Irfan Rahim , Qi Xiang
发明人： Jun Liu , Albert Ratnakumar , Irfan Rahim , Qi Xiang
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , H03K2217/0054
摘要： An IC that includes a memory cell and a pass gate coupled to the memory cell, where the pass gate includes a PMOS transistor, is described. In one implementation, the PMOS transistor has a negative threshold voltage. In one implementation, the memory cell includes thick oxide transistors.
摘要翻译：描述了包括耦合到存储器单元的存储单元和通过栅极的IC，其中栅极包括PMOS晶体管。在一个实现中，PMOS晶体管具有负阈值电压。在一个实现中，存储单元包括厚的氧化物晶体管。

3. 发明授权

US08081502B1 Memory elements with body bias control 有权
标题翻译：记忆元素与身体偏差控制
公开(公告)号：US08081502B1
公开(公告)日：2011-12-20
申请号：US12345560
申请日：2008-12-29
申请人： Irfan Rahim , Jun Liu , Andy L. Lee , William Bradley Vest , Lu Zhou , Qi Xiang , Yanzhong Yu , Jeffrey Xiaoqi Tung , Albert Ratnakumar
发明人： Irfan Rahim , Jun Liu , Andy L. Lee , William Bradley Vest , Lu Zhou , Qi Xiang , Yanzhong Yu , Jeffrey Xiaoqi Tung , Albert Ratnakumar
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： An integrated circuit with memory elements is provided. The memory elements may have memory element transistors with body terminals. Body bias control circuitry may supply body bias voltages that strengthen or weaken memory element transistors to improve read and write margins. The body bias control circuitry may dynamically control body bias voltages so that time-varying body bias voltages are supplied to memory element transistors. Address transistors and latch transistors in the memory elements may be selectively strengthened and weakened. Process variations may be compensated by weakening fast transistors and strengthening slow transistors with body bias adjustments.
摘要翻译：提供了一种具有存储元件的集成电路。存储器元件可以具有带有主体端子的存储器元件晶体管。体偏置控制电路可以提供加强或削弱存储元件晶体管的体偏置电压，以改善读和写余量。体偏置控制电路可以动态地控制体偏置电压，从而将时变体偏置电压提供给存储元件晶体管。存储元件中的地址晶体管和锁存晶体管可以被选择性地加强和削弱。过程变化可以通过削弱快速晶体管和加强具有体偏置调整的慢晶体管来补偿。

4. 发明授权

US08921170B1 Integrated circuits with asymmetric pass transistors 有权
标题翻译：具有不对称传输晶体管的集成电路
公开(公告)号：US08921170B1
公开(公告)日：2014-12-30
申请号：US13408959
申请日：2012-02-29
申请人： Jun Liu , Albert Ratnakumar , Mark T. Chan , Irfan Rahim
发明人： Jun Liu , Albert Ratnakumar , Mark T. Chan , Irfan Rahim
IPC分类号： H01L21/338
CPC分类号： H01L21/823418 , H01L21/324 , H01L21/823814 , H01L27/082 , H01L27/088 , H01L29/1083 , H01L29/6653 , H01L29/66659
摘要： Asymmetric transistors such as asymmetric pass transistors may be formed on an integrated circuit. The asymmetric transistors may have gate structures. Symmetric pocket implants may be formed in source-drains on opposing sides of each transistor gate structure. Selective heating may be used to asymmetrically diffuse the implants. Selective heating may be implemented by patterning the gate structures on a semiconductor substrate so that the spacing between adjacent gate structures varies. A given gate structure may be located between first and second adjacent gate structures spaced at different respective distances from the given gate structure. A larger gate structure spacing leads to a greater substrate temperature rise than a smaller gate structure spacing. The pocket implant diffuses more in portions of the substrate with the greater temperature rise, producing asymmetric transistors. Asymmetric pass transistors may be controlled by static control signals from memory elements to implement circuits such as programmable multiplexers.
摘要翻译：不对称晶体管，例如不对称传输晶体管可以形成在集成电路上。不对称晶体管可以具有栅极结构。可以在每个晶体管栅极结构的相对侧上的源极漏极中形成对称的袋状植入物。选择性加热可用于不对称地扩散植入物。可以通过在半导体衬底上图案化栅极结构来实现选择性加热，使得相邻栅极结构之间的间隔变化。给定的栅极结构可以位于与给定栅极结构不同的相应距离处间隔开的第一和第二相邻栅极结构之间。较大的栅极结构间隔导致比较小栅极结构间隔更大的衬底温度升高。在较大的温度上升的情况下，口袋植入物在衬底的部分扩散，产生不对称晶体管。不对称传输晶体管可以由来自存储器元件的静态控制信号来控制，以实现诸如可编程多路复用器之类的电路。

5. 发明授权

US08138797B1 Integrated circuits with asymmetric pass transistors 有权
标题翻译：具有不对称传输晶体管的集成电路
公开(公告)号：US08138797B1
公开(公告)日：2012-03-20
申请号：US12790660
申请日：2010-05-28
申请人： Jun Liu , Albert Ratnakumar , Mark T. Chan , Irfan Rahim
发明人： Jun Liu , Albert Ratnakumar , Mark T. Chan , Irfan Rahim
IPC分类号： H01L25/00 , H03K19/00
CPC分类号： H01L21/823418 , H01L21/324 , H01L21/823814 , H01L27/082 , H01L27/088 , H01L29/1083 , H01L29/6653 , H01L29/66659
摘要： Asymmetric transistors such as asymmetric pass transistors may be formed on an integrated circuit. The asymmetric transistors may have gate structures. Symmetric pocket implants may be formed in source-drains on opposing sides of each transistor gate structure. Selective heating may be used to asymmetrically diffuse the implants. Selective heating may be implemented by patterning the gate structures on a semiconductor substrate so that the spacing between adjacent gate structures varies. A given gate structure may be located between first and second adjacent gate structures spaced at different respective distances from the given gate structure. A larger gate structure spacing leads to a greater substrate temperature rise than a smaller gate structure spacing. The pocket implant diffuses more in portions of the substrate with the greater temperature rise, producing asymmetric transistors. Asymmetric pass transistors may be controlled by static control signals from memory elements to implement circuits such as programmable multiplexers.
摘要翻译：不对称晶体管，例如不对称传输晶体管可以形成在集成电路上。不对称晶体管可以具有栅极结构。可以在每个晶体管栅极结构的相对侧上的源极漏极中形成对称的袋状植入物。选择性加热可用于不对称地扩散植入物。可以通过在半导体衬底上图案化栅极结构来实现选择性加热，使得相邻栅极结构之间的间隔变化。给定的栅极结构可以位于与给定栅极结构不同的相应距离处间隔开的第一和第二相邻栅极结构之间。较大的栅极结构间隔导致比较小栅极结构间隔更大的衬底温度升高。在较大的温度上升的情况下，口袋植入物在衬底的部分扩散，产生不对称晶体管。不对称传输晶体管可以由来自存储器元件的静态控制信号来控制，以实现诸如可编程多路复用器之类的电路。

6. 发明授权

US08633731B1 Programmable integrated circuit with thin-oxide passgates 有权
标题翻译：可编程集成电路与薄氧化物通风门
公开(公告)号：US08633731B1
公开(公告)日：2014-01-21
申请号：US13206401
申请日：2011-08-09
申请人： Irfan Rahim , Mao Du , Jeffrey Xiaoqi Tung , Jun Liu , Qi Xiang
发明人： Irfan Rahim , Mao Du , Jeffrey Xiaoqi Tung , Jun Liu , Qi Xiang
IPC分类号： G06F7/38
CPC分类号： H03K19/1733 , G11C8/16 , G11C11/419
摘要： Integrated circuits such as programmable integrated circuits may have configuration random-access memory elements. The configuration random-access memory elements may be loaded with configuration data to customize programmable circuitry on the integrated circuits. Each memory element may have a bistable element that is powered using a positive power supply voltage and a negative power supply voltage. Programmable transistors in the programmable circuitry may have gates coupled to outputs of the bistable elements. The programmable transistors may have gate insulators that are thinner than gate insulators in the transistors of the bistable elements and may have threshold voltages of about zero volts. During operation, some of the configuration random-access memory elements may supply negative voltages to their associated programmable transistors so that the programmable transistors are provided with gate-source voltages of less than zero volts.
摘要翻译：诸如可编程集成电路的集成电路可以具有配置随机存取存储器元件。配置随机存取存储器元件可以被加载配置数据以定制集成电路上的可编程电路。每个存储元件可以具有使用正电源电压和负电源电压供电的双稳态元件。可编程电路中的可编程晶体管可以具有耦合到双稳态元件的输出的栅极。可编程晶体管可以具有比双稳态元件的晶体管中的栅极绝缘体更薄的栅极绝缘体，并且可以具有约零伏特的阈值电压。在操作期间，一些配置随机存取存储器元件可以向其相关联的可编程晶体管提供负电压，使得可编程晶体管具有小于零伏的栅极 - 源极电压。

7. 发明授权

US08995175B1 Memory circuit with PMOS access transistors 有权
标题翻译：具有PMOS存取晶体管的存储电路
公开(公告)号：US08995175B1
公开(公告)日：2015-03-31
申请号：US13350575
申请日：2012-01-13
申请人： Jun Liu , Irfan Rahim , Yanzhong Xu , Andy L. Lee
发明人： Jun Liu , Irfan Rahim , Yanzhong Xu , Andy L. Lee
IPC分类号： G11C11/412 , G11C5/14
CPC分类号： G11C5/14 , G11C11/412 , G11C11/418
摘要： A memory circuit that includes a memory storage unit and access transistors coupled to the memory storage unit, where the access transistors include PMOS transistors, is described. In one implementation, the memory circuit further includes a bias clamp transistor coupled to the memory storage unit.
摘要翻译：描述了一种存储器电路，其包括存储器存储单元和耦合到存储器存储单元的存取晶体管，其中存取晶体管包括PMOS晶体管。在一个实现中，存储器电路还包括耦合到存储器存储单元的偏置钳位晶体管。

8. 发明授权

US08611137B2 Memory elements with relay devices 有权
标题翻译：具有中继设备的存储器元件
公开(公告)号：US08611137B2
公开(公告)日：2013-12-17
申请号：US13304226
申请日：2011-11-23
申请人： Lin-Shih Liu , Mark T. Chan , Yanzhong Xu , Irfan Rahim , Jeffrey T. Watt
发明人： Lin-Shih Liu , Mark T. Chan , Yanzhong Xu , Irfan Rahim , Jeffrey T. Watt
IPC分类号： G11C11/00
CPC分类号： G11C11/52 , B82Y10/00 , G11C13/025 , G11C23/00 , H01H1/0094 , H01H1/20 , H01H59/0009 , H01L27/101 , H01L27/11
摘要： Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors. Memory elements configured in this way may be used to provide volatile storage characteristics and SEU immunity.
摘要翻译：提供具有存储元件的集成电路。集成电路可以包括形成在具有互补金属氧化物半导体（CMOS）器件的第一部分中的逻辑电路，并且可以包括形成在具有纳米机电（NEM）器件的第二部分中的存储器元件和相关联的存储器电路的至少一部分，中继设备 NEM和CMOS器件可以通过介电堆叠中的通孔互连。第一和第二部分中的装置可以接收相应的电源电压。在一个合适的布置中，存储器元件可以包括提供非易失性存储特性和软错误失真（SEU）抗扰性的两个继电器开关。在另一种合适的布置中，存储元件可以包括第一和第二交叉耦合反相电路。第一反相电路可以包括继电器开关，而第二反相电路仅包括CMOS晶体管。以这种方式配置的存储器元件可用于提供易失性存储特性和SEU抗扰度。

9. 发明授权

US08030962B2 Configuration random access memory 有权
标题翻译：配置随机存取存储器
公开(公告)号：US08030962B2
公开(公告)日：2011-10-04
申请号：US12868575
申请日：2010-08-25
申请人： Irfan Rahim , Andy L. Lee , Myron Wai Wong , William Bradley Vest , Jeffrey T. Watt
发明人： Irfan Rahim , Andy L. Lee , Myron Wai Wong , William Bradley Vest , Jeffrey T. Watt
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , G11C11/401 , G11C11/404 , G11C14/00 , H03K19/1778
摘要： Integrated circuits such as programmable logic device integrated circuits are provided that have configuration random-access memory elements. The configuration random-access memory elements are loaded with configuration data to customize programmable logic on the integrated circuits. Each memory element has a capacitor that stores data for that memory element. A pair of cross-coupled inverters are connected to the capacitor. The inverters ensure that the memory elements produce output control signals with voltages than range from one power supply rail to another. Each configuration random-access memory element may have a clear transistor. The capacitor may be formed in a dielectric layer that lies above the transistors of the inverters, the address transistor, and the clear transistor. The inverters may be powered with an elevated power supply voltage.
摘要翻译：提供了诸如可编程逻辑器件集成电路的集成电路，其具有配置随机存取存储器元件。配置随机存取存储器元件装载有配置数据以在集成电路上定制可编程逻辑。每个存储器元件具有存储该存储器元件的数据的电容器。一对交叉耦合的反相器连接到电容器。逆变器确保存储元件产生的输出控制信号的电压低于从一个电源轨到另一个电源的范围。每个配置随机存取存储器元件可以具有透明晶体管。电容器可以形成在位于反相器，地址晶体管和透明晶体管的晶体管之上的电介质层中。逆变器可以用升高的电源电压供电。

10. 发明授权

US07902611B1 Integrated circuit well isolation structures 有权
标题翻译：集成电路阱隔离结构
公开(公告)号：US07902611B1
公开(公告)日：2011-03-08
申请号：US11998016
申请日：2007-11-27
申请人： Irfan Rahim , Bradley Jensen , Peter J. McElheny
发明人： Irfan Rahim , Bradley Jensen , Peter J. McElheny
IPC分类号： H01L21/70 , H01L23/52 , H01L29/00
CPC分类号： H01L27/0928 , H01L21/76224 , H01L21/765 , H01L21/823878 , H01L21/823892
摘要： An integrated circuit is provided with transistor body regions that may be independently biased. Some of the bodies may be forward body biased to lower threshold voltages and increase transistor switching speed. Some of the bodies may be reverse body biased to increase threshold voltages and decrease leakage current. The integrated circuit may be formed on a silicon substrate. Body bias isolation structures may be formed in the silicon substrate to isolate the bodies from each other. Body bias isolation structures may be formed from shallow trench isolation trenches. Doped regions may be formed at the bottom of the trenches using ion implantation. Oxide may be used to fill the trenches above the doped region. A deep well may be formed under the body regions. The deep well may contact the doped regions that are formed at the bottom of the trenches.
摘要翻译：集成电路设置有可独立偏置的晶体管本体区域。一些物体可能被向前偏置，以降低阈值电压并增加晶体管切换速度。一些物体可能被反向体偏置以增加阈值电压并减小漏电流。集成电路可以形成在硅衬底上。可以在硅衬底中形成体偏置隔离结构以将体彼此隔离。体偏置隔离结构可以由浅沟槽隔离沟槽形成。可以使用离子注入在沟槽的底部形成掺杂区域。氧化物可用于填充掺杂区域上方的沟槽。可以在身体区域下方形成深井。深阱可以接触形成在沟槽底部的掺杂区域。

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