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1. 发明申请

US20150067248A1 DRAM CONTROLLER HAVING DRAM BAD PAGE MANAGEMENT FUNCTION AND BAD PAGE MANAGEMENT METHOD THEREOF 有权
标题翻译：具有DRAM边缘页管理功能的DRAM控制器及其页面管理方法
公开(公告)号：US20150067248A1
公开(公告)日：2015-03-05
申请号：US14465105
申请日：2014-08-21
申请人： Jun Hee Yoo , Sung Hyun Lee , Dongsoo Kang , Sua Kim , Haksoo Yu , Jaeyoun Youn , Hyojin Choi
发明人： Jun Hee Yoo , Sung Hyun Lee , Dongsoo Kang , Sua Kim , Haksoo Yu , Jaeyoun Youn , Hyojin Choi
IPC分类号： G06F12/10
CPC分类号： G06F11/00 , G11C8/06 , G11C11/401 , G11C29/78 , G11C2029/4402
摘要： A bad page management system is provided to guarantee a yield of a volatile semiconductor memory device such as a DRAM. A bad page list exists in a DRAM. A page remapper in a memory controller performs a page remapping operation in parallel with a normal operation of a scheduling unit to perform a latency overhead hidden function. A chip size of the DRAM is reduced or minimized. A DRAM controller performs a latency overhead hidden function to control a DRAM.
摘要翻译：提供了不良页面管理系统以保证诸如DRAM之类的易失性半导体存储器件的产量。 DRAM中存在不良页面列表。存储器控制器中的页面重新映射器与调度单元的正常操作并行执行页面重映射操作，以执行延迟开销隐藏功能。 DRAM的芯片尺寸减小或最小化。 DRAM控制器执行延迟开销隐藏功能来控制DRAM。

2. 发明申请

US20150081989A1 SEMICONDUCTOR DEVICES INCLUDING APPLICATION PROCESSOR CONNECTED TO HIGH-BANDWIDTH MEMORY AND LOW-BANDWIDTH MEMORY, AND CHANNEL INTERLEAVING METHOD THEREOF 有权
标题翻译：包括连接到高带宽存储器和低带宽存储器的应用处理器的半导体器件及其通道交换方法
公开(公告)号：US20150081989A1
公开(公告)日：2015-03-19
申请号：US14307994
申请日：2014-06-18
申请人： Sung Hyun Lee , Jun Hee Yoo , Dongsoo Kang , Il Park , Kiyeon Lee , Euicheol Lim
发明人： Sung Hyun Lee , Jun Hee Yoo , Dongsoo Kang , Il Park , Kiyeon Lee , Euicheol Lim
IPC分类号： G06F12/06
CPC分类号： G06F12/0607 , Y02D10/13
摘要： A memory system includes a high-bandwidth memory device, the high-bandwidth memory device having a relatively high operation bandwidth, the high-bandwidth memory device having a plurality of access channels. A low-bandwidth memory device has a relatively low operation bandwidth relative to the high-bandwidth memory device, the low-bandwidth memory device having one or more access channels. An interleaving unit performs a memory interleave operation among the plurality of access channels of the high-bandwidth memory device and an access channel of the one or more access channels of the low-bandwidth memory device.
摘要翻译：存储器系统包括高带宽存储器件，具有相对高的操作带宽的高带宽存储器件，高带宽存储器件具有多个存取通道。低带宽存储器件相对于高带宽存储器件具有相对低的操作带宽，低带宽存储器件具有一个或多个存取通道。交织单元在高带宽存储装置的多个接入信道和低带宽存储装置的一个以上的接入信道的接入信道之间进行存储器交织操作。

3. 发明授权

US08645791B2 Data cache controller, devices having the same, and method of operating the same 有权
标题翻译：数据缓存控制器，具有相同功能的设备及其操作方法
公开(公告)号：US08645791B2
公开(公告)日：2014-02-04
申请号：US13446345
申请日：2012-04-13
申请人： Sung Hyun Lee , Jun Hee Yoo
发明人： Sung Hyun Lee , Jun Hee Yoo
IPC分类号： H03M13/00 , G11C29/00
CPC分类号： G06F12/0855 , G06F11/1064
摘要： An method of operating a data cache controller is provided. The method includes transmitting first data output from a data cache to a central processing unit (CPU) core with a first latency and transmitting second data to the CPU core with a second latency greater than the first latency. The first latency is a delay between a read request to the data cache and transmission of the first data according to execution of a first instruction fetched from an instruction cache, and the second latency is a delay between a read request to the data cache and transmission of the second data according to execution of a second instruction fetched from the instruction cache.
摘要翻译：提供了一种操作数据高速缓存控制器的方法。该方法包括以第一等待时间将从数据高速缓存输出的第一数据传输到中央处理单元（CPU）核心，并以大于第一等待时间的第二等待时间向CPU核发送第二数据。第一等待时间是根据从指令高速缓存取出的第一指令的执行，对数据高速缓存的读取请求和第一数据的传输之间的延迟，并且第二等待时间是对数据高速缓存和传输的读请求之间的延迟根据从指令高速缓存取出的第二指令的执行来执行第二数据。

4. 发明申请

US20130117627A1 DATA CACHE CONTROLLER, DEVICES HAVING THE SAME, AND METHOD OF OPERATING THE SAME 有权
标题翻译：数据缓存控制器，具有该数据缓存控制器的设备及其操作方法
公开(公告)号：US20130117627A1
公开(公告)日：2013-05-09
申请号：US13446345
申请日：2012-04-13
申请人： Sung Hyun Lee , Jun Hee Yoo
发明人： Sung Hyun Lee , Jun Hee Yoo
IPC分类号： G06F11/08 , G06F12/08
CPC分类号： G06F12/0855 , G06F11/1064
摘要： An method of operating a data cache controller is provided. The method includes transmitting first data output from a data cache to a central processing unit (CPU) core with a first latency and transmitting second data to the CPU core with a second latency greater than the first latency. The first latency is a delay between a read request to the data cache and transmission of the first data according to execution of a first instruction fetched from an instruction cache, and the second latency is a delay between a read request to the data cache and transmission of the second data according to execution of a second instruction fetched from the instruction cache.
摘要翻译：提供了一种操作数据高速缓存控制器的方法。该方法包括以第一等待时间将从数据高速缓存输出的第一数据传输到中央处理单元（CPU）核心，并以大于第一等待时间的第二等待时间向CPU核发送第二数据。第一等待时间是根据从指令高速缓存取出的第一指令的执行，对数据高速缓存的读取请求和第一数据的传输之间的延迟，并且第二等待时间是对数据高速缓存和传输的读请求之间的延迟根据从指令高速缓存取出的第二指令的执行来执行第二数据。

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