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1. 发明授权

US07086015B2 Method of optimizing RTL code for multiplex structures 失效
标题翻译：优化多路复用结构的RTL码的方法
公开(公告)号：US07086015B2
公开(公告)日：2006-08-01
申请号：US10844664
申请日：2004-05-12
申请人： Juergen Lahner , Kiran Atkmakuri , Kavitha Chaturvedula
发明人： Juergen Lahner , Kiran Atkmakuri , Kavitha Chaturvedula
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method and computer program are disclosed for optimizing RTL code for an integrated circuit design that include steps of: (a) receiving as input a first register transfer level code for an integrated circuit design; (b) receiving as input a user defined optimum multiplex structure; (c) analyzing the first register transfer level code to identify a critical multiplex structure; (d) partitioning the global multiplex structure into local multiplex structures each identical to the user defined optimum multiplex structure; and (e) generating as output a second register transfer level code for the integrated circuit design that replaces the global multiplex structure with the local multiplex structures.
摘要翻译：公开了一种用于优化用于集成电路设计的RTL代码的方法和计算机程序，其包括以下步骤：（a）作为输入接收用于集成电路设计的第一寄存器传送级代码; （b）接收用户定义的最佳多路复用结构作为输入; （c）分析第一寄存器传送级代码以识别关键的多路复用结构; （d）将全局多路复用结构划分为与用户定义的最佳多路复用结构相同的本地多路复用结构; 以及（e）为所述集成电路设计产生用本地多路复用结构代替所述全局多路复用结构的第二寄存器传送级代码作为输出。

2. 发明申请

US20050257180A1 Method of optimizing RTL code for multiplex structures 失效
标题翻译：优化多路复用结构的RTL码的方法
公开(公告)号：US20050257180A1
公开(公告)日：2005-11-17
申请号：US10844664
申请日：2004-05-12
申请人： Juergen Lahner , Kiran Atmakuri , Kavitha Chaturvedula
发明人： Juergen Lahner , Kiran Atmakuri , Kavitha Chaturvedula
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method and computer program are disclosed for optimizing RTL code for an integrated circuit design that include steps of: (a) receiving as input a first register transfer level code for an integrated circuit design; (b) receiving as input a user defined optimum multiplex structure; (c) analyzing the first register transfer level code to identify a critical multiplex structure; (d) partitioning the global multiplex structure into local multiplex structures each identical to the user defined optimum multiplex structure; and (e) generating as output a second register transfer level code for the integrated circuit design that replaces the global multiplex structure with the local multiplex structures.
摘要翻译：公开了一种用于优化用于集成电路设计的RTL代码的方法和计算机程序，其包括以下步骤：（a）作为输入接收用于集成电路设计的第一寄存器传送级代码; （b）接收用户定义的最佳多路复用结构作为输入; （c）分析第一寄存器传送级代码以识别关键的多路复用结构; （d）将全局多路复用结构划分为与用户定义的最佳多路复用结构相同的本地多路复用结构; 以及（e）为所述集成电路设计产生用本地多路复用结构代替所述全局多路复用结构的第二寄存器传送级代码作为输出。

3. 发明授权

US07082584B2 Automated analysis of RTL code containing ASIC vendor rules 有权
标题翻译：自动分析包含ASIC供应商规则的RTL代码
公开(公告)号：US07082584B2
公开(公告)日：2006-07-25
申请号：US10427609
申请日：2003-04-30
申请人： Juergen Lahner , Kiran Atmakuri , Kavitha Chaturvedula , Balamurugan Balasubramanian , Krishna Devineni , Srinivas Adusumalli , Randall P. Fry , Gregory A. Pierce
发明人： Juergen Lahner , Kiran Atmakuri , Kavitha Chaturvedula , Balamurugan Balasubramanian , Krishna Devineni , Srinivas Adusumalli , Randall P. Fry , Gregory A. Pierce
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method of automatically analyzing RTL code includes receiving as input RTL code for an integrated circuit design. An RTL platform is selected that incorporates design rules for a vendor of the integrated circuit design. The design rules are displayed from the RTL platform on a graphic user interface. A number of the design rules are selected from the graphic user interface. An analysis is performed in the RTL platform of the RTL code for each of the selected design rules. A result of the analysis is generated as output for each of the selected design rules.
摘要翻译：一种自动分析RTL代码的方法包括接收集成电路设计的输入RTL代码。选择了一种集成电路设计供应商的设计规则的RTL平台。设计规则从图形用户界面的RTL平台显示。从图形用户界面中选择了多个设计规则。在RTL代码的RTL平台中对每个选定的设计规则进行分析。生成分析结果作为每个选定设计规则的输出。

4. 发明申请

US20070079266A1 Method and computer program for analysis of an integrated circuit design to identify and resolve a problematic structure characterized by multiple rule violations using a design closure knowledge base and a physical design database 审中-公开
标题翻译：用于分析集成电路设计的方法和计算机程序，以使用设计闭包知识库和物理设计数据库来识别和解决以多规则违规为特征的有问题的结构
公开(公告)号：US20070079266A1
公开(公告)日：2007-04-05
申请号：US11241033
申请日：2005-09-30
申请人： Krishna Devineni , Juergen Lahner , Gregory Pierce , Balamurugan Balasubramanian , Srinivas Adusumalli , Kiran Atmakuri , Kavitha Chaturvedula , Randall Fry
发明人： Krishna Devineni , Juergen Lahner , Gregory Pierce , Balamurugan Balasubramanian , Srinivas Adusumalli , Kiran Atmakuri , Kavitha Chaturvedula , Randall Fry
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method and computer program product analyzes an integrated circuit design to identify and resolve a problematic structure characterized by multiple rule violations uses a Design Closure Knowledge Base to generate a corrective action strategy in a Design Closure Guidance Report. In one embodiment, a method includes steps of receiving as input an integrated circuit design and a set of design rules, analyzing the integrated circuit design to identify design rule violations, and generating as output a compilation of each of the design rule violations and a corresponding list of primary and secondary objects in the integrated circuit design for each of the design rule violations. The compilation of each of the design rule violations and the corresponding list of primary and secondary objects in the integrated circuit design for each of the design rule violations is included in a Design Closure Knowledge Base to generate a detailed and structured strategy for resolving the design rule violations in the Design Closure Guidance Report.
摘要翻译：一种方法和计算机程序产品分析集成电路设计，以识别和解决以多规则违规为特征的有问题的结构，使用设计闭合知识库在“设计闭合指导报告”中生成纠正措施策略。在一个实施例中，一种方法包括以下步骤：接收集成电路设计和一组设计规则作为输入，分析集成电路设计以识别设计规则违反，以及生成作为输出的每个设计规则违规的汇编以及对应的集成电路设计中的每个设计规则违规的主要和次要对象列表。每个设计规则违规的汇编以及每个设计规则违规的集成电路设计中的主要和次要对象的相应列表都包含在设计闭包知识库中，以生成详细和结构化的解决设计规则的策略违反设计关闭指引报告。

5. 发明授权

US07594201B2 Enhanced method of optimizing multiplex structures and multiplex control structures in RTL code 失效
标题翻译：在RTL代码中优化多路复用结构和多路复用控制结构的增强方法
公开(公告)号：US07594201B2
公开(公告)日：2009-09-22
申请号：US11460680
申请日：2006-07-28
申请人： Juergen Lahner , Kiran Atmakuri , Kavitha Chaturvedula
发明人： Juergen Lahner , Kiran Atmakuri , Kavitha Chaturvedula
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5054 , G06F17/5077
摘要： A method and computer program are disclosed for optimizing RTL code for an integrated circuit design that include steps of method of optimizing register transfer level code for an integrated circuit design comprising steps of receiving as input a first register transfer level code for the integrated circuit design and receiving as input criteria defining a critical multiplex structure. The first register transfer level code is analyzed to identify multiplex structures in the first register transfer level code. Each of the multiplex structures identified in the first register transfer level code is compared to the criteria defining a critical multiplex structure. Each of the multiplex structures identified in the first register transfer level code that satisfy the criteria defining a critical multiplex structure is entered in a list of critical multiplex structures. The list of critical multiplex structures is generated as output.
摘要翻译：公开了一种用于优化用于集成电路设计的RTL代码的方法和计算机程序，其包括用于集成电路设计的优化寄存器传送级代码的方法的步骤，包括以下步骤：接收用于集成电路设计的第一寄存器传送级代码和接收作为定义关键多路复用结构的输入标准。分析第一个寄存器传送电平代码以识别第一个寄存器传输电平代码中的多路复用结构。将在第一寄存器传送级代码中识别的多路复用结构中的每一个与定义关键复用结构的标准进行比较。在第一寄存器传送级代码中识别的满足定义关键复用结构的标准的多路复用结构中的每一个被输入到关键多路复用结构的列表中。关键复用结构列表作为输出生成。

6. 发明申请

US20060282801A1 ENHANCED METHOD OF OPTIMIZING MULTIPLEX STRUCTURES AND MULTIPLEX CONTROL STRUCTURES IN RTL CODE 失效
标题翻译：在RTL代码中优化多重结构和多重控制结构的增强方法
公开(公告)号：US20060282801A1
公开(公告)日：2006-12-14
申请号：US11460680
申请日：2006-07-28
申请人： Juergen Lahner , Kiran Atmakuri , Kavitha Chaturvedula
发明人： Juergen Lahner , Kiran Atmakuri , Kavitha Chaturvedula
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5054 , G06F17/5077
摘要： A method and computer program are disclosed for optimizing RTL code for an integrated circuit design that include steps of method of optimizing register transfer level code for an integrated circuit design comprising steps of receiving as input a first register transfer level code for the integrated circuit design and receiving as input criteria defining a critical multiplex structure. The first register transfer level code is analyzed to identify multiplex structures in the first register transfer level code. Each of the multiplex structures identified in the first register transfer level code is compared to the criteria defining a critical multiplex structure. Each of the multiplex structures identified in the first register transfer level code that satisfy the criteria defining a critical multiplex structure is entered in a list of critical multiplex structures. The list of critical multiplex structures is generated as output.
摘要翻译：公开了一种用于优化用于集成电路设计的RTL代码的方法和计算机程序，其包括用于集成电路设计的优化寄存器传输级代码的方法的步骤，包括以下步骤：接收用于集成电路设计的第一寄存器传送级代码和接收作为定义关键多路复用结构的输入标准。分析第一个寄存器传送电平代码以识别第一个寄存器传输电平代码中的多路复用结构。将在第一寄存器传送级代码中识别的多路复用结构中的每一个与定义关键复用结构的标准进行比较。在第一寄存器传送级代码中识别的满足定义关键复用结构的标准的多路复用结构中的每一个被输入到关键多路复用结构的列表中。关键复用结构列表作为输出生成。

7. 发明授权

US07380228B2 Method of associating timing violations with critical structures in an integrated circuit design 失效
标题翻译：将定时违规与集成电路设计中的关键结构相关联的方法
公开(公告)号：US07380228B2
公开(公告)日：2008-05-27
申请号：US10984115
申请日：2004-11-08
申请人： Randall P. Fry , Gregory Pierce , Juergen Lahner
发明人： Randall P. Fry , Gregory Pierce , Juergen Lahner
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5031
摘要： A method and computer program product for associating timing violations with critical structures in an integrated circuit design include steps of: (a) receiving as input an integrated circuit design; (b) identifying a critical structure in the integrated circuit design; and (c) generating as output a script for a static timing analysis tool that includes a timing check for a path having a start point at an input of the critical structure and an end point at an output of the critical structure.
摘要翻译：一种用于将定时违规与关键结构相关联的集成电路设计的方法和计算机程序产品包括以下步骤：（a）作为输入接收集成电路设计; （b）识别集成电路设计中的关键结构; 以及（c）生成用于静态时序分析工具的输出脚本，该工具包括对关键结构的输入端具有起始点的路径的定时检查以及临界结构输出端的终点。

8. 发明授权

US06546538B1 Integrated circuit having on-chip capacitors for supplying power to portions of the circuit requiring high-transient peak power 有权
标题翻译：具有用于向需要高瞬态峰值功率的电路的部分供电的片上电容器的集成电路
公开(公告)号：US06546538B1
公开(公告)日：2003-04-08
申请号：US09523224
申请日：2000-03-10
申请人： Shalini Rubdi , Stefan Graef , Juergen Lahner
发明人： Shalini Rubdi , Stefan Graef , Juergen Lahner
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： Provided is an integrated circuit (IC) device that includes a semiconductor substrate on which electronic components are formed and multiple metal layers on which wires are routed. Formed on the multiple metal layers is a capacitor that includes a first plate formed on a first metal layer and a second plate formed on a second metal layer that is adjacent to the first metal layer. An area in which the first plate and the second plate overlap has a width of at least twice the width of a typical wire on the IC device. Also provided is a technique for supplying power and ground to locations on an integrated circuit (IC) device that has multiple metal layers for routing wires and a substrate for forming electronic components. Initially, the technique identifies an overlap area where two of the multiple metal layers that are adjacent to each other have open space. A plate is then formed in the overlap area of each of the two metal layers so as to construct a capacitor. Then, one plate of the capacitor is connected to power, the other plate of the capacitor is connected to ground, and the plates of the capacitor are also connected to locations on the substrate of the IC device.
摘要翻译：提供了一种集成电路（IC）装置，其包括其上形成有电子部件的半导体基板和布线有多个金属层。在多个金属层上形成的电容器包括形成在第一金属层上的第一板和形成在与第一金属层相邻的第二金属层上的第二板。第一板和第二板重叠的区域的宽度至少是IC器件上典型导线宽度的两倍。还提供了一种用于向具有用于布线的多个金属层的集成电路（IC）装置和用于形成电子部件的基板的集成电路（IC）装置的位置供电和接地的技术。最初，该技术识别彼此相邻的多个金属层中的两个具有开放空间的重叠区域。然后在两个金属层中的每一个的重叠区域中形成一个板，以构成电容器。然后，电容器的一个板连接到电源，电容器的另一个板连接到地，并且电容器的板也连接到IC器件的基板上的位置。

9. 发明申请

US20070083839A1 On-the-fly RTL instructor for advanced DFT and design closure 失效
标题翻译：高效DFT和设计关闭的即时RTL教练
公开(公告)号：US20070083839A1
公开(公告)日：2007-04-12
申请号：US11247630
申请日：2005-10-11
申请人： Juergen Lahner , Juergen Dirks , Balamurugan Balasubramanian
发明人： Juergen Lahner , Juergen Dirks , Balamurugan Balasubramanian
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5045
摘要： A method for developing a circuit design is disclosed. The method generally includes the steps of (A) editing a file for a circuit design based on a plurality of edits received from a designer, the file containing a code written in a hardware description language, (B) characterizing the code in the file while the designer is editing the code to generate a plurality of characterization results and (C) generating a plurality of suggestions to the designer to modify the code based on a comparison of a plurality of goals for the circuit design and the characterization results.
摘要翻译：公开了一种开发电路设计的方法。该方法通常包括以下步骤：（A）基于从设计者接收的多个编辑来编辑用于电路设计的文件，该文件包含用硬件描述语言编写的代码，（B）表征文件中的代码，同时设计人员正在编辑代码以生成多个表征结果;（C）基于对于电路设计和表征结果的多个目标的比较，向设计者生成多个建议以修改代码。

10. 发明授权

US06907588B2 Congestion estimation for register transfer level code 失效
标题翻译：寄存器传输级代码的拥塞估计
公开(公告)号：US06907588B2
公开(公告)日：2005-06-14
申请号：US10334743
申请日：2002-12-31
申请人： Balamurugan Balasubramanian , Juergen Lahner , Srinivas Adusumalli
发明人： Balamurugan Balasubramanian , Juergen Lahner , Srinivas Adusumalli
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method of estimating congestion for register transfer level code includes steps for receiving as input a floor plan mapped from the register transfer level code, identifying regions in the floor plan, computing routing demand numbers for the regions in the floor plan, computing routing resource numbers for the regions in the floor plan, and generating a congestion estimate of the register transfer level code as a function of the routing demand numbers and the routing resource numbers.
摘要翻译：估计寄存器传送级代码的拥塞的方法包括以下步骤：接收作为输入的从寄存器传送级代码映射的平面图，识别平面图中的区域，计算平面图中的区域的路由需求数，计算路由资源号对于平面图中的区域，并且根据路由需求号码和路由资源号码生成寄存器传送级别代码的拥塞估计。

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