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1. 发明授权

US6061360A Method and apparatus for preserving loop fairness with dynamic half-duplex 有权
标题翻译：用动态半双工保持环路公平性的方法和装置
公开(公告)号：US6061360A
公开(公告)日：2000-05-09
申请号：US256108
申请日：1999-02-24
申请人： Michael H. Miller , Judy Lynn Westby
发明人： Michael H. Miller , Judy Lynn Westby
IPC分类号： H04J3/02 , H04L12/433 , H04L12/56
CPC分类号： H04L12/5602 , H04L12/433
摘要： A method and apparatus for preserving loop fairness. Some embodiments include a dynamic half-duplex feature. One aspect includes a communications channel system and method for preserving loop fairness that includes a first channel node having one or more ports, each port supporting and attached to a fiber-channel arbitrated-loop serial communications channel. One of the ports will arbitrate for control of that port's attached channel, wherein control of the channel loop, once arbitration is won, a fairness-preserving apparatus causes control of the communications channel to be released based at least in part on whether a predetermined amount of use has occurred between the first port and the communications channel. In some embodiments, the predetermined amount of use includes a transfer of a first predetermined amount of data. In some embodiments, release of control of the channel is inhibited if less than a second predetermined amount of data remains to be transferred.
摘要翻译：一种保护环路公平性的方法和装置。一些实施例包括动态半双工特征。一个方面包括用于保持环路公平性的通信信道系统和方法，该通信信道系统和方法包括具有一个或多个端口的第一信道节点，每个端口支持并附加到光纤信道仲裁环路串行通信信道。其中一个端口将仲裁用于控制该端口附加的信道，其中一旦仲裁被赢得，信道环路的控制就是至少部分地基于是否预定的量来保证通信信道的控制被释放的使用发生在第一个端口和通信信道之间。在一些实施例中，预定的使用量包括传送第一预定量的数据。在一些实施例中，如果小于第二预定量的数据仍然要传送，则禁止释放信道的控制。

2. 再颁专利

USRE42228E1 Method and apparatus for using data protection code for data integrity in on-chip memory 有权
标题翻译：使用片上存储器中的数据完整性的数据保护代码的方法和装置
公开(公告)号：USRE42228E1
公开(公告)日：2011-03-15
申请号：US10723963
申请日：2003-11-26
申请人： Judy Lynn Westby , Michael H. Miller
发明人： Judy Lynn Westby , Michael H. Miller
IPC分类号： G06F11/08
CPC分类号： H04L1/0061 , G06F3/0619 , G06F3/0656 , G06F3/0689 , G06F11/1004 , G06F11/2007 , G06F13/368 , G11B5/012 , H04L1/246 , H04L12/42 , H04L45/02 , H04L45/12 , H04L45/48 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9073
摘要： Cyclic-redundancy-code (“CRC”) information that is received along with a frame from a fiber-channel is stored in an on-chip frame buffer, and later checked to ensure the integrity of the data while in the frame buffer. In various embodiments, data frames, along with their CRC information, are stored into a data-frame buffer, and/or non-data frames along with their CRC information are stored into a receive-non-data-frame buffer. The improved communications channel system includes a channel node having dual ports, each port supporting a fiber-channel arbitrated-loop serial communications channel. The serial communications channels each include CRC on data transmissions on the channel, an on-chip frame memory located on-chip in the channel node that receives a data frame and the frame's associated CRC from the communications channel, and an integrity apparatus that later uses the received associated CRC for data-integrity checking of data in the on-chip frame memory. In addition, a method for using CRC for data integrity in on-chip memory is described.
摘要翻译：与光纤信道的帧一起接收的循环冗余码（“CRC”）信息被存储在片上帧缓冲器中，并且稍后检查以确保在帧缓冲器中数据的完整性。在各种实施例中，数据帧及其CRC信息被存储到数据帧缓冲器中，和/或非数据帧及其CRC信息被存储在接收非数据帧缓冲器中。改进的通信信道系统包括具有双端口的信道节点，每个端口支持光纤信道仲裁环路串行通信信道。串行通信信道各自包括在信道上的数据传输上的CRC，位于信道节点中片上的片上帧存储器，其接收来自通信信道的数据帧和帧的相关联的CRC，以及后来使用的完整性装置所接收的相关CRC用于片内帧存储器中数据的完整性检查。另外，描述了在片上存储器中使用CRC用于数据完整性的方法。

3. 再颁专利

USRE40034E1 Method and apparatus to reduce serial communications path connection overhead 有权
公开(公告)号：USRE40034E1
公开(公告)日：2008-01-22
申请号：US10714478
申请日：2003-11-13
申请人： Judy Lynn Westby , Michael H. Miller
发明人： Judy Lynn Westby , Michael H. Miller
IPC分类号： G06F13/14
CPC分类号： H04L1/0061 , G06F3/0619 , G06F3/0656 , G06F3/0689 , G06F11/1004 , G06F11/2007 , G06F13/368 , G11B5/012 , H04L1/246 , H04L12/42 , H04L45/02 , H04L45/12 , H04L45/48 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9073
摘要： Control of a loop of a fiber-channel arbitrated-loop serial communications channel is maintained (i.e., the loop connection is held open) as long as a minimum amount of data, which optionally is determined by programming (called a “programmable amount of data”), is available for transmission, in order to reduce the overall amount of time spent arbitrating for control of the loop. The improved communications channel system includes a channel node having one or more ports, each port supporting a fiber-channel arbitrated-loop serial communications channel loop, wherein each port arbitrates for control of that port's attached channel loop. The system also includes an arbitration-and-control apparatus to reduce arbitrated-loop overhead, wherein control of the channel loop, once control is achieved by arbitration, is maintained by the arbitration-and-control apparatus as long as a predetermined amount of data is available within control of the node. In addition, a method to reduce arbitrated-loop overhead is described. Control of a serial communications path is maintained (i.e., the connection is held open) as long as a minimum amount of data, which optionally is determined by programming (called a “programmable amount of data”), is available for transmission, in order to reduce the overall amount of time spent opening the connection to the serial communications path. The system includes a serial device having n ports (where n equals one or more), each port supporting a serial communications path. Each port arbitrates for control of that port's attached serial communications path. The system also includes an arbitration-and-control apparatus, wherein control of the serial communications path, once control is achieved, is maintained by the arbitration-and-control apparatus as long as a predetermined amount of data is available within control of the serial device. In addition, a method to reduce connection overhead is described.

4. 发明授权

US06317800B1 System for reducing arbitrated-loop overhead by maintaining control of a communications channel as long as a predetermined amount of data is available within control of channel node 失效
标题翻译：只要预定数量的数据在信道节点的控制范围内可用，通过维持通信信道的控制来减少仲裁环路开销的系统
公开(公告)号：US06317800B1
公开(公告)日：2001-11-13
申请号：US09193482
申请日：1998-11-17
申请人： Judy Lynn Westby , Michael H. Miller
发明人： Judy Lynn Westby , Michael H. Miller
IPC分类号： G06F1314
CPC分类号： H04L1/0061 , G06F3/0619 , G06F3/0656 , G06F3/0689 , G06F11/1004 , G06F11/2007 , G06F13/368 , G11B5/012 , H04L1/246 , H04L12/42 , H04L45/02 , H04L45/12 , H04L45/48 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9073
摘要： Control of a loop of a fiber-channel arbitrated-loop serial communications channel is maintained (i.e., the loop connection is held open) as long as a minimum amount of data, which optionally is determined by programming (called a “programmable amount of data”), is available for transmission, in order to reduce the overall amount of time spent arbitrating for control of the loop. The improved communications channel system includes a channel node having one or more ports, each port supporting a fiber-channel arbitrated-loop serial communications channel loop, wherein each port arbitrates for control of that port's attached channel loop. The system also includes an arbitration-and-control apparatus to reduce arbitrated-loop overhead, wherein control of the channel loop, once control is achieved by arbitration, is maintained by the arbitration-and-control apparatus as long as a predetermined amount of data is available within control of the node. In addition, a method to reduce arbitrated-loop overhead is described.
摘要翻译：只要最小数量的数据（可选地由编程确定）（称为“可编程数据量”）即可维持光纤信道仲裁环路串行通信信道的环路的控制（即，环路连接保持打开） “），可用于传输，以便减少仲裁控制循环所花费的总时间。改进的通信信道系统包括具有一个或多个端口的信道节点，每个端口支持光纤信道仲裁环路串行通信信道环路，其中每个端口仲裁用于控制该端口的附加信道环路。该系统还包括一个减少仲裁环路开销的仲裁和控制装置，其中一旦通过仲裁实现控制就可以通过仲裁控制装置来维持信道环路的控制，只要预定量的数据在节点的控制下可用。另外，描述了减少仲裁环路开销的方法。

5. 发明授权

US06553036B1 Method and apparatus for preserving loop fairness with dynamic half-duplex 有权
标题翻译：用动态半双工保持环路公平性的方法和装置
公开(公告)号：US06553036B1
公开(公告)日：2003-04-22
申请号：US09567174
申请日：2000-05-08
申请人： Michael H. Miller , Judy Lynn Westby
发明人： Michael H. Miller , Judy Lynn Westby
IPC分类号： H04J302
CPC分类号： H04L12/5602 , H04L12/433
摘要： A method and apparatus for preserving loop fairness. Some embodiments include a dynamic half-duplex feature. One aspect includes a communications channel system and method for preserving loop fairness that includes a first channel node having one or more ports, each port supporting and attached to a fibre-channel arbitrated-loop serial communications channel. One of the ports will arbitrate for control of that port's attached channel, wherein control of the channel loop, once arbitration is won, a fairness-preserving apparatus causes control of the communications channel to be released based at least in part on whether a predetermined amount of use has occurred between the first port and the communications channel. In some embodiments, the predetermined amount of use includes a transfer of a first predetermined amount of data. In some embodiments, release of control of the channel is inhibited if less than a second predetermined amount of data remains to be transferred.
摘要翻译：一种保护环路公平性的方法和装置。一些实施例包括动态半双工特征。一个方面包括用于保持环路公平性的通信信道系统和方法，该通信信道系统和方法包括具有一个或多个端口的第一信道节点，每个端口支持并附加到光纤信道仲裁环路串行通信信道。其中一个端口将仲裁用于控制该端口附加的信道，其中一旦仲裁被赢得，信道环路的控制就是至少部分地基于是否预定的量来保证通信信道的控制被释放的使用发生在第一个端口和通信信道之间。在一些实施例中，预定的使用量包括传送第一预定量的数据。在一些实施例中，如果小于第二预定量的数据仍然要传送，则禁止释放信道的控制。

6. 发明授权

US5663724A 16B/20B encoder 失效
标题翻译： 16B / 20B编码器
公开(公告)号：US5663724A
公开(公告)日：1997-09-02
申请号：US623400
申请日：1996-03-28
申请人： Judy Lynn Westby
发明人： Judy Lynn Westby
IPC分类号： H03M5/14 , H03M7/00
CPC分类号： H03M5/145
摘要： A 16-bit data block is partitioned into upper 5-bit and 3-bit sub-blocks and lower 5-bit and 3-bit sub-blocks. During a single clock cycle, a first 5B/6B encoder portion encodes the upper 5-bit sub-block to produce an upper 6-bit sub-block, a first 3B/4B encoder portion encodes the upper 3-bit sub-block to produce an upper 4-bit sub-block, a second 5B/6B encoder portion encodes the lower 5-bit sub-block to produce a lower 6-bit sub-block, and a second 3B/4B encoder portion encodes the lower 3-bit sub-block to produce a lower 4-bit sub-block. During the same clock cycle, the running disparities of the upper 6-bit sub-block, the upper 4-bit sub-block and the lower 6-bit sub-block are simultaneously combinationally passed to the first 3B/4B encoder portion, the second 5B/6B encoder portion and the second 3B/4B encoder portion, respectively, to selectively complement the output sub-block to adjust running disparity. During the next clock cycle, the running disparity of the lower 4-bit sub-block is passed to the first 5B/6B encoder for the same purpose.
摘要翻译：一个16位的数据块被划分为高5位和3位子块以及较低的5位和3位子块。在单个时钟周期期间，第一个5B / 6B编码器部分对上部5位子块进行编码以产生一个高6位子块，第一个3B / 4B编码器部分将上部3位子块编码为产生高4位子块，第二5B / 6B编码器部分编码下位5位子块以产生低6位子块，第二3B / 4B编码器部分编码下3位子块，位子块以产生较低的4位子块。在同一时钟周期内，上位6位子块，上位4位子块和下位6位子块的运行差异同时组合传递到第一个3B / 4B编码器部分，第二5B / 6B编码器部分和第二3B / 4B编码器部分，以选择性地补充输出子块以调整运行差异。在下一个时钟周期内，为了相同的目的，低4位子块的运行差异被传递到第一个5B / 6B编码器。

7. 发明授权

US06324669B1 Method and apparatus for using CRC for data integrity in on-chip memory 有权
标题翻译：在片上存储器中使用CRC进行数据完整性的方法和装置
公开(公告)号：US06324669B1
公开(公告)日：2001-11-27
申请号：US09193446
申请日：1998-11-17
申请人： Judy Lynn Westby
发明人： Judy Lynn Westby
IPC分类号： G06F1108
CPC分类号： H04L1/0061 , G06F3/0619 , G06F3/0656 , G06F3/0689 , G06F11/1004 , G06F11/2007 , G06F13/368 , G11B5/012 , H04L1/246 , H04L12/42 , H04L45/02 , H04L45/12 , H04L45/48 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9073
摘要： Cyclic-redundancy-code (“CRC”) information that is received along with a frame from a fiber-channel is stored in an on-chip frame buffer, and later checked to ensure the integrity of the data while in the frame buffer. In various embodiments, data frames, along with their CRC information, are stored into a data-frame buffer, and/or non-data frames along with their CRC information are stored into a receive-non-data-frame buffer. The improved communications channel system includes a channel node having dual ports, each port supporting a fiber-channel arbitrated-loop serial communications channel. The serial communications channels each include CRC on data transmissions on the channel, an on-chip frame memory located on-chip in the channel node that receives a data frame and the frame's associated CRC from the communications channel, and an integrity apparatus that later uses the received associated CRC for data-integrity checking of data in the on-chip frame memory. In addition, a method for using CRC for data integrity in on-chip memory is described.
摘要翻译：与光纤信道的帧一起接收的循环冗余码（“CRC”）信息被存储在片上帧缓冲器中，并且稍后检查以确保在帧缓冲器中数据的完整性。在各种实施例中，数据帧及其CRC信息被存储到数据帧缓冲器中，和/或非数据帧及其CRC信息被存储在接收非数据帧缓冲器中。改进的通信信道系统包括具有双端口的信道节点，每个端口支持光纤信道仲裁环路串行通信信道。串行通信信道各自包括在信道上的数据传输上的CRC，位于信道节点中片上的片上帧存储器，其接收来自通信信道的数据帧和帧的相关联的CRC，以及后来使用的完整性装置所接收的相关CRC用于片内帧存储器中数据的完整性检查。另外，描述了在片上存储器中使用CRC用于数据完整性的方法。

8. 发明授权

US06502189B1 Method and dedicated frame buffer for loop initialization and responses 有权
标题翻译：方法和专用帧缓冲区，用于循环初始化和响应
公开(公告)号：US06502189B1
公开(公告)日：2002-12-31
申请号：US09193387
申请日：1998-11-17
申请人： Judy Lynn Westby
发明人： Judy Lynn Westby
IPC分类号： G06F300
CPC分类号： H04L1/0061 , G06F3/0619 , G06F3/0656 , G06F3/0689 , G06F11/1004 , G06F11/2007 , G06F13/368 , G11B5/012 , H04L1/246 , H04L12/42 , H04L45/02 , H04L45/12 , H04L45/48 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9073
摘要： A fiber-channel loop interface circuit that includes a dedicated transmit-frame buffer for loop initialization and responses (“responses” are non-data frames sent in response to commands or inquiries from other nodes). Having a dedicated transmit-frame buffer allows one port of a dual-port node to be transmitting initialization or response frames while another port is transmitting data frames, response frames, or initialization frames. Either or both ports can also be simultaneously receiving frames. The system includes a channel node having dual ports, each supporting a fiber-channel arbitrated-loop serial communications channel, and dedicated frame buffers within the channel node for loop initialization and responses. In some embodiments, the dedicated frame buffers are configured as on-chip buffers and include: two inbound non-data buffers coupled to the two ports, a data-frame buffer coupled to both ports, and an outbound transmit-frame buffer coupled to at least one of the ports. In addition, a method for loop initialization and responses using the dedicated buffer is described.
摘要翻译：一种光纤通道环路接口电路，其包括用于环路初始化和响应的专用发送帧缓冲器（“响应”是响应于来自其他节点的命令或查询而发送的非数据帧）。具有专用的发送帧缓冲器允许双端口节点的一个端口正在发送初始化或响应帧，而另一个端口正在发送数据帧，响应帧或初始化帧。两个或两个端口也可以同时接收帧。该系统包括具有双端口的信道节点，每个端口支持光纤信道仲裁环路串行通信信道，以及信道节点内的专用帧缓冲器用于环路初始化和响应。在一些实施例中，专用帧缓冲器被配置为片上缓冲器，并且包括：耦合到两个端口的两个入站非数据缓冲器，耦合到两个端口的数据帧缓冲器和耦合到其上的出站发送帧缓冲器至少有一个端口。另外，描述了使用专用缓冲器的循环初始化和响应的方法。

9. 发明授权

US06279057B1 Communications system having dedicated frame buffers located in a channel node connected to two ports of the channel node for receiving frames 有权
标题翻译：通信系统具有位于连接到信道节点的两个端口的信道节点中的专用帧缓冲器，用于接收帧
公开(公告)号：US06279057B1
公开(公告)日：2001-08-21
申请号：US09193681
申请日：1998-11-17
申请人： Judy Lynn Westby
发明人： Judy Lynn Westby
IPC分类号： G06F1314
CPC分类号： H04L1/0061 , G06F3/0619 , G06F3/0656 , G06F3/0689 , G06F11/1004 , G06F11/2007 , G06F13/368 , G11B5/012 , H04L1/246 , H04L12/42 , H04L45/02 , H04L45/12 , H04L45/48 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9073
摘要： Dedicated receive buffers for receiving non-data frames are provided for each port of a two-port node in a fibre-channel arbitrated-loop serial communications channel design. The improved communications channel system and method includes a channel node having dual ports each supporting a communications channel, both ports interfaced from a single interface chip, and a dedicated on-chip frame buffer located on the chip for receiving frames. The dedicated on-chip frame buffer includes two inbound non-data buffers, one coupled to each of two ports, wherein inbound non-data frames from each port are received into the respective inbound non-data buffer. The system further includes an off-chip buffer, wherein received non-data frames are received into one of the non-data-frame buffers and transferred from the non-data-frame buffer to the off-chip buffer. A data-frame buffer is operatively coupled to both ports to receive data frames from the ports, and move the data frames to the off-chip buffer. In addition, a method for receiving frames using the dedicated buffer is described.
摘要翻译：在光纤信道仲裁环路串行通信设计中，为双端口节点的每个端口提供用于接收非数据帧的专用接收缓冲器。改进的通信信道系统和方法包括具有双端口的信道节点，每个端口支持通信信道，从单个接口芯片接口的两个端口以及位于芯片上用于接收帧的专用片上帧缓冲器。专用的片上帧缓冲器包括两个入站非数据缓冲器，一个耦合到两个端口中的每一个，其中来自每个端口的入站非数据帧被接收到相应的入站非数据缓冲器中。该系统还包括片外缓冲器，其中接收到的非数据帧被接收到非数据帧缓冲器之一并从非数据帧缓冲器传送到片外缓冲器。数据帧缓冲器可操作地耦合到两个端口以从端口接收数据帧，并将数据帧移动到片外缓冲器。此外，描述了使用专用缓冲器来接收帧的方法。

10. 发明授权

US5802080A CRC checking using a CRC generator in a multi-port design 失效
标题翻译：在多端口设计中使用CRC发生器进行CRC校验
公开(公告)号：US5802080A
公开(公告)日：1998-09-01
申请号：US623508
申请日：1996-03-28
申请人： Judy Lynn Westby
发明人： Judy Lynn Westby
IPC分类号： G06F11/10 , H03M13/00
CPC分类号： G06F11/10
摘要： A module for connection to a computer network has a plurality of ports for exchanging data with the network. First and second buffers store data received through separate ones of the ports, the first buffer also stores data to be transmitted through all of the ports. An error (CRC) checker is responsive to a CRC code associated with data received by one of the ports to verify the integrity of the associated data. A CRC generator generates a CRC code for data to be transmitted through one of the ports. A gate is connected between the CRC generator and the buffers to transfer to-be-transmitted data stored in the first buffer to the CRC generator and to transfer received data stored in the second buffer to the CRC generator. A comparator is connected to the CRC generator and to the second buffer and is responsive to the CRC code generated by the CRC generator and the CRC code stored in the second buffer to verify the integrity of received data stored in the second buffer.
摘要翻译：用于连接到计算机网络的模块具有用于与网络交换数据的多个端口。第一和第二缓冲器存储通过单独的端口接收的数据，第一缓冲器还存储要通过所有端口传输的数据。错误（CRC）检查器响应于与其中一个端口接收的数据相关联的CRC码，以验证相关数据的完整性。 CRC发生器产生用于通过其中一个端口传输的数据的CRC码。门之间连接在CRC发生器和缓冲器之间，将存储在第一缓冲器中的要发送的数据传送到CRC发生器，并将存储在第二缓冲器中的接收数据传送到CRC发生器。比较器连接到CRC发生器和第二缓冲器，并响应由CRC发生器产生的CRC码和存储在第二缓冲器中的CRC码，以验证存储在第二缓冲器中的接收数据的完整性。

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