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1. 发明授权

US07973556B1 System and method for using reconfiguration ports for power management in integrated circuits 有权
标题翻译：在集成电路中使用重新配置端口进行电源管理的系统和方法
公开(公告)号：US07973556B1
公开(公告)日：2011-07-05
申请号：US12398844
申请日：2009-03-05
申请人： Juan J. Noguera Serra , Tim Tuan
发明人： Juan J. Noguera Serra , Tim Tuan
IPC分类号： H03K19/173
CPC分类号： H03K19/0016 , H03K19/177
摘要： A method of operating an integrated circuit having a circuit block configurable by a configuration memory is disclosed. The method includes determining whether to operate the circuit block in a normal operation mode or a low power mode. The configuration memory is loaded with normal operation mode configuration data for the circuit block if the normal operation mode is determined. If the low power mode is determined, the configuration memory is loaded with low power mode configuration data for the circuit block.
摘要翻译：公开了一种具有由配置存储器配置的电路块的集成电路的操作方法。该方法包括在正常操作模式或低功率模式下确定是否操作电路块。如果确定了正常操作模式，配置存储器将加载电路块的正常操作模式配置数据。如果确定了低功耗模式，配置存储器将加载电路块的低功耗模式配置数据。

2. 发明授权

US08155907B1 Methods of enabling functions of a design to be implemented in an integrated circuit device and a computer program product 有权
标题翻译：使设计功能能够在集成电路装置和计算机程序产品中实现的方法
公开(公告)号：US08155907B1
公开(公告)日：2012-04-10
申请号：US12480488
申请日：2009-06-08
申请人： Austin H. Lesea , Stephen M. Trimberger , Christopher H. Kingsley , Satyaki Das , Tim Tuan
发明人： Austin H. Lesea , Stephen M. Trimberger , Christopher H. Kingsley , Satyaki Das , Tim Tuan
IPC分类号： G06F11/00 , G06F19/00 , G06F17/40
CPC分类号： G06F17/5045 , G06F11/26 , G06F2217/86
摘要： Methods of enabling functions of a design to be implemented in an integrated circuit device are disclosed. An exemplary method comprises applying test data to a plurality of dice having different element types for implementing circuits, wherein the plurality of dice have a common layout of the different element types for implementing the circuits; receiving output data from the plurality of dice in response to applying the test data to the plurality of dice; analyzing the output data from the plurality of dice; transforming by a computer the output data to characterization data comprising timing data associated with the different element types for implementing circuits, wherein the characterization data comprises data associated with regions of the dice, and storing the characterization data. A computer program product for enabling functions of a design to be implemented in an integrated circuit device is also disclosed.
摘要翻译：公开了在集成电路装置中实现设计功能的方法。示例性方法包括将测试数据应用于具有用于实现电路的不同元件类型的多个骰子，其中所述多个骰子具有用于实现电路的不同元件类型的公共布局; 响应于将所述测试数据应用于所述多个骰子，从所述多个骰子接收输出数据; 分析来自多个骰子的输出数据; 通过计算机将输出数据转换成包括与用于实现电路的不同元件类型相关联的定时数据的表征数据，其中表征数据包括与骰子区域相关联的数据，并存储表征数据。还公开了一种用于使得能够在集成电路器件中实现设计功能的计算机程序产品。

3. 发明授权

US08130027B1 Apparatus and method for the detection and compensation of integrated circuit performance variation 有权
标题翻译：用于检测和补偿集成电路性能变化的装置和方法
公开(公告)号：US08130027B1
公开(公告)日：2012-03-06
申请号：US12357703
申请日：2009-01-22
申请人： Tim Tuan
发明人： Tim Tuan
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G11C5/147 , H03K19/17784 , H03K19/17792
摘要： An apparatus and method for the dynamic detection and compensation of performance variations within an integrated circuit (IC) is provided to detect performance variations within the IC at any stage of test or operation. An arbitrary reference signal is utilized in conjunction with an internal oscillation device to establish a speed reference that may be used to characterize the IC. Dynamic detection and compensation may also be configured within a plurality of geographic locations within the IC, so that performance variations may be detected and compensated. Test data that is indicative of the IC's performance may be dynamically generated continuously, or at programmable intervals, so that performance variations caused by virtually any source may be substantially detected and compensated at any point in time of the IC's life cycle.
摘要翻译：提供用于动态检测和补偿集成电路（IC）内的性能变化的装置和方法，用于在任何测试或操作阶段检测IC内的性能变化。与内部振荡装置结合使用任意的参考信号以建立可用于表征IC的速度参考。也可以在IC内的多个地理位置内配置动态检测和补偿，从而可以检测和补偿性能变化。表示IC性能的测试数据可以连续地或以可编程的间隔动态产生，从而可以在IC的生命周期的任何时刻基本上检测和补偿实际上任何源引起的性能变化。

4. 发明授权

US07992020B1 Power management with packaged multi-die integrated circuit 有权
标题翻译：电源管理与封装的多芯片集成电路
公开(公告)号：US07992020B1
公开(公告)日：2011-08-02
申请号：US12043096
申请日：2008-03-05
申请人： Tim Tuan , Kerry M. Pierce , Albert Franceschino
发明人： Tim Tuan , Kerry M. Pierce , Albert Franceschino
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： G06F1/3203 , G06F1/3296 , Y02D10/172
摘要： Power management with a packaged multi-die integrated circuit (IC) is described. A first integrated circuit die is capable of a first operational mode. A second integrated circuit die is coupled to the first integrated circuit die. The first integrated circuit die has a rate of power consumption that is lower than the second integrated circuit die when the first integrated circuit die is in the first operational mode and the second integrated circuit die is in a second operational mode. The first integrated circuit die is configured for power management of the second integrated circuit die for placing the second integrated circuit die in a standby mode from the second operational mode and for returning the second integrated circuit die to the second operational mode from the standby mode.
摘要翻译：描述了使用封装的多芯片集成电路（IC）进行电源管理。第一集成电路管芯能够具有第一操作模式。第二集成电路管芯耦合到第一集成电路管芯。当第一集成电路管芯处于第一操作模式并且第二集成电路管芯处于第二操作模式时，第一集成电路管芯具有低于第二集成电路管芯的功率消耗率。第一集成电路管芯被配置为用于第二集成电路管芯的电源管理，用于将第二集成电路管芯从第二操作模式放置在待机模式中，并且用于将第二集成电路管芯退回到从待机模式的第二操作模式。

5. 发明授权

US07581124B1 Method and mechanism for controlling power consumption of an integrated circuit 有权
标题翻译：控制集成电路功耗的方法和机制
公开(公告)号：US07581124B1
公开(公告)日：2009-08-25
申请号：US11326542
申请日：2006-01-04
申请人： Neil G. Jacobson , Matthew T. Murphy , Tim Tuan , Kameswara K. Rao , Robert O. Conn
发明人： Neil G. Jacobson , Matthew T. Murphy , Tim Tuan , Kameswara K. Rao , Robert O. Conn
IPC分类号： G06F1/22
CPC分类号： G11C5/14 , G11C5/148 , G11C29/021 , G11C29/028 , G11C2029/0401 , H03K19/17784
摘要： A PLD includes a plurality of logic blocks, a test circuit, and a test pin set. The logic blocks are coupled to gating circuits that selectively adjust an operating voltage for the blocks in response to control signals. During operation of the PLD, the control signals are updated in response to externally-generated signals provided to the PLD via the test pin set and routed to the logic blocks using the test circuit.
摘要翻译： PLD包括多个逻辑块，测试电路和测试引脚组。逻辑块耦合到选通电路，门电路响应于控制信号选择性地调整块的工作电压。在PLD的操作期间，响应于通过测试引脚设置到PLD的外部产生的信号来更新控制信号，并使用测试电路将其传送到逻辑块。

6. 发明授权

US07212462B1 Structure and method for suppressing sub-threshold leakage in integrated circuits 有权
标题翻译：用于抑制集成电路中的次阈值泄漏的结构和方法
公开(公告)号：US07212462B1
公开(公告)日：2007-05-01
申请号：US10701835
申请日：2003-11-04
申请人： Tim Tuan
发明人： Tim Tuan
IPC分类号： G11C7/00
CPC分类号： G11C11/413
摘要： Techniques for reducing leakage power in the transistors of integrated circuits are provided. Suppressing sub-threshold leakage techniques can be applied to memory cells that drive the gates of the transistors, memory cells that drive the sources of the transistors, and level shifters that drive the gates of the transistors. In these techniques, an appropriate gate to source voltage (VGS) can be applied to a transistor in its off state. Of importance, this VGS can under-drive the transistor, which significantly reduces the sub-threshold leakage of that transistor. These techniques fail to affect a transistor in its on state, thereby ensuring that high speed performance of the integrated circuit can be maintained.
摘要翻译：提供了降低集成电路晶体管漏电功率的技术。抑制亚阈值泄漏技术可以应用于驱动晶体管的栅极的存储单元，驱动晶体管源极的存储单元以及驱动晶体管栅极的电平移位器。在这些技术中，适当的栅极 - 源极电压（V SUB）可以被施加到处于截止状态的晶体管。重要的是，该晶体管可以驱动晶体管，这显着降低了该晶体管的次阈值泄漏。这些技术不能使晶体管处于导通状态，从而确保集成电路的高速性能得以保持。

7. 发明授权

US06950998B1 Place-and-route with power analysis 有权
标题翻译：功率分析的布局和路线
公开(公告)号：US06950998B1
公开(公告)日：2005-09-27
申请号：US10421251
申请日：2003-04-22
申请人： Tim Tuan
发明人： Tim Tuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077 , G06F2217/78
摘要： Method and apparatus for placing and routing an electronic circuit design. Various embodiments are disclosed for analyzing placed and/or routed designs for power consumption characteristics and timing characteristics. New designs are iteratively generated in order to reduce power consumption and satisfy timing requirements of the design.
摘要翻译：放置和布线电子电路设计的方法和装置。公开了用于分析用于功耗特性和定时特性的放置和/或路由设计的各种实施例。为了降低功耗并满足设计的时序要求，迭代地生成了新的设计。

8. 发明授权

US09355690B1 Time-multiplexed, asynchronous device 有权
标题翻译：时分复用，异步设备
公开(公告)号：US09355690B1
公开(公告)日：2016-05-31
申请号：US13050394
申请日：2011-03-17
申请人： Tim Tuan
发明人： Tim Tuan
IPC分类号： G06F13/00 , G11C7/10 , G06F13/38
CPC分类号： G11C7/1039 , G06F13/385 , G11C7/222 , H03K19/1772 , Y02D10/14 , Y02D10/151
摘要： A method for asynchronous time multiplexing of information with synchronous interfacing includes, responsive to a first edge of a clock signal, asynchronously loading first data, including first multiple sets of data for multiple operations, into a first asynchronous shift register. The first data is asynchronously unloaded from the first asynchronous shift register to a function block for processing to provide second data, including second multiple sets of data as results of the multiple operations. The second data is asynchronously loaded into a second asynchronous shift register. Responsive to a second edge of the clock signal, the second data is asynchronously unloaded from the second asynchronous shift register as the results of the multiple operations. The first edge and the second edge of the clock signal are associated with a same period of the clock signal.
摘要翻译：一种用于具有同步接口的信息的异步时间复用的方法包括响应于时钟信号的第一边缘将包括用于多个操作的第一多组数据的第一数据异步加载到第一异步移位寄存器中。第一数据从第一异步移位寄存器异步卸载到功能块，用于处理以提供第二数据，包括第二多组数据作为多个操作的结果。第二个数据被异步加载到第二个异步移位寄存器中。响应于时钟信号的第二边缘，第二数据作为多次操作的结果从第二异步移位寄存器异步地卸载。时钟信号的第一边沿和第二边沿与时钟信号的相同周期相关联。

9. 发明授权

US08443344B1 Methods for identifying gating opportunities from a high-level language program and generating a hardware definition 有权
标题翻译：从高级语言程序中识别选通机会并生成硬件定义的方法
公开(公告)号：US08443344B1
公开(公告)日：2013-05-14
申请号：US12237486
申请日：2008-09-25
申请人： Prasanna Sundararajan , Tim Tuan
发明人： Prasanna Sundararajan , Tim Tuan
IPC分类号： G06F9/44
CPC分类号： G06F17/5054 , G06F17/5045 , G06F2217/78
摘要： Approaches for generating a hardware definition from a program specified in a high-level language. In one approach, a first set of blocks of instructions in the high-level language program is identified. Each block in the first set is bounded by a respective loop designation in the high-level language. For each block in the first set, an associated respective second set of one or more blocks of the program is identified. Each block in the second set is outside the block in the first set. A hardware definition of the program is generated and stored. For each block in the first set, the hardware definition specifies power-reducing circuitry for one or more blocks in the associated second set. The power-reducing circuitry is controlled based on a status indication from the hardware definition of the block in the first set.
摘要翻译：从高级语言指定的程序生成硬件定义的方法。在一种方法中，识别高级语言程序中的第一组指令块。第一组中的每个块由高级语言中的相应循环指定界定。对于第一组中的每个块，识别该程序的一个或多个块的相关联的相应的第二组。第二组中的每个块都在第一组中的块之外。生成并存储程序的硬件定义。对于第一组中的每个块，硬件定义为相关联的第二组中的一个或多个块指定功率降低电路。基于来自第一组中的块的硬件定义的状态指示来控制功率降低电路。

10. 发明授权

US07498835B1 Implementation of low power standby modes for integrated circuits 有权
标题翻译：实现集成电路的低功耗待机模式
公开(公告)号：US07498835B1
公开(公告)日：2009-03-03
申请号：US11268265
申请日：2005-11-04
申请人： Arifur Rahman , Sean W. Kao , Tim Tuan , Patrick J. Crotty , Jinsong Oliver Huang
发明人： Arifur Rahman , Sean W. Kao , Tim Tuan , Patrick J. Crotty , Jinsong Oliver Huang
IPC分类号： H03K19/173 , G11C5/14
CPC分类号： H03K19/17772 , G06F1/3203 , G06F1/3287 , G11C5/148 , H03K19/0016 , H03K19/17784 , Y02D10/171 , Y02D50/20
摘要： A PLD (200) includes a power management unit (PMU 210) that selectively implements one or more different power-reduction techniques in response to power configuration signals (PC). By manipulating the PC signals, the PMU can independently enable/disable various supply voltage circuits (110, 120, 130) that power CLBs (101), IOBs (102), and configuration memory cells (106), can generate a capture signal that causes data stored in storage elements of the CLBs to be captured in configuration memory cells, and/or can switch power terminals of configuration memory cells between voltage supply circuits. Also, the PMU can sequentially apply and remove power from a number of configurable PLD portions in response to the PC signals, wherein each configurable portion may include any number of the PLD's resources.
摘要翻译： PLD（200）包括功率管理单元（PMU 210），其响应于功率配置信号（PC）选择性地实现一个或多个不同的功率降低技术。通过操纵PC信号，PMU可以独立地启用/禁用为CLB（101），IOB（102）和配置存储器单元（106）供电的各种电源电压电路（110,120,130）可以产生捕获信号，导致存储在CLB的存储元件中的数据被捕获在配置存储单元中，和/或可以在电压供应电路之间切换配置存储单元的电源端子。此外，响应于PC信号，PMU可以顺序地从多个可配置PLD部分中施加和去除电力，其中每个可配置部分可以包括任何数量的PLD资源。

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