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1. 发明申请

US20130256834A1 BACK-SIDE MOM/MIM DEVICES 有权
标题翻译：背面MOM / MIM设备
公开(公告)号：US20130256834A1
公开(公告)日：2013-10-03
申请号：US13430778
申请日：2012-03-27
申请人： Juan Boon TAN , Yeow Kheng Lim , Shao Ning Yuan , Soh Yun Siah , Shunqiang Gong
发明人： Juan Boon TAN , Yeow Kheng Lim , Shao Ning Yuan , Soh Yun Siah , Shunqiang Gong
IPC分类号： H01L29/02 , H01L21/02
CPC分类号： H01L23/5223 , H01L23/481 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： Back-side MOM/MIM structures are integrated on a device with front-side circuitry. Embodiments include forming a substrate having a front side and a back side that is opposite the front side, the substrate including circuitry on the front side of the substrate; and forming a metal-oxide-metal (MOM) capacitor, a metal-insulator-metal (MIM) capacitor, or a combination thereof on the back side of the substrate. Other embodiments include forming a through-silicon via (TSV), in the substrate, connecting the MOM capacitor, the MIM capacitor, or a combination thereof to the circuitry on the front side of the substrate.
摘要翻译：背面MOM / MIM结构集成在具有前端电路的设备上。实施例包括形成具有与前侧相对的前侧和后侧的基板，所述基板在基板的正面上包括电路; 以及在衬底的背面上形成金属 - 氧化物 - 金属（MOM）电容器，金属 - 绝缘体 - 金属（MIM）电容器或其组合。其他实施例包括在衬底中形成穿硅通孔（TSV），将MOM电容器，MIM电容器或其组合连接到衬底前侧上的电路。

2. 发明授权

US08759947B2 Back-side MOM/MIM devices 有权
标题翻译：背面MOM / MIM设备
公开(公告)号：US08759947B2
公开(公告)日：2014-06-24
申请号：US13430778
申请日：2012-03-27
申请人： Juan Boon Tan , Yeow Kheng Lim , Shao Ning Yuan , Soh Yun Siah , Shunqiang Gong
发明人： Juan Boon Tan , Yeow Kheng Lim , Shao Ning Yuan , Soh Yun Siah , Shunqiang Gong
IPC分类号： H01L21/02
CPC分类号： H01L23/5223 , H01L23/481 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： Back-side MOM/MIM structures are integrated on a device with front-side circuitry. Embodiments include forming a substrate having a front side and a back side that is opposite the front side, the substrate including circuitry on the front side of the substrate; and forming a metal-oxide-metal (MOM) capacitor, a metal-insulator-metal (MIM) capacitor, or a combination thereof on the back side of the substrate. Other embodiments include forming a through-silicon via (TSV), in the substrate, connecting the MOM capacitor, the MIM capacitor, or a combination thereof to the circuitry on the front side of the substrate.
摘要翻译：背面MOM / MIM结构集成在具有前端电路的设备上。实施例包括形成具有与前侧相对的前侧和后侧的基板，所述基板在基板的正面上包括电路; 以及在衬底的背面上形成金属 - 氧化物 - 金属（MOM）电容器，金属 - 绝缘体 - 金属（MIM）电容器或其组合。其他实施例包括在衬底中形成穿硅通孔（TSV），将MOM电容器，MIM电容器或其组合连接到衬底前侧上的电路。

3. 发明授权

US08716856B2 Device with integrated power supply 有权
标题翻译：集成电源设备
公开(公告)号：US08716856B2
公开(公告)日：2014-05-06
申请号：US13565748
申请日：2012-08-02
申请人： Juan Boon Tan , Yeow Kheng Lim , Soh Yun Siah , Wei Liu , Shunqiang Gong
发明人： Juan Boon Tan , Yeow Kheng Lim , Soh Yun Siah , Wei Liu , Shunqiang Gong
IPC分类号： H01L23/52
CPC分类号： H01L23/49827 , H01L23/147 , H01L23/481 , H01L23/58 , H01L2224/16225
摘要： Semiconductor devices and methods for forming a semiconductor device are disclosed. The semiconductor device includes a die. The die includes a die substrate having first and second major surfaces. The semiconductor device includes a power module disposed below the second major surface of the die substrate. The power module is electrically coupled to the die through silicon via (TSV) contacts.
摘要翻译：公开了用于形成半导体器件的半导体器件和方法。该半导体器件包括一个管芯。模具包括具有第一和第二主表面的模具基板。半导体器件包括设置在管芯衬底的第二主表面下方的功率模块。电源模块通过硅通孔（TSV）触点电连接到管芯。

4. 发明申请

US20130277810A1 METHOD FOR FORMING HEAT SINK WITH THROUGH SILICON VIAS 审中-公开
标题翻译：通过硅酮形成热沉的方法
公开(公告)号：US20130277810A1
公开(公告)日：2013-10-24
申请号：US13453762
申请日：2012-04-23
申请人： Juan Boon Tan , Yeow Kheng Lim , Shao Ning Yuan , Soh Yun Siah
发明人： Juan Boon Tan , Yeow Kheng Lim , Shao Ning Yuan , Soh Yun Siah
IPC分类号： H01L29/02 , H01L21/768
CPC分类号： H01L23/3677 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices are formed with through silicon vias extending into the semiconductor substrate from a backside surface for improved heat dissipation. Embodiments include forming a cavity in a backside surface of a substrate, the substrate including a gate stack on a frontside surface, and filling the cavity with a thermally conductive material.
摘要翻译：半导体器件通过从后侧表面延伸到半导体衬底中的硅通孔形成，以改善散热。实施例包括在衬底的背面形成空腔，衬底包括在前表面上的栅叠层，并用导热材料填充空腔。

5. 发明授权

US06271133B1 Optimized Co/Ti-salicide scheme for shallow junction deep sub-micron device fabrication 失效
标题翻译：用于浅结深亚微米器件制造的优化Co / Ti-自对准方案
公开(公告)号：US06271133B1
公开(公告)日：2001-08-07
申请号：US09290918
申请日：1999-04-12
申请人： Chong Wee Lim , Eng Hua Lim , Kin Leong Pey , Soh Yun Siah , Chun Hui Low
发明人： Chong Wee Lim , Eng Hua Lim , Kin Leong Pey , Soh Yun Siah , Chun Hui Low
IPC分类号： H01L2144
CPC分类号： H01L29/66507 , H01L21/28518 , H01L29/665 , H01L29/66545 , Y10S438/97
摘要： A new method is established to form different silicide layers over the top of the gate electrode and the surface of the source/drain regions. A thin layer of TiSi2 is formed over the source/drain regions by depositing a layer of titanium and annealing this layer with the silicon substrate. The gate electrode is created as a recessed electrode, in the top recession of the electrode a layer of CoSi2 is formed by depositing a layer of cobalt over the gate electrode. This layer of COSi2 serves as the electrical gate contact point.
摘要翻译：建立了一种新的方法，以在栅电极的顶部和源极/漏极区的表面上形成不同的硅化物层。通过沉积钛层并用硅衬底退火该层，在源极/漏极区域上形成薄的TiSi 2层。栅电极被形成为凹陷电极，在电极的顶部凹陷中，通过在栅电极上沉积钴层形成CoSi 2层。该COSi2层用作电接触点。

6. 发明授权

US06265302B1 Partially recessed shallow trench isolation method for fabricating borderless contacts 有权
标题翻译：用于制造无边界触点的部分凹槽浅沟槽隔离方法
公开(公告)号：US06265302B1
公开(公告)日：2001-07-24
申请号：US09351238
申请日：1999-07-12
申请人： Chong Wee Lim , Eng Hua Lim , Soh Yun Siah , Kong Hean Lee , Chun Hui Low
发明人： Chong Wee Lim , Eng Hua Lim , Soh Yun Siah , Kong Hean Lee , Chun Hui Low
IPC分类号： H01L214763
CPC分类号： H01L21/76897 , H01L21/76232
摘要： An improved and new process for fabricating MOSFET's in shallow trench isolation (STI), with sub-quarter micron ground rules, includes a passivating trench liner of silicon nitride. The silicon nitride passivating liner is utilized in the formation of borderless or “unframed” electrical contacts, without reducing the poly to poly spacing. Borderless contacts are formed, wherein contact openings are etched in an interlevel dielectric (ILD) layer over both an active region (P-N junction) and an inactive trench isolation region. During the contact hole opening, a selective etch process is utilized which etches the ILD layer, while the protecting passivating silicon nitride liner remains intact protecting the P-N junction at the edge of trench region. Subsequent processing of conductive tungsten metal plugs are prevented from shorting by the passivating trench liner. This method of forming borderless contacts with a passivating trench liner in a partially recessed trench isolation scheme improves device reliability since it prevents electrically short circuiting of the P-N junction and lowers the overall diode leakage. In addition, the use of this invention's semi-recessed STI process scheme helps to reduce the aspect ratio of the trench, thereby aiding the filling of the trench. Therefore, with the process described herein, STI oxide seam formation is eliminated.
摘要翻译：具有亚四分之一微米基准规则的在浅沟槽隔离（STI）中制造MOSFET的改进和新工艺包括氮化硅的钝化沟槽衬垫。氮化硅钝化衬垫用于形成无边界或“非成形”电触头，而不会减少聚对多晶间距。形成无边界接触，其中接触开口在有源区（P-N结）和无源沟槽隔离区之上的层间电介质（ILD）层中被蚀刻。在接触孔开口期间，利用蚀刻ILD层的选择性蚀刻工艺，而保护性钝化氮化硅衬垫保持完好，保护沟槽区域边缘处的P-N结。防止导电钨金属插塞的后续处理被钝化沟槽衬垫短路。这种在部分凹槽沟槽隔离方案中与钝化沟槽衬垫形成无边界接触的这种方法提高了器件的可靠性，因为它防止了P-N结的电短路并降低了整体的二极管泄漏。此外，使用本发明的半凹陷STI工艺方案有助于减小沟槽的纵横比，从而有助于填充沟槽。因此，通过本文所述的方法，消除了STI氧化物接缝形成。

7. 发明授权

US08569173B2 Methods of protecting elevated polysilicon structures during etching processes 有权
标题翻译：在蚀刻过程中保护高架多晶硅结构的方法
公开(公告)号：US08569173B2
公开(公告)日：2013-10-29
申请号：US13314270
申请日：2011-12-08
申请人： Liang Li , Huang Liu , Alex See , Soh Yun Siah , Xue Song Rao , Peng Zhou
发明人： Liang Li , Huang Liu , Alex See , Soh Yun Siah , Xue Song Rao , Peng Zhou
IPC分类号： H01L21/302
CPC分类号： H01L27/11534 , H01L21/28273
摘要： Disclosed herein are various methods of protecting elevated polysilicon structures during etching processes. In one example, the method includes forming a layer stack above a semiconducting substrate for a memory device, forming a protective mask layer above the layer stack of the memory device and performing at least one etching process to define a gate electrode for a transistor while the protective mask is in position above the layer stack for the memory device.
摘要翻译：本文公开了在蚀刻工艺期间保护升高的多晶硅结构的各种方法。在一个示例中，该方法包括在用于存储器件的半导体衬底之上形成层堆叠，在存储器件的层堆叠之上形成保护掩模层，并执行至少一个蚀刻工艺以限定晶体管的栅电极，而保护罩位于存储器件的层堆叠之上。

8. 发明授权

US06762085B2 Method of forming a high performance and low cost CMOS device 有权
标题翻译：形成高性能和低成本CMOS器件的方法
公开(公告)号：US06762085B2
公开(公告)日：2004-07-13
申请号：US10262169
申请日：2002-10-01
申请人： Jia Zhen Zheng , Soh Yun Siah , Liang Choo Hsia , Eng Hua Lim , Simon Chooi , Chew Hoe Ang
发明人： Jia Zhen Zheng , Soh Yun Siah , Liang Choo Hsia , Eng Hua Lim , Simon Chooi , Chew Hoe Ang
IPC分类号： H01L218238
CPC分类号： H01L29/66598 , H01L21/823814 , H01L21/823835 , H01L21/823864
摘要： A method of fabricating a CMOS device with reduced processing costs as a result of a reduction in photolithographic masking procedures, has been developed. The method features formation of L shaped silicon oxide spacers on the sides of gate structures, with a vertical spacer component located on the sides of the gate structure, and with horizontal spacer components located on the surface of the semiconductor substrate with a thick horizontal spacer component located adjacent to the gate structures, while a thinner horizontal spacer component is located adjacent to the thicker horizontal spacer component. After formation of a block out shape in a PMOS region of the CMOS device, a high angle implantation procedure is used to form a P type halo region in a top portion of the NMOS region, followed by another implantation procedure performed at lower implant angles, resulting in an N type LDD region in a portion of the NMOS region underlying the thicker horizontal spacer component, and resulting in an N type heavily doped source/drain region in a portion of the NMOS underlying the thinner horizontal spacer component. Another block out shape, and another series of similar implantation procedures is performed to create the halo, LDD and source/drain regions in the PMOS region. After formation of a photoresist block out shape on specific CMOS regions, a composite insulator spacer is formed on the sides of gate structures not covered by the photoresist shape, followed by formation of metal silicide on the gate structures and source/drain regions not covered by the photoresist block out shape.
摘要翻译：已经开发了由于光刻掩模程序的减少而制造具有降低的处理成本的CMOS器件的方法。该方法特征是在栅极结构的侧面上形成L形氧化硅间隔物，其中垂直间隔件部件位于栅极结构的侧面，并且水平间隔件部件位于半导体衬底的表面上，具有厚的水平间隔件位于邻近门结构的位置，而较薄的水平间隔件组件位于较厚的水平间隔件部件附近。在CMOS器件的PMOS区域中形成块状形状之后，使用高角度注入工艺在NMOS区域的顶部形成P型卤素区域，随后以较低的注入角度进行另一种注入工艺，导致在较厚的水平间隔器部件下面的NMOS区域的一部分中的N型LDD区域，并且导致在较薄的水平间隔器部件下面的NMOS的一部分中的N型重掺杂的源极/漏极区域。执行另一个块状形状，并且进行另一系列相似的注入工艺以在PMOS区域中产生卤素，LDD和源极/漏极区域。在特定CMOS区域上形成光致抗蚀剂阻挡形状之后，在未被光致抗蚀剂形状覆盖的栅极结构的侧面上形成复合绝缘体间隔物，然后在栅极结构和未被覆盖的源极/漏极区域上形成金属硅化物光致抗蚀剂阻挡形状。

9. 发明授权

US6093628A Ultra-low sheet resistance metal/poly-si gate for deep sub-micron CMOS application 有权
标题翻译：用于深亚微米CMOS应用的超低电阻金属/多晶硅栅极
公开(公告)号：US6093628A
公开(公告)日：2000-07-25
申请号：US165003
申请日：1998-10-01
申请人： Chong Wee Lim , Kin Leong Pey , Soh Yun Siah , Eng Hwa Lim , Lap Chan
发明人： Chong Wee Lim , Kin Leong Pey , Soh Yun Siah , Eng Hwa Lim , Lap Chan
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/49 , H01L21/4763 , H01L21/3205 , H01L21/44
CPC分类号： H01L29/6659 , H01L21/28061 , H01L21/823842 , H01L29/4941 , H01L29/66545
摘要： A method for fabricating a deep sub-micron gate electrode, comprising polysilicon and metal, having ultra-low sheet resistance. The process begins by forming shallow trench isolation regions 14 in a silicon substrate 10. A gate oxide layer is formed on device areas. A doped blanket polysilicon layer 16 is formed on the gate oxide layer. A cap layer 20 composed of silicon nitride is formed on the polysilicon layer 16. The cap layer 20 and the polysilicon layer 16 are patterned by photoresist masking and anisotropic etching to form a bottom gate electrode 16A and a gate cap 20A. Lightly doped source/drain areas 22 are formed adjacent to the gate bottom electrodes 16A by ion implantation. Sidewall spacers 21 are formed on the gate electrode 16A and gate cap 20A. Source/drain regions 24 are formed by ion implantation adjacent to said sidewall spacers 21. A metal silicide 23 is formed on the source/drain regions 24. An interlevel dielectric layer (ILD) 28 is deposited and planarized by CMP using the gate cap 20A as a CMP stop. The gate cap 20 is selectively removed. A barrier layer 32 composed of a TaN, CoWP, TiN or W.sub.x N.sub.y is formed over the planarized IDL 28A. A top gate layer 36 composed of copper or tungsten is formed on the barrier layer 32. The top gate layer 36 and the barrier layer 32 are removed down to the level of the top of the ILD 28 using CMP; thereby forming a top gate electrode. A passivation layer 40, composed of Pd or NiP is selectively deposited over the gate top electrode 36A.
摘要翻译：一种制造具有超薄薄层电阻的深亚微米栅电极的方法，包括多晶硅和金属。该过程通过在硅衬底10中形成浅沟槽隔离区14开始。栅极氧化物层形成在器件区域上。掺杂的覆盖多晶硅层16形成在栅极氧化物层上。在多晶硅层16上形成由氮化硅构成的覆盖层20.通过光致抗蚀剂掩模和各向异性蚀刻对覆盖层20和多晶硅层16进行构图以形成底栅电极16A和栅极帽20A。通过离子注入，与栅极底部电极16A相邻地形成轻掺杂源极/漏极区域22。侧壁间隔件21形成在栅极16A和栅极盖20A上。源极/漏极区24通过与所述侧壁间隔物21相邻的离子注入而形成。金属硅化物23形成在源/漏区24上。层间绝缘层（ILD）28通过CMP使用栅极帽20A沉积并平坦化作为CMP停止。选择性地去除栅极盖20。在平坦化的IDL28A上形成由TaN，CoWP，TiN或WxNy构成的阻挡层32。在势垒层32上形成由铜或钨构成的顶栅层36.顶栅层36和势垒层32使用CMP向下移至ILD28顶部的电平; 从而形成顶栅电极。由栅极顶电极36A选择性地沉积由Pd或NiP组成的钝化层40。

10. 发明授权

US06734082B2 Method of forming a shallow trench isolation structure featuring a group of insulator liner layers located on the surfaces of a shallow trench shape 有权
标题翻译：形成浅沟槽隔离结构的方法，其特征在于位于浅沟槽形状的表面上的一组绝缘体衬垫层
公开(公告)号：US06734082B2
公开(公告)日：2004-05-11
申请号：US10213173
申请日：2002-08-06
申请人： Jia Zhen Zheng , Soh Yun Siah , Chew Hoe Ang
发明人： Jia Zhen Zheng , Soh Yun Siah , Chew Hoe Ang
IPC分类号： H01L2146
CPC分类号： H01L21/76232
摘要： A process for forming a shallow trench isolation (STI), structure in a semiconductor substrate, featuring a group of insulator liner layers located on the surfaces of the shallow trench shape used to accommodate the STI structure, has been developed. After defining a shallow trench shape featuring rounded corners, a group of thin insulator liner layers, each comprised of either silicon oxide or silicon nitride, is deposited on the exposed surfaces of the shallow trench shape via atomic layer depositing (ALD), procedures. A high density plasma procedure is used for deposition of silicon oxide, filling the shallow trench shape which is lined with the group of thin insulator liner layers. The silicon nitride component of the insulator liner layers, prevents diffusion or segregation of P type dopants from an adjacent P well region to the silicon oxide of the STI structure.
摘要翻译：已经开发了用于形成半导体衬底中的浅沟槽隔离（STI）结构的方法，其特征在于位于用于容纳STI结构的浅沟槽形状的表面上的一组绝缘体衬垫层。在定义了具有圆角的浅沟槽形状之后，通过原子层沉积（ALD）方法将沉积在浅沟槽形状的暴露表面上的一组薄的绝缘体衬垫层（每个都由氧化硅或氮化硅组成）沉积在一起。使用高密度等离子体方法沉积氧化硅，填充衬有薄绝缘体衬层层的浅沟槽形状。绝缘体衬垫层的氮化硅组分防止P型掺杂剂从相邻P阱区扩散或分离到STI结构的氧化硅上。

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