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1. 发明授权

US08522115B2 Flash memory device and memory system comprising same 有权
标题翻译：闪存器件和包括其的存储器系统
公开(公告)号：US08522115B2
公开(公告)日：2013-08-27
申请号：US12898843
申请日：2010-10-06
申请人： Ju hyung Kim , Chang Seok Kang , Young Woo Park , Jung Dal Choi , Jong-Yeon Kim
发明人： Ju hyung Kim , Chang Seok Kang , Young Woo Park , Jung Dal Choi , Jong-Yeon Kim
IPC分类号： G11C29/00
CPC分类号： G06F11/1068 , G11C2029/0411
摘要： A flash memory device provided here comprises a user data area storing user data; and a security data area storing security data. The security data area stores a security data pattern in which first groups of memory cells storing security data are arranged respectively between second groups of memory cells storing dummy data.
摘要翻译：这里提供的闪存装置包括存储用户数据的用户数据区域; 以及存储安全数据的安全数据区。安全数据区域存储其中存储有安全数据的第一组存储单元分别布置在存储虚拟数据的第二组存储单元之间的安全数据模式。

2. 发明申请

US20070195597A1 Non-Volatile Memory Devices that Utilize Mirror-Image Programming Techniques to Inhibit Program Coupling Noise and Methods of Programming Same 有权
标题翻译：利用镜像编程技术抑制程序耦合噪声和编程方法的非易失性存储器件相同
公开(公告)号：US20070195597A1
公开(公告)日：2007-08-23
申请号：US11567865
申请日：2006-12-07
申请人： Ki Tae Park , Jung Dal Choi
发明人： Ki Tae Park , Jung Dal Choi
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C2216/14
摘要： Non-volatile memory devices have improved data storage reliability resulting from mirror-image programming techniques that operate to reduce coupling noise between adjacent memory cells within a memory array. The adjacent memory cells include a first pair of memory cells and a second pair of memory cells. A program control circuit is provided to support mirror-image programming of the first and second pairs of memory cells when the two pairs of memory cells are storing the same 3-bit data.
摘要翻译：非易失性存储器件具有改善的数据存储可靠性，这是由于操作以减少存储器阵列内的相邻存储器单元之间的耦合噪声的镜像编程技术而产生的。相邻的存储单元包括第一对存储单元和第二对存储单元。当两对存储器单元存储相同的3位数据时，提供程序控制电路以支持第一和第二对存储单元的镜像编程。

3. 发明授权

US08248853B2 Methods of programming non-volatile flash memory devices by applying a higher voltage level to a selected word line than to a word line neighboring the selected word line 有权
标题翻译：通过对所选择的字线施加比毗邻所选字线的字线更高的电压电平来对非易失性闪存器件进行编程的方法
公开(公告)号：US08248853B2
公开(公告)日：2012-08-21
申请号：US12590701
申请日：2009-11-12
申请人： Jae Duk Lee , Soon Moon Jung , Jung Dal Choi
发明人： Jae Duk Lee , Soon Moon Jung , Jung Dal Choi
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： In a method of programming a non-volatile memory device, a first voltage is applied to a selected word line corresponding to a selected memory cell transistor of a selected transistor string to be programmed; a second voltage is applied to a neighboring word line neighboring the selected word line and corresponding to a neighboring transistor of the selected transistor string, wherein the first voltage is greater than the second voltage, the application of the first and second voltages to the selected and neighboring word lines respectively causing electrons to be generated by an electric field formed between the neighboring transistor and the selected memory cell transistor, the electrons accelerating toward the selected memory cell transistor and injecting into a charge storage layer of the selected memory cell transistor; wherein the neighboring transistor is positioned between the selected memory cell transistor and one of a ground select transistor and a string select transistor, and the first voltage is applied to unselected word lines corresponding to unselected memory cell transistors of the selected transistor string positioned between the selected memory cell transistor and the other of the ground select transistor and the string select transistor.
摘要翻译：在编程非易失性存储器件的方法中，将第一电压施加到对应于要编程的所选择的晶体管串的选定存储单元晶体管的选定字线; 第二电压被施加到与所选择的字线相邻并且对应于所选择的晶体管串的相邻晶体管的相邻字线，其中第一电压大于第二电压，将第一和第二电压施加到所选择的和分别使相邻的晶体管与所选择的存储单元晶体管之间形成的电场产生电子的相邻字线，电子向所选择的存储单元晶体管加速并注入到所选存储单元晶体管的电荷存储层中; 其中所述相邻晶体管位于所选择的存储单元晶体管和接地选择晶体管和串选择晶体管中的一个之间，并且所述第一电压被施加到对应于所选择的晶体管串的未选择存储单元晶体管的未选择字线，存储单元晶体管和另一个接地选择晶体管和串选择晶体管。

4. 发明申请

US20070139077A1 Level shifter with reduced leakage current and block driver for nonvolatile semiconductor memory device 失效
标题翻译：具有减少泄漏电流的电平移位器和用于非易失性半导体存储器件的块驱动器
公开(公告)号：US20070139077A1
公开(公告)日：2007-06-21
申请号：US11604701
申请日：2006-11-28
申请人： Ki Tae Park , Jung Dal Choi
发明人： Ki Tae Park , Jung Dal Choi
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521 , G11C16/08
摘要： A level shifter is disclosed and generates an output signal having a swing voltage shifted by a positive boost voltage with respect to an input signal. The level shifter comprises; an enable unit adapted to enable the output signal in response to the input signal, and a disable unit adapted to disable the output signal in response to the input signal. The enable unit comprises; a shifting voltage terminal adapted to receive the boost voltage, a control node, a shifting unit disposed between the shifting voltage terminal and the control node and responsive to the output signal, such that a voltage having a difference with the boost voltage lower than a voltage of the output signal is provided to the control node, whereby the output signal is boosted by the positive boost voltage, a control PMOS transistor disposed between the control node and the output signal and gated by the input signal, and bulk voltage generation unit adapted to generate a predetermined bulk voltage having a voltage difference with the boost voltage lower than that of the control node to a bulk of the control PMOS transistor.
摘要翻译：公开了一种电平转换器，并且产生具有相对于输入信号偏移正升压电压的摆幅电压的输出信号。电平移位器包括：响应于所述输入信号使能所述输出信号的使能单元，以及适于响应于所述输入信号禁用所述输出信号的禁用单元。使能单元包括：适于接收升压电压的换档电压端子，控制节点，设置在变换电压端子和控制节点之间并响应于输出信号的移位单元，使得与升压电压的差值低于电压输出信号被提供给控制节点，由此输出信号由正升压电压升压，控制PMOS晶体管设置在控制节点和输出信号之间并由输入信号选通，体电压产生单元适于产生具有与控制节点的升压电压相比低于控制PMOS晶体管的体积的电压差的预定体积电压。

5. 发明授权

US08427881B2 Semiconductor memory device and programming method thereof 有权
标题翻译：半导体存储器件及其编程方法
公开(公告)号：US08427881B2
公开(公告)日：2013-04-23
申请号：US12748613
申请日：2010-03-29
申请人： Jae Hoon Jang , Jung Dal Choi
发明人： Jae Hoon Jang , Jung Dal Choi
IPC分类号： G11C11/4094
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/24
摘要： A programming method of a semiconductor memory device includes charging a channel of an inhibit string to a precharge voltage provided to the common source line and boosting the charged channel by providing a wordline voltage to the cell strings. The inhibit string is connected to a program bitline among the bitlines.
摘要翻译：半导体存储器件的编程方法包括：将禁止串的通道充电到提供给公共源极线的预充电电压，并通过向单元串提供字线电压来升压充电通道。禁止字符串连接到位线之间的程序位线。

6. 发明申请

US20100118606A1 Methods of programming non-volatile memory devices and memory devices programmed thereby 有权
标题翻译：对由此编程的非易失性存储器件和存储器件进行编程的方法
公开(公告)号：US20100118606A1
公开(公告)日：2010-05-13
申请号：US12590701
申请日：2009-11-12
申请人： Jae Duk Lee , Soon Moon Jung , Jung Dal Choi
发明人： Jae Duk Lee , Soon Moon Jung , Jung Dal Choi
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： In a method of programming a non-volatile memory device, and in a device incorporating the same, the memory device includes: a plurality of memory cell transistors arranged in a plurality of transistor strings, wherein a transistor string includes a plurality of memory cell transistors arranged in series; a plurality of word lines, each word line connected to a corresponding memory cell transistor of each of the different transistor strings; and a plurality of bit lines, each bit line connected to one of the transistor strings. The method comprises: applying a first voltage to a selected word line corresponding to a selected memory cell transistor of a selected transistor string to be programmed; and applying a second voltage to a neighboring word line neighboring the selected word line and corresponding to a neighboring transistor of the selected transistor string, wherein the first voltage is greater than the second voltage, the application of the first and second voltages to the selected and neighboring word lines respectively causing electrons to be generated by an electric field formed between the neighboring transistor and the selected memory cell transistor, the electrons accelerating toward the selected memory cell transistor and injecting into a charge storage layer of the selected memory cell transistor.
摘要翻译：在一种编程非易失性存储器件的方法中，以及在其中包含该非易失性存储器件的器件中，存储器件包括：多个存储单元晶体管，被布置在多个晶体管串中，其中晶体管串包括多个存储单元晶体管串联排列多个字线，每个字线连接到每个不同晶体管串的对应存储单元晶体管; 和多个位线，每个位线连接到一个晶体管串。该方法包括：将第一电压施加到与要编程的所选晶体管串的选定存储单元晶体管相对应的选定字线; 以及将第二电压施加到与所选择的字线相邻并且对应于所选择的晶体管串的相邻晶体管的相邻字线，其中所述第一电压大于所述第二电压，将所述第一和第二电压施加到所选择的和分别使相邻的晶体管和选择的存储单元晶体管之间形成的电场产生电子的相邻字线，电子向所选择的存储单元晶体管加速并注入到所选择的存储单元晶体管的电荷存储层中。

7. 发明申请

US20090321811A1 MEMORY CELL TRANSISTORS HAVING BANDGAP-ENGINEERED TUNNELING INSULATOR LAYERS, NON-VOLATILE MEMORY DEVICES INCLUDING SUCH TRANSISTORS, AND METHODS OF FORMATION THEREOF 审中-公开
标题翻译：具有带状工程隧道绝缘层的存储单元晶体管，包括这种晶体管的非易失性存储器件及其形成方法
公开(公告)号：US20090321811A1
公开(公告)日：2009-12-31
申请号：US12492237
申请日：2009-06-26
申请人： Chang Hyun Lee , Jung Dal Choi
发明人： Chang Hyun Lee , Jung Dal Choi
IPC分类号： H01L29/788 , H01L27/06
CPC分类号： H01L27/11565 , H01L29/40114 , H01L29/40117 , H01L29/42332 , H01L29/513 , H01L29/7883 , H01L29/792
摘要： A memory cell transistor comprises: an active region, the active region being elongated in a first direction of extension; a tunnel layer on the active region, the tunnel layer comprising a first tunnel insulating layer, a second tunnel insulating layer on the first tunnel insulating layer and a third tunnel insulating layer on the second tunnel insulating layer; a charge storage layer on the tunnel layer; a blocking insulating layer on the charge storage layer; and a control gate electrode on the blocking insulating layer, the control gate electrode being elongated in a second direction of extension that is transverse the first direction of extension, the active region having a first width in the second direction of extension, the second tunnel insulating layer having a second width in the second direction of extension, the second width being different than the first width.
摘要翻译：存储单元晶体管包括：有源区，有源区在第一扩展方向上是细长的; 所述隧道层包括第一隧道绝缘层，所述第一隧道绝缘层上的第二隧道绝缘层和所述第二隧道绝缘层上的第三隧道绝缘层; 隧道层上的电荷存储层; 电荷存储层上的阻挡绝缘层; 以及在所述阻挡绝缘层上的控制栅极电极，所述控制栅极电极在与所述第一延伸方向横向的第二延伸方向上延伸，所述有源区域在所述第二延伸方向上具有第一宽度，所述第二隧道绝缘层在第二延伸方向上具有第二宽度，第二宽度不同于第一宽度。

8. 发明授权

US07639529B2 Non-volatile memory devices that utilize mirror-image programming techniques to inhibit program coupling noise and methods of programming same 有权
标题翻译：利用镜像编程技术抑制程序耦合噪声的非易失性存储器件和编程方法相同
公开(公告)号：US07639529B2
公开(公告)日：2009-12-29
申请号：US11567865
申请日：2006-12-07
申请人： Ki Tae Park , Jung Dal Choi
发明人： Ki Tae Park , Jung Dal Choi
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C2216/14
摘要： Non-volatile memory devices have improved data storage reliability resulting from mirror-image programming techniques that operate to reduce coupling noise between adjacent memory cells within a memory array. The adjacent memory cells include a first pair of memory cells and a second pair of memory cells. A program control circuit is provided to support mirror-image programming of the first and second pairs of memory cells when the two pairs of memory cells are storing the same 3-bit data.
摘要翻译：非易失性存储器件具有改善的数据存储可靠性，这是由于操作以减少存储器阵列内的相邻存储器单元之间的耦合噪声的镜像编程技术而产生的。相邻的存储单元包括第一对存储单元和第二对存储单元。当两对存储器单元存储相同的3位数据时，提供程序控制电路以支持第一和第二对存储单元的镜像编程。

9. 发明申请

US20110019486A1 SEMICONDUCTOR MEMORY DEVICE AND PROGRAMMING METHOD THEREOF 有权
标题翻译：半导体存储器件及其编程方法
公开(公告)号：US20110019486A1
公开(公告)日：2011-01-27
申请号：US12748613
申请日：2010-03-29
申请人： Jae Hoon Jang , Jung Dal Choi
发明人： Jae Hoon Jang , Jung Dal Choi
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/24
摘要： A programming method of a semiconductor memory device includes charging a channel of an inhibit string to a precharge voltage provided to the common source line and boosting the charged channel by providing a wordline voltage to the cell strings. The inhibit string is connected to a program bitline among the bitlines.
摘要翻译：半导体存储器件的编程方法包括：将禁止串的通道充电到提供给公共源极线的预充电电压，并通过向单元串提供字线电压来升压充电通道。禁止字符串连接到位线之间的程序位线。

10. 发明授权

US07492206B2 Level shifter with reduced leakage current and block driver for nonvolatile semiconductor memory device 失效
标题翻译：具有减少泄漏电流的电平移位器和用于非易失性半导体存储器件的块驱动器
公开(公告)号：US07492206B2
公开(公告)日：2009-02-17
申请号：US11604701
申请日：2006-11-28
申请人： Ki Tae Park , Jung Dal Choi
发明人： Ki Tae Park , Jung Dal Choi
IPC分类号： H03L5/00
CPC分类号： H03K19/018521 , G11C16/08
摘要： A level shifter is disclosed and generates an output signal having a swing voltage shifted by a positive boost voltage with respect to an input signal. The level shifter comprises; an enable unit adapted to enable the output signal in response to the input signal, and a disable unit adapted to disable the output signal in response to the input signal. The enable unit comprises; a shifting voltage terminal adapted to receive the boost voltage, a control node, a shifting unit disposed between the shifting voltage terminal and the control node and responsive to the output signal, such that a voltage having a difference with the boost voltage lower than a voltage of the output signal is provided to the control node, whereby the output signal is boosted by the positive boost voltage, a control PMOS transistor disposed between the control node and the output signal and gated by the input signal, and bulk voltage generation unit adapted to generate a predetermined bulk voltage having a voltage difference with the boost voltage lower than that of the control node to a bulk of the control PMOS transistor.
摘要翻译：公开了一种电平转换器，并且产生具有相对于输入信号偏移正升压电压的摆幅电压的输出信号。电平移位器包括：响应于所述输入信号使能所述输出信号的使能单元，以及适于响应于所述输入信号禁用所述输出信号的禁用单元。使能单元包括：适于接收升压电压的换档电压端子，控制节点，设置在变换电压端子和控制节点之间并响应于输出信号的移位单元，使得与升压电压的差值低于电压输出信号被提供给控制节点，由此输出信号由正升压电压升压，控制PMOS晶体管设置在控制节点和输出信号之间并由输入信号选通，体电压产生单元适于产生具有与控制节点的升压电压相比低于控制PMOS晶体管体积的电压差的预定体积电压。

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