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1. 发明授权

US5369049A DRAM cell having raised source, drain and isolation 失效
标题翻译： DRAM电池具有升高的源极，漏极和隔离
公开(公告)号：US5369049A
公开(公告)日：1994-11-29
申请号：US169873
申请日：1993-12-17
申请人： Joyce E. Acocella , Louis L. Hsu , Seiki Ogura , Nivo Rovedo , Joseph F. Shepard
发明人： Joyce E. Acocella , Louis L. Hsu , Seiki Ogura , Nivo Rovedo , Joseph F. Shepard
IPC分类号： H01L27/108 , H01L27/00 , H01L21/70
CPC分类号： H01L27/10829
摘要： A method of forming a MOS DRAM cell having a trench capacitor in which the strap connection to the trench capacitor, the source, drain, and isolation are all raised above the surface of the single crystal silicon includes the steps of forming the trench capacitors, depositing a blanket gate stack including the gate oxide and a set of gate layers, and then depositing isolation members in apertures etched in the gate stack using the gate oxide as an etch stop. The same sidewalls that are used to form an LDD source and drain form a self-aligned aperture for a surface strap that insulates the strap from misaligned portions of the gate stack.
摘要翻译：一种形成具有沟槽电容器的MOS DRAM单元的方法，其中与沟槽电容器的带连接，源极，漏极和隔离都在单晶硅的表面上方升高，包括以下步骤：形成沟槽电容器，包括栅极氧化物和一组栅极层的覆盖栅极堆叠，然后使用栅极氧化物作为蚀刻停止层，在隔离栅堆叠中蚀刻的孔中沉积隔离元件。用于形成LDD源和漏极的相同侧壁形成用于将带与栅堆叠的未对准部分绝缘的表面带的自对准孔。

2. 发明授权

US5622881A Packing density for flash memories 失效
标题翻译：闪存的包装密度
公开(公告)号：US5622881A
公开(公告)日：1997-04-22
申请号：US319393
申请日：1994-10-06
申请人： Joyce E. Acocella , Carol Galli , Louis Lu-Chen Hsu , Seiki Ogura , Nivo Rovedo , Joseph F. Shepard
发明人： Joyce E. Acocella , Carol Galli , Louis Lu-Chen Hsu , Seiki Ogura , Nivo Rovedo , Joseph F. Shepard
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C13/00
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11546 , Y10S148/117 , Y10S438/981
摘要： Improved packing density as well as improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation structures covered with a thin nitride layer. The confinement of the floating gate is achieved by planarization, preferably with a self-limiting chemical/mechanical polishing process, to the surface of the nitride layer covering the isolation structures. Gate oxide and control electrode connections can then be formed on a substantially planar surface without compromising the quality of the gate oxide or breakdown voltage the device must withstand for programming. Since severe topology is avoided over which these connections are formed, improved formation of low resistance connections, possibly including metal connections, are possible and allow scaling of transistors of the memory cells to be scaled to sizes not previously possible.
摘要翻译：通过将浮置栅极结构限制在被薄氮化物层覆盖的隔离结构之间，可在电可编程存储器中实现提高的封装密度以及改进的性能和制造产量。浮栅的限制是通过平面化，优选采用自限制化学/机械抛光工艺，覆盖覆盖隔离结构的氮化物层的表面来实现的。然后可以在基本平坦的表面上形成栅极氧化物和控制电极连接，而不会损害器件必须承受编程的栅极氧化物的质量或击穿电压。由于避免了形成这些连接的严格的拓扑结构，所以可能包括可能包括金属连接的低电阻连接的形成得到改进，并且允许将存储器单元的晶体管缩放到先前不可能的尺寸。

3. 发明授权

US4551906A Method for making self-aligned lateral bipolar transistors 失效
标题翻译：制造自对准侧向双极晶体管的方法
公开(公告)号：US4551906A
公开(公告)日：1985-11-12
申请号：US560629
申请日：1983-12-12
申请人： Seiki Ogura , Jacob Riseman , Nivo Rovedo , Joseph F. Shepard
发明人： Seiki Ogura , Jacob Riseman , Nivo Rovedo , Joseph F. Shepard
IPC分类号： H01L21/8222 , H01L21/28 , H01L21/331 , H01L21/336 , H01L27/06 , H01L27/082 , H01L29/73 , H01L21/265 , H01L21/225
CPC分类号： H01L29/6625 , H01L29/66272 , H01L29/66606
摘要： A semiconductor body having surface regions thereof isolated from other such regions by a pattern of dielectric isolation is provided. At least two narrow widths PN junction regions are located within at least one of the surface regions. Each PN junction has a width dimension substantially that of its electrical contact. Substantially vertical conformal conductive layers electrically ohmic contact each of the PN junction regions. The PN junction regions are the emitter and collector regions for a lateral bipolar transistor. A base PN junction region of an opposite conductivity is located between and contiguous to the emitter and the collector junctions. Substantially horizontal conductive layers are in electrical contact with an edge of each of the vertical conductive layers and separated from the surface regions by a first electrical insulating layer. A second insulating layer covers the conformal conductive layers. The horizontal conductive layer is patterned so as to have electrically separated conductive lines from one another. A third electrical insulating layer is located over the patterned horizontal conductive layers. An electrical contact is made to each of the horizontal conductive layers through an opening in the third electrical insulating layer which effectively makes contacts to the emitter and collector regions through the patterned horizontal conductive layers and the vertical conductive layers. An ohmic contact is made to the base region which is separated from the vertical conductive layers by the second insulating layer.
摘要翻译：提供了具有通过介电隔离图案与其它这样的区域隔离的表面区域的半导体本体。至少两个窄宽度PN结区域位于至少一个表面区域内。每个PN结的宽度尺寸基本上是其电接触点。基本上垂直的保形导电层电阻接触每个PN结区域。 PN结区域是用于横向双极晶体管的发射极和集电极区域。具有相反电导率的基极PN结区域位于发射极和集电极结之间并且邻近发射极和集电极结。基本上水平的导电层与每个垂直导电层的边缘电接触并且通过第一电绝缘层与表面区域分离。第二绝缘层覆盖保形导电层。将水平导电层图案化成具有彼此分离的导电线。第三电绝缘层位于图案化的水平导电层上。通过第三电绝缘层中的开口对每个水平导电层进行电接触，其有效地通过图案化的水平导电层和垂直导电层与发射极和集电极区域接触。与通过第二绝缘层与垂直导电层分离的基极区域进行欧姆接触。

4. 发明授权

US4641170A Self-aligned lateral bipolar transistors 失效
标题翻译：自对准侧向双极晶体管
公开(公告)号：US4641170A
公开(公告)日：1987-02-03
申请号：US762669
申请日：1985-08-05
申请人： Seiki Ogura , Jacob Riseman , Nivo Rovedo , Joseph F. Shepard
发明人： Seiki Ogura , Jacob Riseman , Nivo Rovedo , Joseph F. Shepard
IPC分类号： H01L21/331 , H01L21/336 , H01L29/72
CPC分类号： H01L29/6625 , H01L29/66272 , H01L29/66606
摘要： An integrated circuit structure which includes small area lateral bipolar and method for making the same is described. A semiconductor body, such as a monocrystalline silicon wafer, having surface regions thereof isolated from other such regions by a pattern of dielectric isolation is provided. At least two narrow widths PN junction regions are located within at least one of the surface regions. Each PN junction has a width dimension substantially that of its electrical contact. Substantially vertical conformal conductive layers electrically ohmic contact each of the PN junction regions. The PN junction regions are the emitter and collector regions for a lateral bipolar transistor. A base PN junction base region of an opposite conductivity is located between and contiguous to the emitter and the collector junctions. Substantially horizontal conductive layers are in electrical contact with an edge of each of the vertical conductive layers and separated from the surface regions by a first electrical insulating layer. A second insulating layer covers the conformal conductive layers. The horizontal conductive layer is patterned so as to have electrically separated conductive lines from one another. A third electrical insulating layer is located over the patterned horizontal conductive layers. An electrical ohmic contact is made to each of the horizontal conductive layers through an opening in the third electrical insulating layer which effectively makes electrical contacts to the emitter and collector regions through the patterned horizontal conductive layers and the vertical conductive layers. An electrical ohmic contact is made to the centrally located base region which contact is separated from the vertical conductive layers by the second insulating layer.
摘要翻译：描述了包括小面积横向双极的集成电路结构及其制造方法。提供了半导体本体，例如单晶硅晶片，其表面区域通过介电隔离图案与其它这样的区域隔离。至少两个窄宽度PN结区域位于至少一个表面区域内。每个PN结的宽度尺寸基本上是其电接触点。基本上垂直的保形导电层电阻接触每个PN结区域。 PN结区域是用于横向双极晶体管的发射极和集电极区域。具有相反电导率的基极PN结基区位于发射极和集电极结之间并且与发射极和集电极结邻接。基本上水平的导电层与每个垂直导电层的边缘电接触，并通过第一电绝缘层与表面区域分离。第二绝缘层覆盖保形导电层。将水平导电层图案化成具有彼此分离的导电线。第三电绝缘层位于图案化的水平导电层上。通过第三电绝缘层中的开口对每个水平导电层进行电欧姆接触，其有效地通过图案化的水平导电层和垂直导电层与发射极和集电极区域电接触。对中心位置的基极区域进行电欧姆接触，该接触部分通过第二绝缘层与垂直导电层分离。

5. 发明授权

US5389559A Method of forming integrated interconnect for very high density DRAMs 失效
标题翻译：形成非常高密度DRAM的集成互连的方法
公开(公告)号：US5389559A
公开(公告)日：1995-02-14
申请号：US161763
申请日：1993-12-02
申请人： Chang-Ming Hsieh , Louis L. Hsu , Toshio Mii , Seiki Ogura , Joseph F. Shepard
发明人： Chang-Ming Hsieh , Louis L. Hsu , Toshio Mii , Seiki Ogura , Joseph F. Shepard
IPC分类号： H01L21/8242 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10861 , H01L27/10829
摘要： A trench capacitor DRAM cell with Shallow Trench Isolation (STI), a self-aligned buried strap and the method of making the cell. A trench capacitor is defined in a substrate. The trench capacitor's polysilicon (poly) plate is recessed below the surface of the substrate and the trench sidewalls are exposed above the poly. A doped poly layer is deposited over the surface contacting both the sidewall and the trench capacitor's poly plate. Horizontal portions of the poly layer are removed either through chemmech polishing or Reactive Ion Etching (RIE). A shallow trench is formed, removing one formerly exposed trench sidewall and a portion of the trench capacitor's poly plate in order to isolate the DRAM cell from adjacent cells. The remaining poly strap, along the trench sidewall contacting the poly plate, is self aligned to contact the source of the DRAM Pass gate Field Effect Transistor (FET). After the shallow trench is filled with oxide, FET's are formed on the substrate, completing the cell. In an alternate embodiment, instead of recessing the poly plate, a shallow trench is formed spanning the entire width of the trench capacitor. The deposited polysilicon is selectively removed, having straps that strap the poly plate to the shallow trench sidewall.
摘要翻译：具有浅沟槽隔离（STI）的沟槽电容器DRAM单元，自对准掩埋带和制造电池的方法。沟槽电容器限定在衬底中。沟槽电容器的多晶硅（poly）板在衬底的表面下方凹入，并且沟槽侧壁暴露在聚合物上方。在与侧壁和沟槽电容器的多晶硅板接触的表面上沉积掺杂的多晶硅层。通过化学抛光或反应离子蚀刻（RIE）去除多层的水平部分。形成浅沟槽，去除一个以前暴露的沟槽侧壁和沟槽电容器的多晶片的一部分，以便将DRAM单元与相邻单元隔离。沿着与多晶硅板接触的沟槽侧壁的剩余多晶带自对准以接触DRAM通过栅极场效应晶体管（FET）的源极。在浅沟槽充满氧化物之后，在衬底上形成FET，从而完成电池。在替代实施例中，代替凹陷多晶硅，形成跨越沟槽电容器的整个宽度的浅沟槽。选择性地去除沉积的多晶硅，具有将多晶板绑定到浅沟槽侧壁的带。

6. 发明授权

US5376578A Method of fabricating a semiconductor device with raised diffusions and isolation 失效
标题翻译：制造具有凸起扩散和隔离的半导体器件的方法
公开(公告)号：US5376578A
公开(公告)日：1994-12-27
申请号：US169874
申请日：1993-12-17
申请人： Louis L. Hsu , Seiki Ogura , Joseph F. Shepard
发明人： Louis L. Hsu , Seiki Ogura , Joseph F. Shepard
IPC分类号： H01L21/8238 , H01L21/28 , H01L21/336 , H01L21/60 , H01L21/762 , H01L27/092 , H01L29/417 , H01L29/78 , H01L21/70
CPC分类号： H01L21/76897 , H01L21/28123 , H01L21/76237 , H01L29/41725 , H01L29/41783 , H01L29/6659 , H01L29/7833 , H01L29/66545
摘要： A method of forming a MOS FET in which the source, drain, and isolation are all raised above the surface of the single crystal silicon includes the steps of depositing a blanket gate stack including the gate oxide and a set of gate layers, and then depositing isolation members in apertures etched in the gate stack using the gate oxide as an etch stop. The sidewalls that are used to form an LDD source and drain separate a gate contact from source and drain contacts.
摘要翻译：源极，漏极和隔离物都形成在单晶硅表面以上的MOS FET的方法包括以下步骤：沉积包括栅极氧化物和一组栅极层的覆盖栅极堆叠，然后沉积使用栅极氧化物作为蚀刻停止在栅堆叠中蚀刻的孔中的隔离构件。用于形成LDD源和漏极的侧壁将栅极接触与源极和漏极接触分开。

7. 发明授权

US5516721A Isolation structure using liquid phase oxide deposition 失效
标题翻译：使用液相氧化物沉积的隔离结构
公开(公告)号：US5516721A
公开(公告)日：1996-05-14
申请号：US393599
申请日：1995-02-23
申请人： Carol Galli , Louis L. Hsu , Seiki Ogura , Joseph F. Shepard
发明人： Carol Galli , Louis L. Hsu , Seiki Ogura , Joseph F. Shepard
IPC分类号： H01L21/76 , H01L21/316 , H01L21/762 , H01L27/08 , H01L29/00
CPC分类号： H01L21/76224 , H01L21/02164 , H01L21/02282
摘要： A shallow trench isolation structure is formed by a process having a reduced number of steps and thermal budget by filling trenches by liquid phase deposition of an insulating semiconductor oxide and heat treating the deposit to form a layer of high quality thermal oxide at an interface between the deposited oxide and the body of semiconductor material (e.g. substrate) into which the trench extends. This process yields an isolation structure with reduced stress and reduced tendency to develop charge leakage. The structure can be readily and easily planarized, particularly if a polish-stop layer is applied over the body of semiconductor material and voids and contamination of the deposited oxide are substantially eliminated by self-aligned deposition above the trench in the volume of apertures on a resist used to form the trench.
摘要翻译：浅沟槽隔离结构通过具有减少步数和热量预算的工艺形成，通过用绝缘半导体氧化物的液相沉积填充沟槽并热处理沉积物以在层间的界面处形成高质量的热氧化物层沉积的氧化物和沟槽延伸到其中的半导体材料（例如衬底）的主体。该方法产生具有减小的应力和降低电荷泄漏倾向的隔离结构。该结构可以容易且容易地平坦化，特别是如果抛光停止层施加在半导体材料的主体上并且空隙和沉积的氧化物的污染基本上通过在孔的体积上的沟槽上的自对准沉积而被消除抗蚀剂用于形成沟槽。

8. 发明授权

US5384277A Method for forming a DRAM trench cell capacitor having a strap connection 失效
标题翻译：用于形成具有带连接的DRAM沟槽电池电容器的方法
公开(公告)号：US5384277A
公开(公告)日：1995-01-24
申请号：US169875
申请日：1993-12-17
申请人： Louis L. Hsu , Toshio Mii , Joseph F. Shepard , Seiki Ogura
发明人： Louis L. Hsu , Toshio Mii , Joseph F. Shepard , Seiki Ogura
IPC分类号： H01L21/285 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L21/28525 , H01L27/10829
摘要： A method of forming a MOS DRAM cell having a trench capacitor in which the strap connection to the trench capacitor, the source, drain, and isolation are all raised above the surface of the single crystal silicon includes the steps of forming the trench capacitors, depositing a blanket gate stack including the gate oxide and a set of gate layers, and then depositing isolation members in apertures etched in the gate stack using the gate oxide as an etch stop. The same sidewalls that are used to form an LDD source and drain combine with nitride sidewalls on a gate contact aperture to separate a gate contact from source and drain contacts.
摘要翻译：一种形成具有沟槽电容器的MOS DRAM单元的方法，其中与沟槽电容器的带连接，源极，漏极和隔离都在单晶硅的表面上方升高，包括以下步骤：形成沟槽电容器，包括栅极氧化物和一组栅极层的覆盖栅极堆叠，然后使用栅极氧化物作为蚀刻停止层，在隔离栅堆叠中蚀刻的孔中沉积隔离元件。用于形成LDD源极和漏极的相同侧壁与栅极接触孔上的氮化物侧壁结合，以将栅极接触与源极和漏极接触分开。

9. 发明授权

US5120668A Method of forming an inverse T-gate FET transistor 失效
标题翻译：形成逆T栅极FET晶体管的方法
公开(公告)号：US5120668A
公开(公告)日：1992-06-09
申请号：US727992
申请日：1991-07-10
申请人： Louis L. Hsu , Seiki Ogura , Joseph F. Shepard , Paul J. Tsang
发明人： Louis L. Hsu , Seiki Ogura , Joseph F. Shepard , Paul J. Tsang
IPC分类号： H01L21/336 , H01L29/423 , H01L29/78
CPC分类号： H01L29/66606 , H01L29/42376 , H01L29/7836
摘要： A method of forming an LDD field effect transistor with an inverted "T"-gate structure in which consecutive, conformal layers of polysilicon, metal and nitride or oxide are deposited to fill the recess in a composite interconnect layer on top of a trench isolated region of a semiconductor substrate. These conformal layers successively decrease in thickness and are selectively etched in two steps to form a self-aligned inverted T structure. A first reactive ion etch (RIE) step preferentially etches the exposed outer polysilicon to a certain depth. During a second step RIE the polysilicon layer is completely etched down to the a gate oxide surface and the metal layer is preferentially etched so that subtends only the remaining nitride or oxide cap.

10. 发明授权

US5241203A Inverse T-gate FET transistor with lightly doped source and drain region 失效
标题翻译：具有轻掺杂源极和漏极区域的反向T栅极FET晶体管
公开(公告)号：US5241203A
公开(公告)日：1993-08-31
申请号：US824228
申请日：1992-01-22
申请人： Louis L. Hsu , Seiki Ogura , Joseph F. Shepard , Paul J. Tsang
发明人： Louis L. Hsu , Seiki Ogura , Joseph F. Shepard , Paul J. Tsang
IPC分类号： H01L21/336 , H01L29/423 , H01L29/78
CPC分类号： H01L29/66606 , H01L29/42376 , H01L29/7836 , H01L2924/0002
摘要： A lightly doped drain, field effect transistor with an inverted "T"-gate structure has a gate electrode disposed on a polysilicon pad in a stack opening. The inner edge of a lightly-doped source and drain region is aligned with the gate electrode and its outer edge is aligned with an edge of the polysilicon pad. The inner edge of a heavily-doped source and drain region is aligned with the edge of the edge of the polysilicon pad and its outer edge is aligned with the wall surface that forms the opening. The inner edge of a source and drain contact region is aligned with the wall and extends under the stack.
摘要翻译：具有反向“T” - 门结构的轻掺杂漏极场效应晶体管具有设置在堆叠开口中的多晶硅焊盘上的栅电极。轻掺杂源极和漏极区域的内边缘与栅电极对准，并且其外边缘与多晶硅焊盘的边缘对准。重掺杂源极和漏极区域的内边缘与多晶硅焊盘的边缘的边缘对准，并且其外边缘与形成开口的壁表面对准。源极和漏极接触区域的内边缘与壁对准并在堆叠下方延伸。

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