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1. 发明授权

US5389559A Method of forming integrated interconnect for very high density DRAMs 失效
标题翻译：形成非常高密度DRAM的集成互连的方法
公开(公告)号：US5389559A
公开(公告)日：1995-02-14
申请号：US161763
申请日：1993-12-02
申请人： Chang-Ming Hsieh , Louis L. Hsu , Toshio Mii , Seiki Ogura , Joseph F. Shepard
发明人： Chang-Ming Hsieh , Louis L. Hsu , Toshio Mii , Seiki Ogura , Joseph F. Shepard
IPC分类号： H01L21/8242 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10861 , H01L27/10829
摘要： A trench capacitor DRAM cell with Shallow Trench Isolation (STI), a self-aligned buried strap and the method of making the cell. A trench capacitor is defined in a substrate. The trench capacitor's polysilicon (poly) plate is recessed below the surface of the substrate and the trench sidewalls are exposed above the poly. A doped poly layer is deposited over the surface contacting both the sidewall and the trench capacitor's poly plate. Horizontal portions of the poly layer are removed either through chemmech polishing or Reactive Ion Etching (RIE). A shallow trench is formed, removing one formerly exposed trench sidewall and a portion of the trench capacitor's poly plate in order to isolate the DRAM cell from adjacent cells. The remaining poly strap, along the trench sidewall contacting the poly plate, is self aligned to contact the source of the DRAM Pass gate Field Effect Transistor (FET). After the shallow trench is filled with oxide, FET's are formed on the substrate, completing the cell. In an alternate embodiment, instead of recessing the poly plate, a shallow trench is formed spanning the entire width of the trench capacitor. The deposited polysilicon is selectively removed, having straps that strap the poly plate to the shallow trench sidewall.
摘要翻译：具有浅沟槽隔离（STI）的沟槽电容器DRAM单元，自对准掩埋带和制造电池的方法。沟槽电容器限定在衬底中。沟槽电容器的多晶硅（poly）板在衬底的表面下方凹入，并且沟槽侧壁暴露在聚合物上方。在与侧壁和沟槽电容器的多晶硅板接触的表面上沉积掺杂的多晶硅层。通过化学抛光或反应离子蚀刻（RIE）去除多层的水平部分。形成浅沟槽，去除一个以前暴露的沟槽侧壁和沟槽电容器的多晶片的一部分，以便将DRAM单元与相邻单元隔离。沿着与多晶硅板接触的沟槽侧壁的剩余多晶带自对准以接触DRAM通过栅极场效应晶体管（FET）的源极。在浅沟槽充满氧化物之后，在衬底上形成FET，从而完成电池。在替代实施例中，代替凹陷多晶硅，形成跨越沟槽电容器的整个宽度的浅沟槽。选择性地去除沉积的多晶硅，具有将多晶板绑定到浅沟槽侧壁的带。

2. 发明授权

US5384277A Method for forming a DRAM trench cell capacitor having a strap connection 失效
标题翻译：用于形成具有带连接的DRAM沟槽电池电容器的方法
公开(公告)号：US5384277A
公开(公告)日：1995-01-24
申请号：US169875
申请日：1993-12-17
申请人： Louis L. Hsu , Toshio Mii , Joseph F. Shepard , Seiki Ogura
发明人： Louis L. Hsu , Toshio Mii , Joseph F. Shepard , Seiki Ogura
IPC分类号： H01L21/285 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L21/28525 , H01L27/10829
摘要： A method of forming a MOS DRAM cell having a trench capacitor in which the strap connection to the trench capacitor, the source, drain, and isolation are all raised above the surface of the single crystal silicon includes the steps of forming the trench capacitors, depositing a blanket gate stack including the gate oxide and a set of gate layers, and then depositing isolation members in apertures etched in the gate stack using the gate oxide as an etch stop. The same sidewalls that are used to form an LDD source and drain combine with nitride sidewalls on a gate contact aperture to separate a gate contact from source and drain contacts.
摘要翻译：一种形成具有沟槽电容器的MOS DRAM单元的方法，其中与沟槽电容器的带连接，源极，漏极和隔离都在单晶硅的表面上方升高，包括以下步骤：形成沟槽电容器，包括栅极氧化物和一组栅极层的覆盖栅极堆叠，然后使用栅极氧化物作为蚀刻停止层，在隔离栅堆叠中蚀刻的孔中沉积隔离元件。用于形成LDD源极和漏极的相同侧壁与栅极接触孔上的氮化物侧壁结合，以将栅极接触与源极和漏极接触分开。

3. 发明授权

US5369049A DRAM cell having raised source, drain and isolation 失效
标题翻译： DRAM电池具有升高的源极，漏极和隔离
公开(公告)号：US5369049A
公开(公告)日：1994-11-29
申请号：US169873
申请日：1993-12-17
申请人： Joyce E. Acocella , Louis L. Hsu , Seiki Ogura , Nivo Rovedo , Joseph F. Shepard
发明人： Joyce E. Acocella , Louis L. Hsu , Seiki Ogura , Nivo Rovedo , Joseph F. Shepard
IPC分类号： H01L27/108 , H01L27/00 , H01L21/70
CPC分类号： H01L27/10829
摘要： A method of forming a MOS DRAM cell having a trench capacitor in which the strap connection to the trench capacitor, the source, drain, and isolation are all raised above the surface of the single crystal silicon includes the steps of forming the trench capacitors, depositing a blanket gate stack including the gate oxide and a set of gate layers, and then depositing isolation members in apertures etched in the gate stack using the gate oxide as an etch stop. The same sidewalls that are used to form an LDD source and drain form a self-aligned aperture for a surface strap that insulates the strap from misaligned portions of the gate stack.
摘要翻译：一种形成具有沟槽电容器的MOS DRAM单元的方法，其中与沟槽电容器的带连接，源极，漏极和隔离都在单晶硅的表面上方升高，包括以下步骤：形成沟槽电容器，包括栅极氧化物和一组栅极层的覆盖栅极堆叠，然后使用栅极氧化物作为蚀刻停止层，在隔离栅堆叠中蚀刻的孔中沉积隔离元件。用于形成LDD源和漏极的相同侧壁形成用于将带与栅堆叠的未对准部分绝缘的表面带的自对准孔。

4. 发明授权

US5376578A Method of fabricating a semiconductor device with raised diffusions and isolation 失效
标题翻译：制造具有凸起扩散和隔离的半导体器件的方法
公开(公告)号：US5376578A
公开(公告)日：1994-12-27
申请号：US169874
申请日：1993-12-17
申请人： Louis L. Hsu , Seiki Ogura , Joseph F. Shepard
发明人： Louis L. Hsu , Seiki Ogura , Joseph F. Shepard
IPC分类号： H01L21/8238 , H01L21/28 , H01L21/336 , H01L21/60 , H01L21/762 , H01L27/092 , H01L29/417 , H01L29/78 , H01L21/70
CPC分类号： H01L21/76897 , H01L21/28123 , H01L21/76237 , H01L29/41725 , H01L29/41783 , H01L29/6659 , H01L29/7833 , H01L29/66545
摘要： A method of forming a MOS FET in which the source, drain, and isolation are all raised above the surface of the single crystal silicon includes the steps of depositing a blanket gate stack including the gate oxide and a set of gate layers, and then depositing isolation members in apertures etched in the gate stack using the gate oxide as an etch stop. The sidewalls that are used to form an LDD source and drain separate a gate contact from source and drain contacts.
摘要翻译：源极，漏极和隔离物都形成在单晶硅表面以上的MOS FET的方法包括以下步骤：沉积包括栅极氧化物和一组栅极层的覆盖栅极堆叠，然后沉积使用栅极氧化物作为蚀刻停止在栅堆叠中蚀刻的孔中的隔离构件。用于形成LDD源和漏极的侧壁将栅极接触与源极和漏极接触分开。

5. 发明授权

US5516721A Isolation structure using liquid phase oxide deposition 失效
标题翻译：使用液相氧化物沉积的隔离结构
公开(公告)号：US5516721A
公开(公告)日：1996-05-14
申请号：US393599
申请日：1995-02-23
申请人： Carol Galli , Louis L. Hsu , Seiki Ogura , Joseph F. Shepard
发明人： Carol Galli , Louis L. Hsu , Seiki Ogura , Joseph F. Shepard
IPC分类号： H01L21/76 , H01L21/316 , H01L21/762 , H01L27/08 , H01L29/00
CPC分类号： H01L21/76224 , H01L21/02164 , H01L21/02282
摘要： A shallow trench isolation structure is formed by a process having a reduced number of steps and thermal budget by filling trenches by liquid phase deposition of an insulating semiconductor oxide and heat treating the deposit to form a layer of high quality thermal oxide at an interface between the deposited oxide and the body of semiconductor material (e.g. substrate) into which the trench extends. This process yields an isolation structure with reduced stress and reduced tendency to develop charge leakage. The structure can be readily and easily planarized, particularly if a polish-stop layer is applied over the body of semiconductor material and voids and contamination of the deposited oxide are substantially eliminated by self-aligned deposition above the trench in the volume of apertures on a resist used to form the trench.
摘要翻译：浅沟槽隔离结构通过具有减少步数和热量预算的工艺形成，通过用绝缘半导体氧化物的液相沉积填充沟槽并热处理沉积物以在层间的界面处形成高质量的热氧化物层沉积的氧化物和沟槽延伸到其中的半导体材料（例如衬底）的主体。该方法产生具有减小的应力和降低电荷泄漏倾向的隔离结构。该结构可以容易且容易地平坦化，特别是如果抛光停止层施加在半导体材料的主体上并且空隙和沉积的氧化物的污染基本上通过在孔的体积上的沟槽上的自对准沉积而被消除抗蚀剂用于形成沟槽。

6. 发明授权

US5120668A Method of forming an inverse T-gate FET transistor 失效
标题翻译：形成逆T栅极FET晶体管的方法
公开(公告)号：US5120668A
公开(公告)日：1992-06-09
申请号：US727992
申请日：1991-07-10
申请人： Louis L. Hsu , Seiki Ogura , Joseph F. Shepard , Paul J. Tsang
发明人： Louis L. Hsu , Seiki Ogura , Joseph F. Shepard , Paul J. Tsang
IPC分类号： H01L21/336 , H01L29/423 , H01L29/78
CPC分类号： H01L29/66606 , H01L29/42376 , H01L29/7836
摘要： A method of forming an LDD field effect transistor with an inverted "T"-gate structure in which consecutive, conformal layers of polysilicon, metal and nitride or oxide are deposited to fill the recess in a composite interconnect layer on top of a trench isolated region of a semiconductor substrate. These conformal layers successively decrease in thickness and are selectively etched in two steps to form a self-aligned inverted T structure. A first reactive ion etch (RIE) step preferentially etches the exposed outer polysilicon to a certain depth. During a second step RIE the polysilicon layer is completely etched down to the a gate oxide surface and the metal layer is preferentially etched so that subtends only the remaining nitride or oxide cap.

7. 发明授权

US5241203A Inverse T-gate FET transistor with lightly doped source and drain region 失效
标题翻译：具有轻掺杂源极和漏极区域的反向T栅极FET晶体管
公开(公告)号：US5241203A
公开(公告)日：1993-08-31
申请号：US824228
申请日：1992-01-22
申请人： Louis L. Hsu , Seiki Ogura , Joseph F. Shepard , Paul J. Tsang
发明人： Louis L. Hsu , Seiki Ogura , Joseph F. Shepard , Paul J. Tsang
IPC分类号： H01L21/336 , H01L29/423 , H01L29/78
CPC分类号： H01L29/66606 , H01L29/42376 , H01L29/7836 , H01L2924/0002
摘要： A lightly doped drain, field effect transistor with an inverted "T"-gate structure has a gate electrode disposed on a polysilicon pad in a stack opening. The inner edge of a lightly-doped source and drain region is aligned with the gate electrode and its outer edge is aligned with an edge of the polysilicon pad. The inner edge of a heavily-doped source and drain region is aligned with the edge of the edge of the polysilicon pad and its outer edge is aligned with the wall surface that forms the opening. The inner edge of a source and drain contact region is aligned with the wall and extends under the stack.
摘要翻译：具有反向“T” - 门结构的轻掺杂漏极场效应晶体管具有设置在堆叠开口中的多晶硅焊盘上的栅电极。轻掺杂源极和漏极区域的内边缘与栅电极对准，并且其外边缘与多晶硅焊盘的边缘对准。重掺杂源极和漏极区域的内边缘与多晶硅焊盘的边缘的边缘对准，并且其外边缘与形成开口的壁表面对准。源极和漏极接触区域的内边缘与壁对准并在堆叠下方延伸。

8. 发明授权

US6144081A Method to suppress subthreshold leakage due to sharp isolation corners in submicron FET structures 失效
标题翻译：抑制由亚微米FET结构中的尖锐隔离角引起的亚阈值泄漏的方法
公开(公告)号：US6144081A
公开(公告)日：2000-11-07
申请号：US540961
申请日：1995-10-11
申请人： Louis Lu-Chen Hsu , Chang-Ming Hsieh , Lyndon Ronald Logan , Jack Allan Mandelman , Seiki Ogura
发明人： Louis Lu-Chen Hsu , Chang-Ming Hsieh , Lyndon Ronald Logan , Jack Allan Mandelman , Seiki Ogura
IPC分类号： G03F1/08 , H01L21/027 , H01L21/28 , H01L21/336 , H01L21/76 , H01L29/423 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/66575 , H01L21/28123 , H01L29/4238 , H01L29/7831
摘要： A field effect transistor (FET) device, which mitigates leakage current induced along the edges of the FET device, is isolated by shallow trench isolation having a channel width between a first and a second shallow trench at a first and second shallow trench edges. A gate extends across the channel width between the first and second shallow trenches. The gate has a first length at the shallow trench edges and a second length less than the first length between the shallow trench edges. The first length and the second length are related such that the threshold voltage, V.sub.t, at the shallow trench edges is substantially equal to V.sub.t between the shallow trench edges. The gate structure of the FET device is produced using a unique phase shift mask that allows the manufacture of submicron FET devices with very small channel lengths.
摘要翻译：通过在第一和第二浅沟槽边缘处具有第一和第二浅沟槽之间的沟道宽度的浅沟槽隔离来隔离减轻沿着FET器件边缘感应的漏电流的场效应晶体管（FET）器件。栅极延伸穿过第一和第二浅沟槽之间的沟道宽度。栅极在浅沟槽边缘处具有第一长度，并且具有小于浅沟槽边缘之间的第一长度的第二长度。第一长度和第二长度相关联，使得浅沟槽边缘处的阈值电压Vt基本上等于浅沟槽边缘之间的Vt。 FET器件的栅极结构使用独特的相移掩模产生，其允许制造具有非常小的沟道长度的亚微米FET器件。

9. 发明授权

US6107141A Flash EEPROM 有权
标题翻译：闪存EEPROM
公开(公告)号：US6107141A
公开(公告)日：2000-08-22
申请号：US163151
申请日：1998-09-29
申请人： Louis Lu-Chen Hsu , Chang-Ming Hsieh , Seiki Ogura
发明人： Louis Lu-Chen Hsu , Chang-Ming Hsieh , Seiki Ogura
IPC分类号： G11C17/00 , G11C16/04 , G11C16/06 , H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L29/66825 , G11C16/0425 , H01L21/2815 , H01L27/115 , H01L29/42328 , H01L29/7885
摘要： An EEPROM cell includes a dual-gate transistor having a floating gate for storing the data and a select gate to access the cell, the two gates each being formed from poly sidewalls and being separated by a thin vertical oxide member that is formed by growing oxide on the vertical poly sidewalls of an aperture in which the select gate is formed, so that the final structure has dimensions that are less than those obtainable with optical lithography because both gates are sidewalls and therefore not limited to the dimensions achievable with optical lithography.
摘要翻译： EEPROM单元包括具有用于存储数据的浮动栅极和访问单元的选择栅极的双栅极晶体管，每个栅极均由多边形成，并由通过生长氧化物形成的薄垂直氧化物元件分隔开在其中形成选择栅极的孔径的垂直多边形上，使得最终结构的尺寸小于通过光学光刻获得的尺寸，因为两个栅极都是侧壁，因此不限于光学光刻实现的尺寸。

10. 发明授权

US5528062A High-density DRAM structure on soi 失效
标题翻译：高密度DRAM结构在soi上
公开(公告)号：US5528062A
公开(公告)日：1996-06-18
申请号：US900041
申请日：1992-06-17
申请人： Chang-Ming Hsieh , Louis L. C. Hsu , Seiki Ogura
发明人： Chang-Ming Hsieh , Louis L. C. Hsu , Seiki Ogura
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10829 , H01L27/10823
摘要： A high density, DRAM cell array with a very short channel, vertical gate transfer transistor that can be manufactured using conventional photolithography process steps. The conventional four-by-four DRAM array shown schematically in FIG. 1a is rearranged to the shared-gate, double-bit array shown schematically in FIG. 1b. Trench storage capacitors and vertical FET transistors are arranged in pairs with a common vertical gate and a common substrate, allowing both bit and substrate contacts to be shared by adjacent cells.
摘要翻译：具有非常短的通道的高密度DRAM单元阵列，垂直栅极转移晶体管可以使用常规光刻工艺步骤制造。图1中示意性示出的常规四乘四DRAM阵列。 1a被重新布置到图1中示意性示出的共享门双位阵列。 1b。沟槽存储电容器和垂直FET晶体管与公共垂直栅极和公共衬底成对配置，允许位和衬底触点由相邻单元共享。

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