专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06429067B1 Dual mask process for semiconductor devices 失效
标题翻译：半导体器件的双掩模工艺
公开(公告)号：US06429067B1
公开(公告)日：2002-08-06
申请号：US09765036
申请日：2001-01-17
申请人： Joyce C. Liu , James C. Brighten , Jeffrey J. Brown , John Golz , George A. Kaplita , Rebecca Mih , Senthil Srinivasan , Jin Jwang Wu , Teresa J. Wu , Chienfan Yu
发明人： Joyce C. Liu , James C. Brighten , Jeffrey J. Brown , John Golz , George A. Kaplita , Rebecca Mih , Senthil Srinivasan , Jin Jwang Wu , Teresa J. Wu , Chienfan Yu
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L21/823842 , H01L27/10873
摘要： A method for fabricating a dual gate structure, comprising providing a semiconductor substrate having a first device area and a second device area covered by a gate oxide layer and a polysilicon layer, forming a first hard mask over the polysilicon layer, said first hard mask being a material that is resistant to a first etching, but susceptible to a second etching forming a second hard mask over the first hard mask and the polysilicon layer, said second hard mask being a material that is resistant to a second etching, but susceptible to a first etching, patterning and etching said second hard mask with a first etch to form a gate pattern on a first device area, and patterning and etching said first hard mask with a second etch to transfer gate patterns on the first and second device areas.
摘要翻译：一种制造双栅结构的方法，包括提供半导体衬底，其具有由栅极氧化层和多晶硅层覆盖的第一器件区域和第二器件区域，在所述多晶硅层上形成第一硬掩模，所述第一硬掩模为耐受第一蚀刻的材料，但易于在第一硬掩模和多晶硅层上形成第二硬掩模的第二蚀刻，所述第二硬掩模是耐第二蚀刻的材料，但易受第首先用第一蚀刻蚀刻图案并蚀刻所述第二硬掩模，以在第一器件区域上形成栅极图案，并用第二蚀刻图案化和蚀刻所述第一硬掩模以在第一和第二器件区域上传输栅极图案。

2. 发明授权

US06486505B1 Semiconductor contact and method of forming the same 有权
标题翻译：半导体接触及其形成方法
公开(公告)号：US06486505B1
公开(公告)日：2002-11-26
申请号：US09535445
申请日：2000-03-24
申请人： Thomas S. Rupp , Jeffrey P. Gambino , Peter Hoh , Senthil Srinivasan
发明人： Thomas S. Rupp , Jeffrey P. Gambino , Peter Hoh , Senthil Srinivasan
IPC分类号： H01L27108
CPC分类号： H01L27/10873
摘要： In one aspect, the present invention discloses a transistor device (see e.g., FIG. 3) that includes first and second source/drain regions 124a and 126 disposed in a semiconductor body 122 and separated by a channel region 128a. A dielectric layer 134a overlies the channel region 128a and a gate electrode 130a/132a overlies the dielectric layer 134a. In the preferred embodiment, the gate electrode includes a polysilicon layer 130a that extends a first lateral distance over the dielectric layer and a silicide layer 132a that extends a second lateral distance over the first polysilicon layer. In this example, the first lateral distance is greater than the second lateral distance.
摘要翻译：一方面，本发明公开了一种晶体管器件（参见例如图3），其包括设置在半导体本体122中并由通道区域128a隔开的第一和第二源极/漏极区域124a和126。电介质层134a覆盖在沟道区128a上，栅电极130a / 132a覆盖在电介质层134a上。在优选实施例中，栅电极包括在电介质层上延伸第一横向距离的多晶硅层130a和在第一多晶硅层上延伸第二横向距离的硅化物层132a。在该示例中，第一横向距离大于第二横向距离。

3. 发明授权

US06294817B1 Source/drain-on insulator (S/DOI) field effect transistor using oxidized amorphous silicon and method of fabrication 失效
标题翻译：使用氧化非晶硅的源极/漏极绝缘体（S / DOI）场效应晶体管及其制造方法
公开(公告)号：US06294817B1
公开(公告)日：2001-09-25
申请号：US09459483
申请日：1999-12-13
申请人： Senthil Srinivasan , Bomy Chen
发明人： Senthil Srinivasan , Bomy Chen
IPC分类号： H01L2972
CPC分类号： H01L29/66636 , H01L29/0653
摘要： Source and drain regions of field effect transistors are fabricated with an electrically insulating layer formed thereunder so as to reduce junction capacitance between each and a semiconductor body in which the regions are formed. Shallow trench isolation partially surrounds each transistor so as to further electrically isolate the source and drain regions from the semiconductor body. Typically for a single transistor only one surface of each drain and source region make direct contact to the semiconductor body and these surfaces are on opposite sides of a channel region of each transistor. One method of fabrication of the source and drain regions is to form an isolating isolation region around active areas in which a transistor is to be formed in a semiconductor body. Trenches separated by portions of the body are then formed in the active areas in which transistors are to be formed. On bottom surfaces of the trenches are formed an electrically insulating layer. The trenches are then filled with semiconductor material of a conductivity type opposite that of the semiconductor body. The semiconductor filled portion of each trench then serves as a drain and/or source of a field effect transistor.
摘要翻译：场效应晶体管的源极和漏极区域由其下面形成的电绝缘层制造，以便减小其中形成区域的半导体本体之间的结电容。浅沟槽隔离部分地围绕每个晶体管，以进一步将源极和漏极区域与半导体本体电隔离。通常，对于单个晶体管，每个漏极和源极区域的仅一个表面与半导体本体直接接触，并且这些表面位于每个晶体管的沟道区域的相对侧上。源极和漏极区域的一种制造方法是在半导体本体内形成晶体管的有源区域周围形成隔离隔离区域。然后在其中将形成晶体管的有源区域中形成由身体的部分分开的沟槽。在沟槽的底表面上形成电绝缘层。然后用与半导体本体相反的导电类型的半导体材料填充沟槽。然后，每个沟槽的半导体填充部分用作场效应晶体管的漏极和/或源极。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式