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1. 发明申请

US20050093854A1 System for synchronizing display of images in a multi-display computer system 失效
标题翻译：用于在多显示器计算机系统中同步显示图像的系统
公开(公告)号：US20050093854A1
公开(公告)日：2005-05-05
申请号：US10695779
申请日：2003-10-30
申请人： Joseph Kennedy , John Klenoski , Greg Sadowski
发明人： Joseph Kennedy , John Klenoski , Greg Sadowski
IPC分类号： G06F3/14 , G09G3/20 , G09G5/00 , G09G5/12
CPC分类号： G09G3/2096 , G06F3/1423 , G09G5/008 , G09G5/12 , G09G2360/02
摘要： An image display system synchronizes the display of images on a plurality of display devices. The system includes a first computer system generating a first signal representing first image data to be displayed on a first display device, a second computer system generating a second signal representing second image data to be displayed on a second display device, and means for synchronizing the first and second image data. The synchronizing means includes a phase-locked loop circuit having a digital rate controller. The digital rate controller allows programmable control of the speed of the phase-locked loop.
摘要翻译：图像显示系统使多个显示装置上的图像的显示同步。该系统包括：第一计算机系统，生成表示要显示在第一显示装置上的第一图像数据的第一信号;第二计算机系统，生成表示要显示在第二显示装置上的第二图像数据的第二信号;以及装置，第一和第二图像数据。同步装置包括具有数字速率控制器的锁相环电路。数字速率控制器允许可编程控制锁相环的速度。

2. 发明授权

US09696784B2 Direct hardware access media player 有权
公开(公告)号：US09696784B2
公开(公告)日：2017-07-04
申请号：US13620389
申请日：2012-09-14
申请人： Greg Sadowski , Gabor Sines
发明人： Greg Sadowski , Gabor Sines
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3206 , G06F1/3287 , Y02D10/171
摘要： A system, method and a computer program product for processing media content on a media player having direct access to hardware are provided in exemplary embodiments. When the media player is initialized, an operating system is placed into a stand-by mode that decreases power consumption on an electronic device. Instead of the operating system, a hardware pipeline processes media content. A hardware pipeline is dedicated to process a media content based on the media content type. The media content is processed using the dedicated hardware pipeline to reduce the power consumption during processing.

3. 发明申请

US20140082389A1 Direct Hardware Access Media Player 有权
标题翻译：直接硬件访问媒体播放器
公开(公告)号：US20140082389A1
公开(公告)日：2014-03-20
申请号：US13620389
申请日：2012-09-14
申请人： Greg Sadowski , Gabor Sines
发明人： Greg Sadowski , Gabor Sines
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3206 , G06F1/3287 , Y02D10/171
摘要： A system, method and a computer program product for processing media content on a media player having direct access to hardware are provided in exemplary embodiments. When the media player is initialized, an operating system is placed into a stand-by mode that decreases power consumption on an electronic device. Instead of the operating system, a hardware pipeline processes media content. A hardware pipeline is dedicated to process a media content based on the media content type. The media content is processed using the dedicated hardware pipeline to reduce the power consumption during processing.
摘要翻译：在示例性实施例中提供了用于在具有直接访问硬件的媒体播放器上处理媒体内容的系统，方法和计算机程序产品。当媒体播放器被初始化时，操作系统被置于能够减少电子设备的功耗的待机模式。硬件管道代替操作系统处理媒体内容。硬件管道专用于基于媒体内容类型来处理媒体内容。使用专用硬件流水线处理媒体内容，以减少处理过程中的功耗。

4. 发明申请

US20130141442A1 METHOD AND APPARATUS FOR MULTI-CHIP PROCESSING 审中-公开
标题翻译：多芯片加工的方法和装置
公开(公告)号：US20130141442A1
公开(公告)日：2013-06-06
申请号：US13311908
申请日：2011-12-06
申请人： John W. Brothers , Greg Sadowski , Konstantine Iourcha , Bryan Black
发明人： John W. Brothers , Greg Sadowski , Konstantine Iourcha , Bryan Black
IPC分类号： G06F15/16
CPC分类号： G06T1/20 , H01L25/0652 , H01L25/18 , H01L2224/16145 , H01L2224/16227 , H01L2224/17181 , H01L2224/32225 , H01L2224/73204 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/15192 , H01L2924/15311
摘要： Various methods, computer-readable mediums and apparatus are disclosed. In one aspect, a method of generating a graphical image on a display device is provided that includes splitting geometry level processing of the image between plural processors coupled to an interposer. Primitives are created using each of the plural processors. Any primitives not needed to render the image are discarded. The image is rasterized using each of the plural processors. A portion of the image is rendered using one of the plural processors and any remaining portion of the image using one or more of the other plural processors.
摘要翻译：公开了各种方法，计算机可读介质和装置。在一个方面，提供了一种在显示设备上生成图形图像的方法，其包括在耦合到插入器的多个处理器之间分割图像的几何级别处理。使用多个处理器中的每一个创建基元。丢弃不需要渲染图像的任何图元。使用多个处理器中的每一个来对图像进行光栅化。图像的一部分使用多个处理器之一和图像的任何剩余部分使用其他多个处理器中的一个或多个来渲染。

5. 发明授权

US08249164B2 Sub-frame video decoding 有权
标题翻译：子帧视频解码
公开(公告)号：US08249164B2
公开(公告)日：2012-08-21
申请号：US11627757
申请日：2007-01-26
申请人： Greg Sadowski
发明人： Greg Sadowski
IPC分类号： H04N11/00 , H04N7/26 , H04N5/445 , G06F3/14
CPC分类号： H04N7/17318 , H04N21/4316 , H04N21/4728
摘要： A video processing apparatus, for use in a video receiver, includes a decoder configured to decode encoded video information into decoded video information and to output the decoded information, and a configuration module coupled to the decoder and configured to a provide a control signal to the decoder indicative of a reduced-image portion of the video frames to be displayed, where the decoder is configured to respond to the control signal by decoding first macroblocks of the video information within the reduced-image portion and second macroblocks of the video information, in a reference section, adjacent the first macroblocks to account for motion of the images in the reduced-image portion without decoding third macroblocks lying outside of the reduced-image portion and the reference section.
摘要翻译：一种在视频接收机中使用的视频处理装置包括：解码器，被配置为将经编码的视频信息解码为经解码的视频信息并输出解码的信息;以及配置模块，其耦合到解码器并且被配置为向指示要显示的视频帧的缩小图像部分的解码器，其中解码器被配置为通过解码视频信息中的视频信息的第一宏块以及视频信息的第二宏块来响应控制信号，参考部分，与第一宏块相邻以解决缩小图像部分中的图像的运动，而不对位于缩小图像部分和参考部分之外的第三宏块进行解码。

6. 发明申请

US20120066471A1 ALLOCATION OF MEMORY BUFFERS BASED ON PREFERRED MEMORY PERFORMANCE 审中-公开
标题翻译：基于优先记忆性能的内存缓冲区分配
公开(公告)号：US20120066471A1
公开(公告)日：2012-03-15
申请号：US13302499
申请日：2011-11-22
申请人： Greg Sadowski , Philip J. Rogers , John Wakefield Brothers, III , W. Fritz Kruger , Konstantine I. Iourcha
发明人： Greg Sadowski , Philip J. Rogers , John Wakefield Brothers, III , W. Fritz Kruger , Konstantine I. Iourcha
IPC分类号： G06F12/00
CPC分类号： G06F13/1673 , G06F13/1684 , Y02D10/14
摘要： A method and system are provided for associating one or more memory buffers in a computing system with a plurality of memory channels. The method and apparatus associates one or more memory buffers with a plurality of memory banks based on preferred performance settings, wherein the plurality of memory banks spans over one or more of the plurality of memory channels. Additionally, the method and apparatus accesses the one or more memory buffers based on the preferred performance settings. Further, the method and apparatus can, in response to accessing the one or more memory buffers based on the preferred performance settings, determine whether the preferred performance settings are being satisfied.
摘要翻译：提供一种用于将计算系统中的一个或多个存储器缓冲器与多个存储器通道相关联的方法和系统。该方法和装置基于优选的性能设置将一个或多个存储器缓冲器与多个存储器组相关联，其中多个存储器跨越多个存储器通道中的一个或多个存储器通道。另外，该方法和装置基于优选的性能设置来访问一个或多个存储器缓冲器。此外，所述方法和装置可以响应于基于优选性能设置访问所述一个或多个存储器缓冲器来确定是否满足所述优选性能设置。

7. 发明授权

US07804435B2 Video decoder with reduced power consumption and method thereof 有权
标题翻译：具有降低功耗的视频解码器及其方法
公开(公告)号：US07804435B2
公开(公告)日：2010-09-28
申请号：US11469335
申请日：2006-08-31
申请人： Greg Sadowski , George Jacobs , Paul Chow
发明人： Greg Sadowski , George Jacobs , Paul Chow
IPC分类号： H03M1/12
CPC分类号： H04N19/127 , H04N19/136 , H04N19/172 , H04N19/176 , H04N19/179 , H04N19/42 , H04N19/44 , H04N19/61
摘要： A video decoder (10) with reduced power consumption includes a power management controller (45) that is operative to select one of a plurality of different power consumption states for a video decoder (10), and, in response to the determination, vary power consumption of at least one operational portion of the video decoder (10). In addition, in one example, a method (200) for reducing power consumption for a video decoder (10) includes determining input stream encoding description data (34) to select one of a plurality of different power consumption states for a video decoder (10) and, in response to the determination, varying power consumption of at least one operational portion of the video decoder (10).
摘要翻译：具有降低的功耗的视频解码器（10）包括功率管理控制器（45），其可操作以选择视频解码器（10）的多个不同功耗状态中的一个，并且响应于该确定，改变功率消耗视频解码器（10）的至少一个操作部分。此外，在一个示例中，用于降低视频解码器（10）的功耗的方法（200）包括确定输入流编码描述数据（34）以选择视频解码器（10）的多个不同功耗状态之一），并且响应于所述确定，改变所述视频解码器（10）的至少一个操作部分的功率消耗。

8. 发明授权

US07427990B2 Data replacement method and circuit for motion prediction cache 有权
标题翻译：运动预测缓存的数据替换方法和电路
公开(公告)号：US07427990B2
公开(公告)日：2008-09-23
申请号：US11342985
申请日：2006-01-30
申请人： Greg Sadowski
发明人： Greg Sadowski
IPC分类号： G06K9/36 , G09G5/36 , G06T15/70 , G06T7/20 , G06T1/20 , H04N7/26 , H04N7/50
CPC分类号： G09G5/393 , G09G2320/0261 , G09G2320/106 , G09G2360/121 , G09G2360/122
摘要： A system for decoding a video bitstream and a method for replacing image data in a motion prediction cache are described. For each of the cache lines, a tag distance between pixels stored in the cache line and uncached pixels that are to be stored in the cache is calculated. The calculated tag distance is used to determine whether the pixels are outside a local image area defined about the uncached pixels. Pixels determined to be outside the local image area are replaced with the uncached pixels. The motion prediction cache can be organized as sets of cache lines and the method can be performed for each of the cache lines in one of the sets. The definition of the sets can be changed in response to cache performance. Similarly, the local image area can be redefined in response to cache performance.
摘要翻译：描述用于解码视频比特流的系统和用于替换运动预测高速缓存中的图像数据的方法。对于每个高速缓存行，计算存储在高速缓存行中的像素和要存储在高速缓存中的未缓存像素之间的标签距离。计算的标签距离用于确定像素是否在关于未缓冲像素定义的局部图像区域之外。被确定为在本地图像区域之外的像素被替换为未被缓冲的像素。运动预测高速缓存可以被组织成高速缓存行集合，并且可以针对其中一个集合中的每个高速缓存线执行该方法。可以根据缓存性能来更改集合的定义。类似地，可以响应于高速缓存性能重新定义本地图像区域。

9. 发明授权

US09417679B2 Adaptive connected standby for a computing device 有权
标题翻译：计算设备的自适应连接待机
公开(公告)号：US09417679B2
公开(公告)日：2016-08-16
申请号：US13674476
申请日：2012-11-12
申请人： Greg Sadowski , Alexander J. Branover , Maurice B. Steinman
发明人： Greg Sadowski , Alexander J. Branover , Maurice B. Steinman
IPC分类号： G06F1/32
CPC分类号： G06F1/3212 , G06F1/3287 , Y02D10/171 , Y02D10/174
摘要： Various computing devices and methods of managing the power consumption thereby are disclosed. In one aspect, a method of managing power consumption of a computing device that has a battery is provided. The method includes cycling the computing device between a connected standby active state and a connected standby idle state. The duration of the connected standby idle state is set based at least in part on a charge level of the battery.
摘要翻译：公开了各种计算设备和管理功耗的方法。一方面，提供一种管理具有电池的计算装置的功耗的方法。该方法包括在连接的待机活动状态和连接的待机空闲状态之间循环计算设备。连接的待机空闲状态的持续时间至少部分地基于电池的充电水平来设定。

10. 发明授权

US09041720B2 Static image retiling and power management method and circuit 有权
标题翻译：静态图像复位和电源管理方法及电路
公开(公告)号：US09041720B2
公开(公告)日：2015-05-26
申请号：US12642257
申请日：2009-12-18
申请人： Greg Sadowski , Warren Fritz Kruger , John Wakefield Brothers, III , David I.J. Glen , Stephen David Presant
发明人： Greg Sadowski , Warren Fritz Kruger , John Wakefield Brothers, III , David I.J. Glen , Stephen David Presant
IPC分类号： G09G5/39 , G06F1/32
CPC分类号： G06F1/3275 , G06F1/3225 , Y02D10/14
摘要： A circuit includes memory retiling methods which distribute image information among a plurality of memory channels producing reconfigured image information distributed among a subset of the plurality of memory channels allowing memory channels outside of the subset to be placed into a power save mode to reduce power consumption. Additional methods are disclosed for further reductions in power consumption.
摘要翻译：电路包括在多个存储器通道之间分配图像信息的存储器重绘方法，其产生分布在多个存储器通道的子集之间的重新配置的图像信息，允许该子集外部的存储器通道进入省电模式以降低功耗。公开了用于进一步降低功耗的附加方法。

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