专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08909840B2 Data bus inversion coding 有权
标题翻译：数据总线反转编码
公开(公告)号：US08909840B2
公开(公告)日：2014-12-09
申请号：US13330482
申请日：2011-12-19
申请人： Aaron J. Nygren , Anwar Kashem , Bryan Black , James Michael O'Connor , Warren Fritz Kruger
发明人： Aaron J. Nygren , Anwar Kashem , Bryan Black , James Michael O'Connor , Warren Fritz Kruger
IPC分类号： G06F13/28
CPC分类号： G06F13/4273 , Y02D10/14 , Y02D10/151
摘要： Techniques are disclosed relating to data inversion encoding. In one embodiment, an apparatus includes an interface circuit. The interface circuit is configured to perform first and second data bursts that include respective pluralities of data transmissions encoded using an inversion coding scheme. In such an embodiment, the initial data transmission of the second data burst is encoded using the final data transmission of the first data burst. In some embodiments, the first and second data bursts correspond to successive write operations or successive read operations to a memory module from a memory PHY.
摘要翻译：公开了涉及数据反转编码的技术。在一个实施例中，一种装置包括接口电路。接口电路被配置为执行包括使用反转编码方案编码的相应多个数据传输的第一和第二数据突发。在这样的实施例中，使用第一数据突发的最终数据传输对第二数据脉冲串的初始数据传输进行编码。在一些实施例中，第一和第二数据脉冲串对应于来自存储器PHY的存储器模块的连续写操作或连续读操作。

2. 发明授权

US08671304B2 Adjustment of write timing based on a training signal 有权
标题翻译：基于训练信号调整写时序
公开(公告)号：US08671304B2
公开(公告)日：2014-03-11
申请号：US12846965
申请日：2010-07-30
申请人： Aaron John Nygren , Ming-Ju Edward Lee , Shadi M. Barakat , Xiaoling Xu , Toan Duc Pham , Warren Fritz Kruger
发明人： Aaron John Nygren , Ming-Ju Edward Lee , Shadi M. Barakat , Xiaoling Xu , Toan Duc Pham , Warren Fritz Kruger
IPC分类号： G06F1/04
CPC分类号： G11C7/1078 , G11C7/1093 , G11C7/222 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/50012 , G11C2207/2254
摘要： A method, system, and computer program product are provided for adjusting write timing in a memory device based on a training signal. For instance, the method can include configuring the memory device in a training mode of operation. The method can also include determining a write timing window between a signal on a data bus and a write clock signal based on the training signal. Further, the method includes adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.
摘要翻译：提供了一种方法，系统和计算机程序产品，用于基于训练信号调整存储器设备中的写时序。例如，该方法可以包括在训练操作模式下配置存储器设备。该方法还可以包括基于训练信号来确定数据总线上的信号和写入时钟信号之间的写时序窗口。此外，该方法包括基于写时序窗口来调整数据总线上的信号与写入时钟信号之间的相位差。存储器件可以基于调整后的相位差来恢复数据总线上的数据。

3. 发明授权

US08245073B2 Method and apparatus synchronizing integrated circuit clocks 有权
标题翻译：方法和装置同步集成电路时钟
公开(公告)号：US08245073B2
公开(公告)日：2012-08-14
申请号：US12509409
申请日：2009-07-24
申请人： Aaron Nygren , Ming-Ju Edward Lee , Shadi Barakat , Xiaoling Xu , Toan Duc Pham , Warren Fritz Kruger , Michael Litt
发明人： Aaron Nygren , Ming-Ju Edward Lee , Shadi Barakat , Xiaoling Xu , Toan Duc Pham , Warren Fritz Kruger , Michael Litt
IPC分类号： G06F1/12
CPC分类号： G11C7/1045
摘要： Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.
摘要翻译：本文描述的实施例包括用于在计算机系统中的耦合集成电路（IC）之间同步时钟的方法和系统。根据实施例，在第一IC上提供专用定时引脚。第一IC配置第二IC以改变引脚分配，使得第二IC解释由第一IC在定时引脚上发送的信号，并且在重新分配的引脚上接收作为发送返回信号的请求的信号。在定时引脚上接收到返回信号。返回信号用于确定是否应由第一个IC调整定时。在一个实施例中，时钟和数据恢复（CDR）电路将发送的信号与所接收的信号进行比较，以进行确定。在一个实施例中，第一IC是基于处理器的设备，第二IC是由第一设备控制的存储设备。

4. 发明授权

US08161209B2 Peer-to-peer special purpose processor architecture and method 有权
标题翻译：对等专用处理器的架构和方法
公开(公告)号：US08161209B2
公开(公告)日：2012-04-17
申请号：US12184197
申请日：2008-07-31
申请人： Stephen Morein , Mark S. Grossman , Warren Fritz Kruger , Brian Etscheid
发明人： Stephen Morein , Mark S. Grossman , Warren Fritz Kruger , Brian Etscheid
IPC分类号： G06F3/00
CPC分类号： G06F13/4265 , G06F13/4004 , G06F2213/0026
摘要： A peer-to-peer special purpose processor architecture and method is described. Embodiments include a plurality of special purpose processors coupled to a central processing unit via a host bridge bus, a direct bus directly coupling each of the plurality of special purpose processors to at least one other of the plurality of special purpose processors and a memory controller coupled to the plurality of special purpose processors, wherein the at least one memory controller determines whether to transmit data via the host bus or the direct bus, and whether to receive data via the host bus or the direct bus.
摘要翻译：描述了一种对等专用处理器架构和方法。实施例包括经由主桥总线耦合到中央处理单元的多个专用处理器，将多个专用处理器中的每一个直接耦合到多个专用处理器中的至少一个的直接总线和耦合到存储器控制器的存储器控制器至多个专用处理器，其中至少一个存储器控制器确定是经由主机总线还是直接总线发送数据，以及是否经由主机总线或直接总线接收数据。

5. 发明申请

US20110148923A1 POWER EFFICIENT MEMORY 有权
标题翻译：功率有效的存储器
公开(公告)号：US20110148923A1
公开(公告)日：2011-06-23
申请号：US12642257
申请日：2009-12-18
申请人： Greg SADOWSKI , Warren Fritz KRUGER , John Wakefield BROTHERS, III , David I.J. GLEN , Stephen David PRESANT
发明人： Greg SADOWSKI , Warren Fritz KRUGER , John Wakefield BROTHERS, III , David I.J. GLEN , Stephen David PRESANT
IPC分类号： G09G5/39 , G09G5/00
CPC分类号： G06F1/3275 , G06F1/3225 , Y02D10/14
摘要： A circuit includes a memory circuit. The memory retiling circuit moves image information configured to be distributed among a plurality of memory channels into reconfigured image information configured to be distributed among a subset of the plurality of memory channels.
摘要翻译：电路包括存储器电路。存储器重放电路将配置为在多个存储信道中分配的图像信息移动到被配置为分布在多个存储器通道的子集之间的重新配置的图像信息中。

6. 发明申请

US20090147015A1 Aperture Compression for Multiple Data Streams 有权
标题翻译：多数据流的孔径压缩
公开(公告)号：US20090147015A1
公开(公告)日：2009-06-11
申请号：US11951184
申请日：2007-12-05
申请人： Brian Etscheid , Mark S. Grossman , Warren Fritz Kruger
发明人： Brian Etscheid , Mark S. Grossman , Warren Fritz Kruger
IPC分类号： G06F12/02
CPC分类号： G09G5/363 , G09G5/39 , G09G2360/06 , G09G2360/12
摘要： A hardware-based aperture compression system permits addressing large memory spaces via a limited bus aperture. Streams are assigned dynamic base addresses (BAR) that are maintained in registers on sources and destinations. Requests for addresses lying between BAR and BAR plus the size of the bus aperture are sent with BAR subtracted off by the source and added back by the destination. Requests for addresses outside that range are handled by transmitting a new, adjusted BAR before sending the address request.
摘要翻译：基于硬件的孔径压缩系统允许通过有限的总线孔径寻址大的存储空间。流分配动态基地址（BAR），它们保存在源和目的地的寄存器中。 BAR和BAR之间的地址请求以及总线孔径的大小被发送，BAR被源减去并被目的地添加回来。在发送地址请求之前，通过发送一个新的调整后的BAR来处理超出该范围的地址的请求。

7. 发明授权

US09041720B2 Static image retiling and power management method and circuit 有权
标题翻译：静态图像复位和电源管理方法及电路
公开(公告)号：US09041720B2
公开(公告)日：2015-05-26
申请号：US12642257
申请日：2009-12-18
申请人： Greg Sadowski , Warren Fritz Kruger , John Wakefield Brothers, III , David I.J. Glen , Stephen David Presant
发明人： Greg Sadowski , Warren Fritz Kruger , John Wakefield Brothers, III , David I.J. Glen , Stephen David Presant
IPC分类号： G09G5/39 , G06F1/32
CPC分类号： G06F1/3275 , G06F1/3225 , Y02D10/14
摘要： A circuit includes memory retiling methods which distribute image information among a plurality of memory channels producing reconfigured image information distributed among a subset of the plurality of memory channels allowing memory channels outside of the subset to be placed into a power save mode to reduce power consumption. Additional methods are disclosed for further reductions in power consumption.
摘要翻译：电路包括在多个存储器通道之间分配图像信息的存储器重绘方法，其产生分布在多个存储器通道的子集之间的重新配置的图像信息，允许该子集外部的存储器通道进入省电模式以降低功耗。公开了用于进一步降低功耗的附加方法。

8. 发明授权

US08730758B2 Adjustment of write timing in a memory device 有权
标题翻译：调整存储设备中的写入时序
公开(公告)号：US08730758B2
公开(公告)日：2014-05-20
申请号：US12490454
申请日：2009-06-24
申请人： Ming-Ju Edward Lee , Shadi M. Barakat , Warren Fritz Kruger , Xiaoling Xu , Toan Duc Pham , Aaron John Nygren
发明人： Ming-Ju Edward Lee , Shadi M. Barakat , Warren Fritz Kruger , Xiaoling Xu , Toan Duc Pham , Aaron John Nygren
IPC分类号： G11C8/18 , G11C7/22 , G11C11/4076
CPC分类号： G11C7/22 , G06F13/1689 , G06F13/4234 , G11C7/222 , G11C11/4076
摘要： A method and system are provided for adjusting a write timing in a memory device. For instance, the method can include receiving a data signal, a write clock signal, and a reference signal. The method can also include detecting a phase shift in the reference signal over time. The phase shift of the reference signal can be used to adjust a phase difference between the data signal and the write clock signal, where the memory device recovers data from the data signal based on an adjusted write timing of the data signal and the write clock signal.
摘要翻译：提供了一种用于调整存储器件中的写时序的方法和系统。例如，该方法可以包括接收数据信号，写时钟信号和参考信号。该方法还可以包括随时间检测参考信号中的相移。参考信号的相移可用于调整数据信号和写入时钟信号之间的相位差，其中存储器件基于数据信号和写入时钟信号的调整的写入定时从数据信号中恢复数据。

9. 发明授权

US08726139B2 Unified data masking, data poisoning, and data bus inversion signaling 有权
标题翻译：统一数据屏蔽，数据中毒和数据总线反向信令
公开(公告)号：US08726139B2
公开(公告)日：2014-05-13
申请号：US13325648
申请日：2011-12-14
申请人： James O'Connor , Aaron Nygren , Anwar Kashem , Warren Fritz Kruger , Bryan Black
发明人： James O'Connor , Aaron Nygren , Anwar Kashem , Warren Fritz Kruger , Bryan Black
IPC分类号： G06F11/00 , H03M13/00 , G11C29/00 , G06F5/00 , G06F13/00 , G06F13/42 , H03K19/20 , H03K19/00
CPC分类号： G06F13/4239 , Y02D10/14 , Y02D10/151
摘要： Provided herein is a method and system for providing and analyzing unified data signaling that includes setting, or analyzing a state of a single indicator signal, generating or analyzing a data pattern of a plurality of data bits, and signal, or determine, based on the state of the single indicator signal and the pattern of the plurality of data bits, that data bus inversion has been applied to the plurality of data bits or that the plurality of data bits is poisoned.
摘要翻译：本文提供了一种用于提供和分析统一数据信令的方法和系统，其包括设置或分析单个指示符信号的状态，生成或分析多个数据位的数据模式，以及基于单个指示符信号的状态和多个数据位的模式，数据总线反转已被应用于多个数据位或多个数据位被中毒。

10. 发明授权

US08489912B2 Command protocol for adjustment of write timing delay 有权
标题翻译：用于调整写时序延迟的命令协议
公开(公告)号：US08489912B2
公开(公告)日：2013-07-16
申请号：US12846972
申请日：2010-07-30
申请人： Aaron John Nygren , Ming-Ju Edward Lee , Shadi M. Barakat , Xiaoling Xu , Toan Duc Pham , Warren Fritz Kruger , Michael John Litt
发明人： Aaron John Nygren , Ming-Ju Edward Lee , Shadi M. Barakat , Xiaoling Xu , Toan Duc Pham , Warren Fritz Kruger , Michael John Litt
IPC分类号： G06F1/04
CPC分类号： G06F1/14 , G06F1/08 , G06F13/1689
摘要： A method, system, and computer program product are provided for adjusting write timing in a memory device based on a command protocol. For instance, the method can include enabling a write clock data recovery (WCDR) mode of operation. The method can also include transmitting WCDR data from a processing unit to the memory device during the WCDR mode of operation and another mode of operation of the memory device. Based on a phase shift in the WCDR data, a phase difference between a signal on a data bus and a write clock signal can be adjusted. Further, the method can include transmitting the signal on the data bus based on the adjusted phase difference between the signal on the data bus and the write clock signal.
摘要翻译：提供了一种方法，系统和计算机程序产品，用于基于命令协议来调整存储器设备中的写入定时。例如，该方法可以包括启用写时钟数据恢复（WCDR）操作模式。该方法还可以包括在WCDR操作模式和存储器件的另一操作模式期间将WCDR数据从处理单元发送到存储器件。基于WCDR数据中的相移，可以调整数据总线上的信号与写入时钟信号之间的相位差。此外，该方法可以包括基于数据总线上的信号与写入时钟信号之间调整的相位差在数据总线上传送信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式