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1. 发明申请

US20090256243A1 LOW K INTERCONNECT DIELECTRIC USING SURFACE TRANSFORMATION 审中-公开
标题翻译：低K互连电介质使用表面变换
公开(公告)号：US20090256243A1
公开(公告)日：2009-10-15
申请号：US12475896
申请日：2009-06-01
申请人： Joseph E. Geusic , Paul A. Farrar , Arup Bhattacharyya
发明人： Joseph E. Geusic , Paul A. Farrar , Arup Bhattacharyya
IPC分类号： H01L23/00 , H01B17/36
CPC分类号： H01L21/0212 , H01L21/02145 , H01L21/02161 , H01L21/02203 , H01L21/02266 , H01L21/02354 , H01L21/31058 , H01L21/31138 , H01L21/3122 , H01L21/31695 , H01L21/7682 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit insulator structure. One embodiment includes a solid structure of an insulator material, and a precisely determined arrangement of at least one void formed within the solid structure which lowers an effective dielectric constant of the insulator structure. One aspect is a method of forming a low-k insulator structure. In one embodiment, an insulator material is deposited, and a predetermined arrangement of at least one hole is formed in a surface of the insulator material. The insulator material is annealed such that the low-k dielectric material undergoes a surface transformation to transform the arrangement of at least one hole into predetermined arrangement of at least one empty space below the surface of the insulator material. Other aspects are provided herein.
摘要翻译：提供系统，器件和方法，以通过提供低k绝缘体来提高集成电路的性能。一个方面是集成电路绝缘体结构。一个实施例包括绝缘体材料的固体结构，以及形成在固体结构内的至少一个空隙的精确确定的布置，其降低绝缘体结构的有效介电常数。一个方面是形成低k绝缘体结构的方法。在一个实施例中，沉积绝缘体材料，并且在绝缘体材料的表面中形成至少一个孔的预定布置。绝缘体材料被退火，使得低k电介质材料进行表面变换，以将至少一个孔的布置转换成绝缘体材料表面下方的至少一个空白空间的预定布置。本文提供了其他方面。

2. 发明授权

US07485497B2 Integrated circuit cooling and insulating device and method 失效
公开(公告)号：US07485497B2
公开(公告)日：2009-02-03
申请号：US11977524
申请日：2007-10-25
申请人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
发明人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
IPC分类号： H01L21/00
CPC分类号： H01L23/427 , G01R31/2817 , H01L2924/0002 , H01L2924/00
摘要： A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a method of controlling chip temperature. This allows circuit and device designers an opportunity to design more efficient structures. Some properties that exhibit less variation when temperature ranges are controlled include electromigration, conductivity, operating speed, and reliability.

3. 发明授权

US07304380B2 Integrated circuit cooling and insulating device and method 有权
标题翻译：集成电路冷却和绝缘装置及方法
公开(公告)号：US07304380B2
公开(公告)日：2007-12-04
申请号：US11482308
申请日：2006-07-07
申请人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
发明人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
IPC分类号： H01L23/34
CPC分类号： H01L23/427 , G01R31/2817 , H01L2924/0002 , H01L2924/00
摘要： A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a method of controlling chip temperature. This allows circuit and device designers an opportunity to design more efficient structures. Some properties that exhibit less variation when temperature ranges are controlled include electromigration, conductivity, operating speed, and reliability.
摘要翻译：提供一种用于冷却集成电路的方法和装置。提供了使用气体来冷却诸如多个空气桥结构之类的电路结构的方法和装置。提供了一种使用沸腾液体来冷却电路结构的方法和装置。还提供了一种控制芯片温度的方法。这允许电路和设备设计者有机会设计更有效的结构。在温度范围被控制时表现出较小变化的一些性质包括电迁移，电导率，操作速度和可靠性。

4. 发明授权

US07132348B2 Low k interconnect dielectric using surface transformation 有权
公开(公告)号：US07132348B2
公开(公告)日：2006-11-07
申请号：US10106915
申请日：2002-03-25
申请人： Joseph E. Geusic , Paul A. Farrar , Arup Bhattacharyya
发明人： Joseph E. Geusic , Paul A. Farrar , Arup Bhattacharyya
IPC分类号： H01L21/4763
CPC分类号： H01L21/0212 , H01L21/02145 , H01L21/02161 , H01L21/02203 , H01L21/02266 , H01L21/02354 , H01L21/31058 , H01L21/31138 , H01L21/3122 , H01L21/31695 , H01L21/7682 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit insulator structure. One embodiment includes a solid structure of an insulator material, and a precisely determined arrangement of at least one void formed within the solid structure which lowers an effective dielectric constant of the insulator structure. One aspect is a method of forming a low-k insulator structure. In one embodiment, an insulator material is deposited, and a predetermined arrangement of at least one hole is formed in a surface of the insulator material. The insulator material is annealed such that the low-k dielectric material undergoes a surface transformation to transform the arrangement of at least one hole into predetermined arrangement of at least one empty space below the surface of the insulator material. Other aspects are provided herein.

5. 发明授权

US07300821B2 Integrated circuit cooling and insulating device and method 有权
公开(公告)号：US07300821B2
公开(公告)日：2007-11-27
申请号：US10930252
申请日：2004-08-31
申请人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
发明人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
IPC分类号： H01L21/00
CPC分类号： H01L23/427 , G01R31/2817 , H01L2924/0002 , H01L2924/00
摘要： A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a method of controlling chip temperature. This allows circuit and device designers an opportunity to design more efficient structures. Some properties that exhibit less variation when temperature ranges are controlled include electromigration, conductivity, operating speed, and reliability.

6. 发明授权

US07492042B2 Integrated circuit cooling and insulating device and method 失效
标题翻译：集成电路冷却和绝缘装置及方法
公开(公告)号：US07492042B2
公开(公告)日：2009-02-17
申请号：US11977515
申请日：2007-10-25
申请人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
发明人： Paul A. Farrar , Leonard Forbes , Kie Y. Ahn , Joseph E. Geusic , Arup Bhattacharyya , Alan R. Reinberg
IPC分类号： H01L23/34
CPC分类号： H01L23/427 , G01R31/2817 , H01L2924/0002 , H01L2924/00
摘要： A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a method of controlling chip temperature. This allows circuit and device designers an opportunity to design more efficient structures. Some properties that exhibit less variation when temperature ranges are controlled include electromigration, conductivity, operating speed, and reliability.
摘要翻译：提供一种用于冷却集成电路的方法和装置。提供了使用气体来冷却诸如多个空气桥结构之类的电路结构的方法和装置。提供了一种使用沸腾液体来冷却电路结构的方法和装置。还提供了一种控制芯片温度的方法。这允许电路和设备设计者有机会设计更有效的结构。在温度范围被控制时表现出较小变化的一些性质包括电迁移，电导率，操作速度和可靠性。

7. 发明授权

US07550824B2 Low k interconnect dielectric using surface transformation 有权
标题翻译：低k互连电介质使用表面变换
公开(公告)号：US07550824B2
公开(公告)日：2009-06-23
申请号：US10931593
申请日：2004-08-31
申请人： Joseph E. Geusic , Paul A. Farrar , Arup Bhattacharyya
发明人： Joseph E. Geusic , Paul A. Farrar , Arup Bhattacharyya
IPC分类号： H01L23/58
CPC分类号： H01L21/0212 , H01L21/02145 , H01L21/02161 , H01L21/02203 , H01L21/02266 , H01L21/02354 , H01L21/31058 , H01L21/31138 , H01L21/3122 , H01L21/31695 , H01L21/7682 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit insulator structure. One embodiment includes a solid structure of an insulator material, and a precisely determined arrangement of at least one void formed within the solid structure which lowers an effective dielectric constant of the insulator structure. One aspect is a method of forming a low-k insulator structure. In one embodiment, an insulator material is deposited, and a predetermined arrangement of at least one hole is formed in a surface of the insulator material. The insulator material is annealed such that the low-k dielectric material undergoes a surface transformation to transform the arrangement of at least one hole into predetermined arrangement of at least one empty space below the surface of the insulator material. Other aspects are provided herein.
摘要翻译：提供系统，器件和方法，以通过提供低k绝缘体来提高集成电路的性能。一个方面是集成电路绝缘体结构。一个实施例包括绝缘体材料的固体结构，以及形成在固体结构内的至少一个空隙的精确确定的布置，其降低绝缘体结构的有效介电常数。一个方面是形成低k绝缘体结构的方法。在一个实施例中，沉积绝缘体材料，并且在绝缘体材料的表面中形成至少一个孔的预定布置。绝缘体材料被退火，使得低k电介质材料进行表面变换，以将至少一个孔的布置转换成绝缘材料表面下方的至少一个空白空间的预定布置。本文提供了其他方面。

8. 发明授权

US06979880B2 Scalable high performance antifuse structure and process 有权
公开(公告)号：US06979880B2
公开(公告)日：2005-12-27
申请号：US10931601
申请日：2004-08-31
申请人： Arup Bhattacharyya , Joseph E. Geusic
发明人： Arup Bhattacharyya , Joseph E. Geusic
IPC分类号： H01L23/525 , H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： Systems and methods are provided for a scalable high-performance antifuse structure and process that has a low RC component, a uniform dielectric breakdown, and a very low, effective dielectric constant (keff) such that a programming pulse voltage is scalable with Vdd. One aspect of the present subject matter is an antifuse device that is positioned or coupled between a first metal level and a second metal level. One embodiment of the antifuse device includes a porous antifuse dielectric layer, and at least one injector Silicon-Rich-Insulator (SRI) layer in contact with the porous antifuse dielectric layer. In one embodiment, the porous antifuse dielectric layer includes SiO2 formed with air-filled voids. In one embodiment, the at least one injector SRI layer includes two injector Silicon-Rich-Nitride layers that sandwich the porous antifuse dielectric layer. Other aspects are provided herein.

9. 发明授权

US06943065B2 Scalable high performance antifuse structure and process 有权
标题翻译：可扩展的高性能反熔丝结构和工艺
公开(公告)号：US06943065B2
公开(公告)日：2005-09-13
申请号：US10106916
申请日：2002-03-25
申请人： Arup Bhattacharyya , Joseph E. Geusic
发明人： Arup Bhattacharyya , Joseph E. Geusic
IPC分类号： H01L23/525 , H01L29/00
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： Systems and methods are provided for a scalable high-performance antifuse structure and process that has a low RC component, a uniform dielectric breakdown, and a very low, effective dielectric constant (keff) such that a programming pulse voltage is scalable with Vdd. One aspect of the present subject matter is an antifuse device that is positioned or coupled between a first metal level and a second metal level. One embodiment of the antifuse device includes a porous antifuse dielectric layer, and at least one injector Silicon-Rich-Insulator (SRI) layer in contact with the porous antifuse dielectric layer. In one embodiment, the porous antifuse dielectric layer includes SiO2 formed with air-filled voids. In one embodiment, the at least one injector SRI layer includes two injector Silicon-Rich-Nitride layers that sandwich the porous antifuse dielectric layer. Other aspects are provided herein.
摘要翻译：为可扩展的高性能反熔丝结构和工艺提供了系统和方法，该结构和工艺具有低RC分量，均匀的介电击穿和非常低的有效介电常数（k eff eff），使得编程脉冲电压可通过Vdd进行扩展。本主题的一个方面是反熔丝装置，其被定位或耦合在第一金属层和第二金属层之间。反熔丝装置的一个实施例包括多孔反熔丝电介质层和与多孔反熔丝电介质层接触的至少一个注入硅富集绝缘体（SRI）层。在一个实施例中，多孔反熔丝电介质层包括由空气填充的空隙形成的SiO 2。在一个实施例中，至少一个喷射器SRI层包括夹着多孔反熔丝电介质层的两个注入器富硅氮化物层。本文提供了其他方面。

10. 发明授权

US06949839B2 Aligned buried structures formed by surface transformation of empty spaces in solid state materials 失效
标题翻译：通过固体材料中的空白空间的表面变换形成的对齐掩埋结构
公开(公告)号：US06949839B2
公开(公告)日：2005-09-27
申请号：US10277043
申请日：2002-10-22
申请人： Paul A. Farrar , Joseph E. Geusic
发明人： Paul A. Farrar , Joseph E. Geusic
IPC分类号： G03F9/00 , H01L21/764 , H01L23/544 , H01L23/48
CPC分类号： H01L21/3247 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L21/764 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , Y10S257/92 , Y10S438/975 , H01L2924/00
摘要： A method of aligning a plurality of empty-spaced buried patterns formed in semiconductor monocrystalline substrates is disclosed. In an exemplary embodiment, high-temperature metal marks are formed to include a conductive material having a melting temperature higher than an annealing temperature used to form such empty-spaced buried patterns. The high-temperature metal marks are formed prior to the formation of the empty-spaced buried patterns formed in a monocrystalline substrate, so that the empty-space buried patterns are aligned to the marks. Subsequent semiconductor structures that are formed as part of desired semiconductor devices can be also aligned to the marks.
摘要翻译：公开了一种对准在半导体单晶衬底中形成的多个空间间隔的掩模图案的方法。在示例性实施例中，形成高温金属标记以包括具有高于用于形成这样的空间间隔掩埋图案的退火温度的熔化温度的导电材料。在形成在单晶衬底中形成的空间间隔的掩模图形之前形成高温金属标记，使得空间掩埋图案与标记对准。形成为期望的半导体器件的一部分的后续半导体结构也可以与标记对准。

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