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1. 发明授权

US06958269B2 Memory device with reduced cell size 有权
标题翻译：具有减小的单元大小的存储器件
公开(公告)号：US06958269B2
公开(公告)日：2005-10-25
申请号：US10178100
申请日：2002-06-24
申请人： Josef Czeslaw Mitros , Imran Khan , Lily Springer
发明人： Josef Czeslaw Mitros , Imran Khan , Lily Springer
IPC分类号： H01L21/28 , H01L29/423 , H01L21/236 , H01L29/745
CPC分类号： H01L29/42324 , H01L21/28273
摘要： A method for manufacturing a memory device includes forming an oxide layer adjacent a substrate. A floating gate layer is formed and disposed outwardly from the oxide layer. A dielectric layer is formed, such that it is disposed outwardly from the floating gate layer. Then, a conductive material layer is formed and disposed outwardly from the dielectric layer, wherein the conductive material layer forms a control gate that is substantially isolated from the floating gate layer by the dielectric layer.
摘要翻译：一种用于制造存储器件的方法包括在衬底附近形成氧化物层。形成浮栅，并从氧化物层向外设置。形成介电层，使得其从浮栅层向外设置。然后，形成导电材料层并从电介质层向外设置导电材料层，其中导电材料层形成通过介电层基本上与浮动栅极隔离的控制栅极。

2. 发明申请

US20200334253A1 SEMANTIC SEARCH METHOD FOR A DISTRIBUTED DATA SYSTEM WITH NUMERICAL TIME SERIES DATA 审中-公开
公开(公告)号：US20200334253A1
公开(公告)日：2020-10-22
申请号：US16765508
申请日：2018-11-20
申请人： Charbel Joseph El Kaed , Imran Khan , Hicham Hossayni
发明人： Charbel Joseph El Kaed , Imran Khan , Hicham Hossayni
IPC分类号： G06F16/2452 , G06F16/36 , G06F16/2458 , G06F17/18
摘要： Methods and systems are provided for searching time series information in a distributed data processing system. A method of processing a semantic search query comprises receiving a structured search query, processing the structured search query to deconstruct into query elements, identifying a set of connected elements based on the query elements, processing a time series data structure of the identified set of connected elements to determine a command data element, utilizing the command data element to process the time series data structure of the identified set of connected elements, annotating the time series data structure of each of the identified set of connected elements to form a queried data set, and providing the queried data set.

3. 发明授权

US08536011B2 Junction leakage suppression in memory devices 有权
标题翻译：存储器件中的结漏电抑制
公开(公告)号：US08536011B2
公开(公告)日：2013-09-17
申请号：US13074836
申请日：2011-03-29
申请人： Shibly S. Ahmed , Jun Kang , Hsiao-Han Thio , Imran Khan , Dong-Hyuk Ju , Chuan Lin
发明人： Shibly S. Ahmed , Jun Kang , Hsiao-Han Thio , Imran Khan , Dong-Hyuk Ju , Chuan Lin
IPC分类号： H01L21/336 , H01L21/44 , H01L29/788
CPC分类号： H01L29/66833 , H01L27/11521 , H01L27/11568 , H01L29/7885 , H01L29/792
摘要： A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.
摘要翻译：存储器件包括衬底和形成在衬底中的源区和漏区。源极和漏极区域包括磷和砷，并且磷可以在砷之前被植入。存储器件还包括形成在衬底上的第一电介质层和形成在第一介电层上的电荷存储元件。存储器件还可以包括形成在电荷存储元件上的第二电介质层和形成在第二介电层上的控制栅极。

4. 发明授权

US09054632B2 In-process electrical connector 有权
标题翻译：在线电连接器
公开(公告)号：US09054632B2
公开(公告)日：2015-06-09
申请号：US13198256
申请日：2011-08-04
申请人： James Hinkle , Imran Khan , Modesto Sanchez , Thomas Truman
发明人： James Hinkle , Imran Khan , Modesto Sanchez , Thomas Truman
IPC分类号： G01R31/26 , H02S50/10 , G01R1/073
CPC分类号： H02S50/10 , G01R1/07342
摘要： Characteristics of partially assembled photovoltaic modules can be determined using electrical connection apparatuses and methods. By providing deformable electrical contacts against a partially assembled module on an assembly line, an electrical bias can be applied to the module before the module is completely assembled. An electrical connection apparatus for a photovoltaic module may include a first contact configured to engage a first lead on the photovoltaic module, a second contact configured to engage a second lead on the photovoltaic module, and an electrical power source configured to apply an electrical bias between the first contact and the second contact.
摘要翻译：可以使用电连接装置和方法来确定部分组装的光伏模块的特性。通过向装配线上的部分组装的模块提供可变形的电触点，在模块完全组装之前，可以将电偏压施加到模块。用于光伏模块的电连接装置可以包括被配置为接合光伏模块上的第一引线的第一触点，被配置为接合光伏模块上的第二引线的第二触点和被配置为在光伏模块之间施加电偏压的电源第一次接触和第二次接触。

5. 发明申请

US20120230235A1 GENERIC PACKET FILTERING 有权
标题翻译：一般分组过滤
公开(公告)号：US20120230235A1
公开(公告)日：2012-09-13
申请号：US13411146
申请日：2012-03-02
申请人： Michelle Perras , Juan Carlos Zuniga , Alexander Reznik , Reeteshkumar Varshney , Imran Khan
发明人： Michelle Perras , Juan Carlos Zuniga , Alexander Reznik , Reeteshkumar Varshney , Imran Khan
IPC分类号： H04W4/00
CPC分类号： H04L69/22 , H04L69/14 , H04W28/06
摘要： Embodiments contemplate one or more techniques for packet filtering. One or more embodiments may apply specific routing and/or forwarding rules on some or each packet when a device has one or more, or multiple, interfaces. Contemplated filtering techniques may be implemented in a module and/or without modifying an IP stack. The contemplated packet filtering techniques may apply to a terminal in uplink and/or downlink as well as to any network node. An incoming packet table may be created using 5-tuple, 6-tuple, and/or tags, among other mechanisms, to support incoming and/or outgoing packet filtering.
摘要翻译：实施例考虑了一种或多种用于分组过滤的技术。一个或多个实施例可以在设备具有一个或多个或多个接口时在一些或每个分组上应用特定路由和/或转发规则。考虑过滤技术可以在模块中实现和/或不修改IP堆栈。预期的分组过滤技术可以应用于上行链路和/或下行链路中的终端以及任何网络节点。可以使用5元组，6元组和/或标签以及其他机制来创建输入分组表，以支持传入和/或传出分组过滤。

6. 发明申请

US20120098045A1 Zero Temperature Coefficient Capacitor 有权
标题翻译：零温度系数电容器
公开(公告)号：US20120098045A1
公开(公告)日：2012-04-26
申请号：US13267674
申请日：2011-10-06
申请人： Weidong Tian , Imran Khan
发明人： Weidong Tian , Imran Khan
IPC分类号： H01L29/772 , H01L21/336 , H01L29/92
CPC分类号： H01L28/40 , H01L27/0629 , H01L29/94
摘要： A zero temperature coefficient (ZTC) capacitor including a silicon dioxide dielectric layer with a phosphorus density between 1.7×1020 atoms/cm3 and 2.3×1020 atoms/cm3. An integrated circuit containing a ZTC capacitor including a silicon dioxide dielectric layer with a phosphorus density between 1.7×1020 atoms/cm3 and 2.3×1020 atoms/cm3. A process of forming an integrated circuit containing a ZTC capacitor including a silicon dioxide dielectric layer with a phosphorus density between 1.7×1020 atoms/cm3 and 2.3×1020 atoms/cm3.
摘要翻译：零温度系数（ZTC）电容器，其包括磷密度在1.7×1020原子/ cm3至2.3×1020原子/ cm3之间的二氧化硅介电层。一种包含ZTC电容器的集成电路，其包括磷密度为1.7×1020原子/ cm3至2.3×1020原子/ cm3的二氧化硅电介质层。形成包含Zinc电容器的集成电路的过程，该电容器包括磷密度为1.7×1020原子/ cm3至2.3×1020原子/ cm3的二氧化硅介电层。

7. 发明申请

US20110237021A1 PHOTOVOLTAIC MODULE MANUFACTURE 有权
标题翻译：光伏模块制造
公开(公告)号：US20110237021A1
公开(公告)日：2011-09-29
申请号：US13035594
申请日：2011-02-25
申请人： Markus Gloeckler , Imran Khan
发明人： Markus Gloeckler , Imran Khan
IPC分类号： H01L31/18
CPC分类号： H01L31/186 , H01L31/03767 , H01L31/048 , Y02E10/50 , Y02P70/521 , Y10T29/5313 , Y10T29/5317
摘要： A method for manufacturing a photovoltaic module including a laminating step.
摘要翻译：一种制造包括层压步骤的光伏组件的方法。

8. 发明申请

US20110139240A1 PHOTOVOLTAIC WINDOW LAYER 审中-公开
标题翻译：光伏窗户层
公开(公告)号：US20110139240A1
公开(公告)日：2011-06-16
申请号：US12969075
申请日：2010-12-15
申请人： Arnold Allenic , Benyamin Buller , Markus Gloeckler , Imran Khan , Viral Parikh , Rick C. Powell , Igor Sankin , Gang Xiong
发明人： Arnold Allenic , Benyamin Buller , Markus Gloeckler , Imran Khan , Viral Parikh , Rick C. Powell , Igor Sankin , Gang Xiong
IPC分类号： H01L31/0216 , H01L31/0224
CPC分类号： H01L31/03529 , H01L31/0296 , H01L31/065 , H01L31/072 , H01L31/073 , H01L31/074 , Y02E10/543 , Y02P70/521
摘要： A discontinuous or reduced thickness window layer can improve the efficiency of CdTe-based or other kinds of solar cells.
摘要翻译：不连续或减薄的窗口层可以提高CdTe或其他类型的太阳能电池的效率。

9. 发明申请

US20080268630A1 METHOD TO OBTAIN MULTIPLE GATE THICKNESSES USING IN-SITU GATE ETCH MASK APPROACH 有权
标题翻译：使用现场浇口掩模方法获取多个浇口厚度的方法
公开(公告)号：US20080268630A1
公开(公告)日：2008-10-30
申请号：US11741998
申请日：2007-04-30
申请人： Imran Khan , Ahmed Shibly , Dong-Hyuk Ju
发明人： Imran Khan , Ahmed Shibly , Dong-Hyuk Ju
IPC分类号： H01L21/3205
CPC分类号： H01L21/31144 , H01L21/823456 , H01L21/823462 , H01L21/82385 , H01L21/823857
摘要： Making gates having multiple thicknesses on the same substrate in a given process flow is provided. For example, a method of making a semiconductor structure having at least two gates of different thickness involves forming a first gate layer having a first thickness; patterning a first hard mask over a portion of the first gate layer to define a first gate underneath the first hard mask having a first gate thickness; forming a second gate layer having a second thickness over the first gate layer and the first hard mask; patterning a second hard mask over a portion of the second gate layer to define a second gate underneath the second hard mask having a second gate thickness; removing portions of the first gate layer and the second gate layer that are not under the first hard mask and the second hard mask; and removing the first hard mask and the second hard mask to provide two gates of different thicknesses.
摘要翻译：提供了在给定的工艺流程中在同一基板上制造具有多个厚度的浇口。例如，制造具有不同厚度的至少两个栅极的半导体结构的方法包括形成具有第一厚度的第一栅极层; 在第一栅极层的一部分上图案化第一硬掩模以限定具有第一栅极厚度的第一硬掩模下面的第一栅极; 在所述第一栅极层和所述第一硬掩模上形成具有第二厚度的第二栅极层; 在第二栅极层的一部分上图案化第二硬掩模以限定具有第二栅极厚度的第二硬掩模下方的第二栅极; 去除不在第一硬掩模下面的第一栅极层和第二栅极层的部分和第二硬掩模; 以及去除第一硬掩模和第二硬掩模以提供不同厚度的两个栅极。

10. 发明授权

US07268394B2 JFET structure for integrated circuit and fabrication method 有权
标题翻译：集成电路和制造方法的JFET结构
公开(公告)号：US07268394B2
公开(公告)日：2007-09-11
申请号：US11038562
申请日：2005-01-18
申请人： Pinghai Hao , Fan-Chi Hou , Imran Khan
发明人： Pinghai Hao , Fan-Chi Hou , Imran Khan
IPC分类号： H01L29/76
CPC分类号： H01L27/085 , G11C2211/4068 , H01L21/8232 , H01L29/0692 , H01L29/1066 , H01L29/66901 , H01L29/808
摘要： Junction field effect transistors (JFETs) can be fabricated with an epitaxial layer that forms a sufficiently thick channel region to enable the JFET for use in high voltage applications (e.g., having a breakdown voltage greater than about 20V). Additionally or alternatively, threshold voltage (VT) implants can be introduced at one or more of the gate, source and drain regions to improve noise performance of the JFET. Additionally, fabrication of such a JFET can be facilitated forming the entire JFET structure concurrently with a CMOS fabrication process and/or with a BiCMOS fabrication process.
摘要翻译：结型场效应晶体管（JFET）可以用形成足够厚的沟道区的外延层来制造，以使得JFET可用于高电压应用（例如具有大于约20V的击穿电压）。另外或替代地，可以在栅极，源极和漏极区域中的一个或多个处引入阈值电压（VT）注入，以改善JFET的噪声性能。另外，这样的JFET的制造可以促进与CMOS制造工艺和/或BiCMOS制造工艺同时形成整个JFET结构。

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