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1. 发明授权

US07835199B2 Nonvolatile memory using resistance material 有权
标题翻译：使用电阻材料的非易失性存储器
公开(公告)号：US07835199B2
公开(公告)日：2010-11-16
申请号：US12244042
申请日：2008-10-02
申请人： Joon-Yong Choi , Byung-Gil Choi , Du-Eung Kim
发明人： Joon-Yong Choi , Byung-Gil Choi , Du-Eung Kim
IPC分类号： G11C5/14 , G11C8/00
CPC分类号： G11C7/20 , G11C8/08 , G11C13/0004 , G11C13/0028 , G11C13/0038 , G11C13/0061 , G11C2207/2227 , G11C2213/72 , G11C2213/79
摘要： Provided is a nonvolatile memory using a resistance material. In embodiments of the invention, a PRAM is configured to apply a step-down voltage to wordlines during a standby mode. Aspects of the present invention thus provide a nonvolatile memory with reduced standby current. Additionally, embodiments of the invention allow for faster transition from a standby state to an active state.
摘要翻译：提供了使用电阻材料的非易失性存储器。在本发明的实施例中，PRAM被配置为在待机模式期间对字线施加降压电压。因此，本发明的方面提供了具有减少的待机电流的非易失性存储器。另外，本发明的实施例允许从待机状态到活动状态的更快的转换。

2. 发明申请

US20070230239A1 Phase change memory devices and program methods 有权
标题翻译：相变存储器件和程序方法
公开(公告)号：US20070230239A1
公开(公告)日：2007-10-04
申请号：US11723354
申请日：2007-03-19
申请人： Byung-Gil Choi , Du-Eung Kim , Yu-Hwan Ro , Joon-Yong Choi , Beak-Hyung Cho , Woo-Yeong Cho
发明人： Byung-Gil Choi , Du-Eung Kim , Yu-Hwan Ro , Joon-Yong Choi , Beak-Hyung Cho , Woo-Yeong Cho
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0078 , G11C2213/72
摘要： A phase change memory device is disclosed. It includes a memory cell array including a plurality of memory cells programmed in relation to a phase change material, and a write driver circuit configured to provide a set current and a reset current to a selected memory cell. The write driver circuit includes a set current driver configured to provide the set current and a reset current driver configured to provide the reset current.
摘要翻译：公开了一种相变存储器件。其包括存储单元阵列，其包括相对于相变材料编程的多个存储器单元，以及写入驱动器电路，其被配置为向所选存储单元提供置位电流和复位电流。写驱动器电路包括配置成提供设定电流的设定电流驱动器和被配置为提供复位电流的复位电流驱动器。

3. 发明授权

US07499316B2 Phase change memory devices and program methods 有权
标题翻译：相变存储器件和程序方法
公开(公告)号：US07499316B2
公开(公告)日：2009-03-03
申请号：US11723354
申请日：2007-03-19
申请人： Byung-Gil Choi , Du-Eung Kim , Yu-Hwan Ro , Joon-Yong Choi , Beak-Hyung Cho , Woo-Yeong Cho
发明人： Byung-Gil Choi , Du-Eung Kim , Yu-Hwan Ro , Joon-Yong Choi , Beak-Hyung Cho , Woo-Yeong Cho
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0078 , G11C2213/72
摘要： A phase change memory device is disclosed. It includes a memory cell array including a plurality of memory cells programmed in relation to a phase change material, and a write driver circuit configured to provide a set current and a reset current to a selected memory cell. The write driver circuit includes a set current driver configured to provide the set current and a reset current driver configured to provide the reset current.
摘要翻译：公开了一种相变存储器件。其包括存储单元阵列，其包括相对于相变材料编程的多个存储器单元，以及写入驱动器电路，其被配置为向所选存储单元提供置位电流和复位电流。写驱动器电路包括配置成提供设定电流的设定电流驱动器和被配置为提供复位电流的复位电流驱动器。

4. 发明授权

US07830699B2 Resistance variable memory device reducing word line voltage 有权
标题翻译：电阻可变存储器件减少字线电压
公开(公告)号：US07830699B2
公开(公告)日：2010-11-09
申请号：US12245929
申请日：2008-10-06
申请人： Byung-Gil Choi , Du-Eung Kim
发明人： Byung-Gil Choi , Du-Eung Kim
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C2013/0078 , G11C2213/72
摘要： A resistance variable memory device includes a memory cell array, a sense amplifier circuit, and a column selection circuit. The memory cell array includes a plurality of block units and a plurality of word line drivers, where each of the block units is connected between adjacent word line drivers and includes a plurality of memory blocks. The sense amplifier circuit includes a plurality of sense amplifier units, where each of the sense amplifier units provides a read current to a corresponding block unit and includes a plurality of sense amplifiers. The column selection circuit is connected between the memory cell array and the sense amplifier circuit and selects at least one of the plurality of memory blocks in response to a column selection signal to apply the read current from the sense amplifier circuit to the selected memory block.
摘要翻译：电阻可变存储器件包括存储单元阵列，读出放大器电路和列选择电路。存储单元阵列包括多个块单元和多个字线驱动器，其中每个块单元连接在相邻字线驱动器之间并且包括多个存储块。读出放大器电路包括多个读出放大器单元，其中每个读出放大器单元向对应的块单元提供读取电流并且包括多个读出放大器。列选择电路连接在存储单元阵列和读出放大器电路之间，并响应于列选择信号选择多个存储块中的至少一个，以将读出的电流从读出放大器电路施加到所选存储块。

5. 发明授权

US07511993B2 Phase change memory device and related programming method 有权
标题翻译：相变存储器件及相关编程方法
公开(公告)号：US07511993B2
公开(公告)日：2009-03-31
申请号：US11724268
申请日：2007-03-15
申请人： Byung-Gil Choi , Du-Eung Kim , Beak-Hyung Cho , Woo-Yeong Cho
发明人： Byung-Gil Choi , Du-Eung Kim , Beak-Hyung Cho , Woo-Yeong Cho
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0078 , G11C2213/72
摘要： A phase change memory device comprises a memory cell array and a write driver circuit. The memory cell array comprises a plurality of memory cells, and the write driver circuit comprises a set current driver and a reset current driver. The set current driver is adapted to provide a set current to a selected memory cell among the plurality of memory cells and the reset current driver is adapted to provide a reset current to a selected memory cell among the plurality of memory cells.
摘要翻译：相变存储器件包括存储单元阵列和写入驱动器电路。存储单元阵列包括多个存储单元，并且写驱动器电路包括设定电流驱动器和复位电流驱动器。所设置的电流驱动器适于向所述多个存储器单元中的所选择的存储单元提供设定电流，并且所述复位电流驱动器适于向所述多个存储器单元中的所选存储单元提供复位电流。

6. 发明申请

US20070217273A1 PHASE-CHANGE RANDOM ACCESS MEMORY 有权
标题翻译：相变随机存取存储器
公开(公告)号：US20070217273A1
公开(公告)日：2007-09-20
申请号：US11616969
申请日：2006-12-28
申请人： Byung-Gil Choi , Du-Eung Kim , Woo-Yeong Cho , Hye-Jin Kim
发明人： Byung-Gil Choi , Du-Eung Kim , Woo-Yeong Cho , Hye-Jin Kim
IPC分类号： G11C29/00
CPC分类号： G11C29/808 , G11C29/02 , G11C29/027 , G11C29/787 , G11C29/804 , G11C29/846
摘要： A phase-change random access memory includes a memory block including a plurality of memory columns corresponding to the same column address and using different input/output paths; a redundancy memory block including a plurality of redundancy memory columns using different input/output paths; and an input/output controller repairing at least one of the plurality of memory columns using at least one of the plurality of redundancy memory columns, and controlling the number of memory columns simultaneously repaired using redundancy memory columns in response to an input/output repair mode control signal.
摘要翻译：相变随机存取存储器包括存储块，该存储块包括对应于同一列地址的多个存储器列并使用不同的输入/输出路径; 冗余存储器块，其包括使用不同的输入/输出路径的多个冗余存储器列; 以及输入/输出控制器，其使用所述多个冗余存储器列中的至少一个来修复所述多个存储器列中的至少一个，并且响应于输入/输出修复模式来控制使用冗余存储器列同时修复的存储器列的数量控制信号。

7. 发明申请

US20070133271A1 Phase-changeable memory device and read method thereof 有权
标题翻译：相变存储器件及其读取方法
公开(公告)号：US20070133271A1
公开(公告)日：2007-06-14
申请号：US11605212
申请日：2006-11-29
申请人： Woo-Yeong Cho , Byung-Gil Choi , Du-Eung Kim , Hyung-Rok Oh , Beak-Hyung Cho , Yu-Hwan Ro
发明人： Woo-Yeong Cho , Byung-Gil Choi , Du-Eung Kim , Hyung-Rok Oh , Beak-Hyung Cho , Yu-Hwan Ro
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C13/0004 , G11C13/004 , G11C2013/0054 , G11C2213/72
摘要： Disclosed is a phase-changeable memory device and a related method of reading data. The memory device is comprised of memory cells, a high voltage circuit, a precharging circuit, a bias circuit, and a sense amplifier. Each memory cell includes a phase-changeable material and a diode connected to a bitline. The high voltage circuit provides a high voltage from a power source. The precharging circuit raises the bitline up to the high voltage after charging the bitline up to the power source voltage. The bias circuit supplies a read current to the bitline by means of the high voltage. The sense amplifier compares a voltage of the bitline with a reference voltage by means of the high voltage, and reads data from the memory cell. The memory device is able to reduce the burden on the high voltage circuit during the precharging operation, thus assuring a sufficient sensing margin during the sensing operation.
摘要翻译：公开了一种可变相存储器件和读取数据的相关方法。存储器件包括存储器单元，高压电路，预充电电路，偏置电路和读出放大器。每个存储单元包括相位可变材料和连接到位线的二极管。高压电路从电源提供高电压。预充电电路将位线充电至电源电压后，将位线升高至高电压。偏置电路通过高电压向位线提供读取电流。读出放大器通过高电压将位线的电压与参考电压进行比较，并从存储单元读取数据。存储器件能够减少在预充电操作期间对高压电路的负担，从而在感测操作期间确保足够的感测余量。

8. 发明授权

US07110286B2 Phase-change memory device and method of writing a phase-change memory device 有权
公开(公告)号：US07110286B2
公开(公告)日：2006-09-19
申请号：US10919371
申请日：2004-08-17
申请人： Byung-Gil Choi , Choong-Keun Kwak , Du-Eung Kim , Beak-Hyung Cho
发明人： Byung-Gil Choi , Choong-Keun Kwak , Du-Eung Kim , Beak-Hyung Cho
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0023 , G11C13/0069 , G11C2013/0078 , G11C2013/0092 , G11C2213/79
摘要： A phase-change cell memory device includes a plurality of phase-change memory cells, an address circuit, a write driver, and a write driver control circuit. The phase-change memory cells each include a volume of material that is programmable between amorphous and crystalline states. The address circuit selects at least one of the memory cells, and the write driver generates a reset pulse current to program a memory cell selected by the address circuit into the amorphous state, and a set pulse current to program the memory cell selected by the address circuit into the crystalline state. The write driver control circuit varies at least one of a pulse width and a pulse count of at least one of the reset and set pulse currents according to a load between the write driver and the memory cell selected by the address circuit.

9. 发明申请

US20050007843A1 Redundancy circuit in semiconductor memory device having a multiblock structure 有权
标题翻译：具有多块结构的半导体存储器件中的冗余电路
公开(公告)号：US20050007843A1
公开(公告)日：2005-01-13
申请号：US10889194
申请日：2004-07-12
申请人： Byung-Gil Choi , Du-Eung Kim , Choong-Keun Kwak
发明人： Byung-Gil Choi , Du-Eung Kim , Choong-Keun Kwak
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C29/812 , G11C29/806
摘要： A redundancy circuit in a semiconductor memory device having a multiblock structure in which a memory cell array is classified into a plurality of memory cell blocks, an integrated redundancy circuit having a plurality of fuse boxes for storing, per block, addresses of defective memory cells provided in the plurality of memory cell blocks, the plurality of fuse boxes being connected to the common precharge unit and being selectively activated in response to a block distinction selection signal.
摘要翻译：一种具有多块结构的半结构存储器件中的冗余电路，其中存储单元阵列被分为多个存储单元块，集成冗余电路具有多个保险丝盒，用于存储每块所提供的不良存储器单元的地址在所述多个存储单元块中，所述多个保险丝盒连接到所述公共预充电单元，并且响应于块区别选择信号被选择性地激活。

10. 发明授权

US08264905B2 Nonvolatile memory device using variable resistive element 有权
标题翻译：使用可变电阻元件的非易失性存储器件
公开(公告)号：US08264905B2
公开(公告)日：2012-09-11
申请号：US12406441
申请日：2009-03-18
申请人： Byung-Gil Choi , Du-Eung Kim
发明人： Byung-Gil Choi , Du-Eung Kim
IPC分类号： G11C16/08
CPC分类号： G11C8/08 , G11C8/14 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/50008 , G11C2029/1202
摘要： A nonvolatile memory device using variable resistive element with reduced layout size and improved performance is provided. The nonvolatile memory device comprising: a main word line; multiple sub-word lines, wherein each of the sub-word line is connected to multiple nonvolatile memory cells; and a section word line driver which controls voltage level of the multiple sub-word lines, wherein the section word line driver includes multiple pull-down elements which are connected to each of the multiple sub-word lines and a common node and a selection element which is connected to the common node and the main word line.
摘要翻译：提供了使用可变电阻元件的非易失性存储器件，其具有减小的布局尺寸和改进的性能。所述非易失性存储器件包括：主字线; 多个子字线，其中每个子字线连接到多个非易失性存储器单元; 以及区域字线驱动器，其控制所述多个子字线的电压电平，其中所述部分字线驱动器包括连接到所述多个子字线中的每一个的多个下拉元件，以及公共节点和选择元件其连接到公共节点和主字线。

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