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1. 发明申请

US20060170459A1 Multiplexer and methods thereof 审中-公开
标题翻译：多路复用器及其方法
公开(公告)号：US20060170459A1
公开(公告)日：2006-08-03
申请号：US11340458
申请日：2006-01-27
申请人： Jong-Shin Shin , Ji-Young Kim , Myoung-Bo Kwak , Il-Won Seo , Chi-Won Kim , Hyun-Goo Kim , Jae-Hyun Park
发明人： Jong-Shin Shin , Ji-Young Kim , Myoung-Bo Kwak , Il-Won Seo , Chi-Won Kim , Hyun-Goo Kim , Jae-Hyun Park
IPC分类号： H03K19/094
CPC分类号： H03K17/693
摘要： A multiplexer and methods thereof. In an example, the multiplexer may receive a first periodic signal with a first active duration and a second periodic signal with a second active duration, the first and second active durations not overlapping. The multiplexer may transition statuses of first and second transmission gates based on the first and second periodic signals, respectively, such that each of the first and second transmission gates are set to the same status during at least one time period (e.g., between the first and second active durations where both the first and second periodic signals are inactive). In a further example, the example multiplexer may include first and second transmission gates receiving first and second input signals which may be controlled by the first and second control signals.
摘要翻译：多路复用器及其方法。在一个示例中，多路复用器可以接收具有第一有效持续时间的第一周期性信号和具有第二有效持续时间的第二周期信号，第一和第二有效持续时间不重叠。复用器可以分别基于第一和第二周期信号转换第一和第二传输门的状态，使得第一和第二传输门中的每一个在至少一个时间段内（例如，在第一和第二周期信号之间）被设置为相同的状态和第二有效持续时间，其中第一和第二周期信号都不起作用）。在另一示例中，示例多路复用器可以包括接收可由第一和第二控制信号控制的第一和第二输入信号的第一和第二传输门。

2. 发明授权

US07557602B2 Pre-emphasis circuit including slew rate controllable buffer 有权
标题翻译：预加重电路包括压摆率可控缓冲器
公开(公告)号：US07557602B2
公开(公告)日：2009-07-07
申请号：US11506652
申请日：2006-08-18
申请人： Chi-Won Kim , Myoung-Bo Kwak , Jong-Shin Shin
发明人： Chi-Won Kim , Myoung-Bo Kwak , Jong-Shin Shin
IPC分类号： H03K17/16 , H03K19/003 , H03K4/06
CPC分类号： H03K6/04
摘要： A pre-emphasis circuit capable of controlling the slew rate of a signal output from a buffer that transfers the output signal to an output driver to increase the range of a controllable voltage step includes a first buffer, a second buffer, and an output driver. The first buffer buffers first and second main input signals having phases opposite to each other, outputs first and second main output signals, and controls slew rates of the first and second main output signals using at least one main control signal. The second buffer buffers first and second sub-input signals having phases opposite to each other, outputs first and sub-output signals, and controls slew rates of the first and second sub-output signals using at least one sub-control signal. The output driver generates first and second output signals having opposite phases using at least two control signals and the output signals of the first and second buffers.
摘要翻译：一种能够控制从缓冲器输出的信号的转换速率的预加重电路，该缓冲器将输出信号传送到输出驱动器以增加可控电压步长的范围包括第一缓冲器，第二缓冲器和输出驱动器。第一缓冲器缓冲具有彼此相反的相位的第一和第二主输入信号，输出第一和第二主输出信号，并且使用至少一个主控制信号来控制第一和第二主输出信号的转换速率。第二缓冲器缓冲具有彼此相反相位的第一和第二子输入信号，输出第一和副输出信号，并且使用至少一个子控制信号来控制第一和第二子输出信号的转换速率。输出驱动器使用至少两个控制信号和第一和第二缓冲器的输出信号产生具有相反相位的第一和第二输出信号。

3. 发明申请

US20070046350A1 Pre-emphasis circuit including slew rate controllable buffer 有权
标题翻译：预加重电路包括压摆率可控缓冲器
公开(公告)号：US20070046350A1
公开(公告)日：2007-03-01
申请号：US11506652
申请日：2006-08-18
申请人： Chi-Won Kim , Myoung-Bo Kwak , Jong-Shin Shin
发明人： Chi-Won Kim , Myoung-Bo Kwak , Jong-Shin Shin
IPC分类号： H03K5/12
CPC分类号： H03K6/04
摘要： A pre-emphasis circuit capable of controlling the slew rate of a signal output from a buffer that transfers the output signal to an output driver to increase the range of a controllable voltage step includes a first buffer, a second buffer, and an output driver. The first buffer buffers first and second main input signals having phases opposite to each other, outputs first and second main output signals, and controls slew rates of the first and second main output signals using at least one main control signal. The second buffer buffers first and second sub-input signals having phases opposite to each other, outputs first and sub-output signals, and controls slew rates of the first and second sub-output signals using at least one sub-control signal. The output driver generates first and second output signals having opposite phases using at least two control signals and the output signals of the first and second buffers.
摘要翻译：一种能够控制从缓冲器输出的信号的转换速率的预加重电路，该缓冲器将输出信号传送到输出驱动器以增加可控电压步长的范围包括第一缓冲器，第二缓冲器和输出驱动器。第一缓冲器缓冲具有彼此相反的相位的第一和第二主输入信号，输出第一和第二主输出信号，并且使用至少一个主控制信号来控制第一和第二主输出信号的转换速率。第二缓冲器缓冲具有彼此相反相位的第一和第二子输入信号，输出第一和副输出信号，并且使用至少一个子控制信号来控制第一和第二子输出信号的转换速率。输出驱动器使用至少两个控制信号和第一和第二缓冲器的输出信号产生具有相反相位的第一和第二输出信号。

4. 发明授权

US07436904B2 Data recovery apparatus and method for decreasing data recovery error in a high-speed serial link 有权
标题翻译：用于降低高速串行链路中的数据恢复错误的数据恢复装置和方法
公开(公告)号：US07436904B2
公开(公告)日：2008-10-14
申请号：US10782705
申请日：2004-02-19
申请人： Myoung-Bo Kwak
发明人： Myoung-Bo Kwak
IPC分类号： H04B14/04
CPC分类号： H04L7/0337 , H04L25/068
摘要： Provided are a data recovery apparatus and method for recovering (parallel) data from serial data received via a high-speed serial link with a reduced data recovery error rate. The data recovery apparatus includes a clock signal generating circuit and a data recovery circuit. The clock signal generating circuit generates at least two clock signal groups including first and second clock signal groups with different phases for alternate use in the data recovery circuit. The data recovery circuit recovers the data from the serial data by oversampling the serial data using one of the at least two clock signal groups selected based on the number of rising edges of sampling clock signals of the selected clock signal group being within an eye open region of the serial data.
摘要翻译：提供了一种数据恢复装置和方法，用于从具有降低的数据恢复错误率的高速串行链路接收的串行数据中恢复（并行）数据。数据恢复装置包括时钟信号发生电路和数据恢复电路。时钟信号发生电路产生至少两个时钟信号组，包括具有不同相位的第一和第二时钟信号组，用于在数据恢复电路中交替使用。数据恢复电路通过使用基于选择的时钟信号组的采样时钟信号的上升沿的数量所选择的至少两个时钟信号组中的一个来对串行数据进行过采样来恢复来自串行数据的数据，该时钟信号组在眼睛开放区域内的串行数据。

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