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    • 1. 发明申请
    • Multiplexer and methods thereof
    • 多路复用器及其方法
    • US20060170459A1
    • 2006-08-03
    • US11340458
    • 2006-01-27
    • Jong-Shin ShinJi-Young KimMyoung-Bo KwakIl-Won SeoChi-Won KimHyun-Goo KimJae-Hyun Park
    • Jong-Shin ShinJi-Young KimMyoung-Bo KwakIl-Won SeoChi-Won KimHyun-Goo KimJae-Hyun Park
    • H03K19/094
    • H03K17/693
    • A multiplexer and methods thereof. In an example, the multiplexer may receive a first periodic signal with a first active duration and a second periodic signal with a second active duration, the first and second active durations not overlapping. The multiplexer may transition statuses of first and second transmission gates based on the first and second periodic signals, respectively, such that each of the first and second transmission gates are set to the same status during at least one time period (e.g., between the first and second active durations where both the first and second periodic signals are inactive). In a further example, the example multiplexer may include first and second transmission gates receiving first and second input signals which may be controlled by the first and second control signals.
    • 多路复用器及其方法。 在一个示例中,多路复用器可以接收具有第一有效持续时间的第一周期性信号和具有第二有效持续时间的第二周期信号,第一和第二有效持续时间不重叠。 复用器可以分别基于第一和第二周期信号转换第一和第二传输门的状态,使得第一和第二传输门中的每一个在至少一个时间段内(例如,在第一和第二周期信号之间)被设置为相同的状态 和第二有效持续时间,其中第一和第二周期信号都不起作用)。 在另一示例中,示例多路复用器可以包括接收可由第一和第二控制信号控制的第一和第二输入信号的第一和第二传输门。
    • 2. 发明授权
    • Pre-emphasis circuit including slew rate controllable buffer
    • 预加重电路包括压摆率可控缓冲器
    • US07557602B2
    • 2009-07-07
    • US11506652
    • 2006-08-18
    • Chi-Won KimMyoung-Bo KwakJong-Shin Shin
    • Chi-Won KimMyoung-Bo KwakJong-Shin Shin
    • H03K17/16H03K19/003H03K4/06
    • H03K6/04
    • A pre-emphasis circuit capable of controlling the slew rate of a signal output from a buffer that transfers the output signal to an output driver to increase the range of a controllable voltage step includes a first buffer, a second buffer, and an output driver. The first buffer buffers first and second main input signals having phases opposite to each other, outputs first and second main output signals, and controls slew rates of the first and second main output signals using at least one main control signal. The second buffer buffers first and second sub-input signals having phases opposite to each other, outputs first and sub-output signals, and controls slew rates of the first and second sub-output signals using at least one sub-control signal. The output driver generates first and second output signals having opposite phases using at least two control signals and the output signals of the first and second buffers.
    • 一种能够控制从缓冲器输出的信号的转换速率的预加重电路,该缓冲器将输出信号传送到输出驱动器以增加可控电压步长的范围包括第一缓冲器,第二缓冲器和输出驱动器。 第一缓冲器缓冲具有彼此相反的相位的第一和第二主输入信号,输出第一和第二主输出信号,并且使用至少一个主控制信号来控制第一和第二主输出信号的转换速率。 第二缓冲器缓冲具有彼此相反相位的第一和第二子输入信号,输出第一和副输出信号,并且使用至少一个子控制信号来控制第一和第二子输出信号的转换速率。 输出驱动器使用至少两个控制信号和第一和第二缓冲器的输出信号产生具有相反相位的第一和第二输出信号。
    • 3. 发明申请
    • Pre-emphasis circuit including slew rate controllable buffer
    • 预加重电路包括压摆率可控缓冲器
    • US20070046350A1
    • 2007-03-01
    • US11506652
    • 2006-08-18
    • Chi-Won KimMyoung-Bo KwakJong-Shin Shin
    • Chi-Won KimMyoung-Bo KwakJong-Shin Shin
    • H03K5/12
    • H03K6/04
    • A pre-emphasis circuit capable of controlling the slew rate of a signal output from a buffer that transfers the output signal to an output driver to increase the range of a controllable voltage step includes a first buffer, a second buffer, and an output driver. The first buffer buffers first and second main input signals having phases opposite to each other, outputs first and second main output signals, and controls slew rates of the first and second main output signals using at least one main control signal. The second buffer buffers first and second sub-input signals having phases opposite to each other, outputs first and sub-output signals, and controls slew rates of the first and second sub-output signals using at least one sub-control signal. The output driver generates first and second output signals having opposite phases using at least two control signals and the output signals of the first and second buffers.
    • 一种能够控制从缓冲器输出的信号的转换速率的预加重电路,该缓冲器将输出信号传送到输出驱动器以增加可控电压步长的范围包括第一缓冲器,第二缓冲器和输出驱动器。 第一缓冲器缓冲具有彼此相反的相位的第一和第二主输入信号,输出第一和第二主输出信号,并且使用至少一个主控制信号来控制第一和第二主输出信号的转换速率。 第二缓冲器缓冲具有彼此相反相位的第一和第二子输入信号,输出第一和副输出信号,并且使用至少一个子控制信号来控制第一和第二子输出信号的转换速率。 输出驱动器使用至少两个控制信号和第一和第二缓冲器的输出信号产生具有相反相位的第一和第二输出信号。
    • 4. 发明申请
    • HIGH DEFINITION MULTIMEDIA INTERFACE (HDMI) APPARATUS INCLUDING TERMINATION CIRCUIT
    • 高定义多媒体接口(HDMI)设备,包括终端电路
    • US20120262200A1
    • 2012-10-18
    • US13440457
    • 2012-04-05
    • Jong-Shin ShinChi-Won Kim
    • Jong-Shin ShinChi-Won Kim
    • H03K19/003
    • H03K19/017545H03K19/00315
    • A termination circuit for a HDMI transmitter includes a bias unit and a termination resistor unit connected in parallel between a positive transmission pin and a negative transmission pin. The bias unit generates a bias voltage by selecting the higher voltage among a first voltage received through the positive transmission pin and a second voltage received through the negative transmission pin. The termination resistor unit is formed on a well region biased by the bias voltage, and conditionally provides a termination resistance between the positive transmission pin and the negative transmission pin in response to a termination resistor control signal. The termination circuit conditionally provides a termination resistance without a leakage current. The termination resistance may be varied by using an n-bit control code.
    • 用于HDMI发送器的终端电路包括在正传输引脚和负传输引脚之间并联连接的偏置单元和终端电阻器单元。 偏置单元通过选择通过正传输引脚接收的第一电压和通过负传输引脚接收的第二电压之间的较高电压来产生偏置电压。 终端电阻单元形成在由偏置电压偏置的阱区上,并且响应于终端电阻器控制信号有条件地在正传输引脚和负传输引脚之间提供终端电阻。 终端电路有条件地提供终端电阻而没有漏电流。 终端电阻可以通过使用n位控制代码来改变。
    • 5. 发明授权
    • High definition multimedia interface (HDMI) apparatus including termination circuit
    • 高分辨率多媒体接口(HDMI)设备,包括终端电路
    • US08624625B2
    • 2014-01-07
    • US13440457
    • 2012-04-05
    • Jong-Shin ShinChi-Won Kim
    • Jong-Shin ShinChi-Won Kim
    • H03K17/16H04B3/00
    • H03K19/017545H03K19/00315
    • A termination circuit for a HDMI transmitter includes a bias unit and a termination resistor unit connected in parallel between a positive transmission pin and a negative transmission pin. The bias unit generates a bias voltage by selecting the higher voltage among a first voltage received through the positive transmission pin and a second voltage received through the negative transmission pin. The termination resistor unit is formed on a well region biased by the bias voltage, and conditionally provides a termination resistance between the positive transmission pin and the negative transmission pin in response to a termination resistor control signal. The termination circuit conditionally provides a termination resistance without a leakage current. The termination resistance may be varied by using an n-bit control code.
    • 用于HDMI发送器的终端电路包括在正传输引脚和负传输引脚之间并联连接的偏置单元和终端电阻器单元。 偏置单元通过选择通过正传输引脚接收的第一电压和通过负传输引脚接收的第二电压之间的较高电压来产生偏置电压。 终端电阻单元形成在由偏置电压偏置的阱区上,并且响应于终端电阻器控制信号有条件地在正传输引脚和负传输引脚之间提供终端电阻。 终端电路有条件地提供终端电阻而没有漏电流。 终端电阻可以通过使用n位控制代码来改变。
    • 6. 发明授权
    • Serializer and method of serializing parallel data into serial data stream
    • 将并行数据串行化为串行数据流的串行器和方法
    • US06937173B2
    • 2005-08-30
    • US10770491
    • 2004-02-04
    • Chi-Won Kim
    • Chi-Won Kim
    • H03M9/00
    • H03M9/00
    • A serializer serializes N data (N>2) in N stages into a serial data stream. Each stage includes a logic section and a first inverter. The logic section receives i-th data (where i is less than or equal to N) of the N parallel data to output the i-th data or inverted i-th data in response to an active status or an inactive status of an j-th clock signal (where j is less than or equal to N) of the N clock signals. The first inverter receives the i-th data or the inverted i-th data from the logic section and inverts the i-th data or the inverted i-th data to output a first output signal. The output signal of the serializer may have reduced jitter even when the serializer operates in a high speed and a low power condition.
    • 串行器将N个阶段的N个数据(N> 2)串行化为串行数据流。 每个级包括逻辑部分和第一反相器。 逻辑部分接收N个并行数据的第i个数据(其中i小于或等于N),以响应于活动状态或j的不活动状态输出第i个数据或第i个数据 时钟信号(其中j小于或等于N)。 第一反相器从逻辑部分接收第i个数据或第i个数据,并将第i个数据或第i个数据反相,以输出第一个输出信号。 即使串行器在高速和低功率状态下工作,串行器的输出信号也可能具有降低的抖动。