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1. 发明申请

US20070184694A1 Wiring structure, semiconductor device and methods of forming the same 审中-公开
标题翻译：接线结构，半导体器件及其形成方法
公开(公告)号：US20070184694A1
公开(公告)日：2007-08-09
申请号：US11592242
申请日：2006-11-03
申请人： Jong-Kyu Kim , Jong-Chul Park , Jang-Bin Yim , Sang-Dong Kwon , Ki-Jeong Kim , Sung-Gil Choi
发明人： Jong-Kyu Kim , Jong-Chul Park , Jang-Bin Yim , Sang-Dong Kwon , Ki-Jeong Kim , Sung-Gil Choi
IPC分类号： H01R3/08
CPC分类号： H01L21/76816 , H01L21/76814 , H01L21/76831 , H01L21/76847 , H01L23/485 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： Example embodiments relate to a wiring structure, a semiconductor device and methods of forming the wiring structure. The wiring structure may include a first contact plug, a second contact plug, a protecting layer pattern and an insulating structure. The first contact plug may be provided on a semiconductor substrate. The second contact plug may be provided on the first contact plug to be electrically connected to the first contact plug. The protecting layer pattern may encompass an upper sidewall of the first contact plug and a sidewall of the second contact plug to retard chemicals from infiltrating into an interface between the first and second contact plugs. The insulating structure may encompass the first contact plug, the second contact plug and the protecting layer pattern.
摘要翻译：示例性实施例涉及布线结构，半导体器件和形成布线结构的方法。布线结构可以包括第一接触插塞，第二接触插塞，保护层图案和绝缘结构。第一接触插塞可以设置在半导体衬底上。第二接触插头可以设置在第一接触插塞上以电连接到第一接触插塞。保护层图案可以包括第一接触插塞的上侧壁和第二接触插塞的侧壁，以阻止化学品渗入第一和第二接触插塞之间的界面。绝缘结构可以包括第一接触插塞，第二接触插塞和保护层图案。

2. 发明申请

US20070066056A1 Method of removing a photoresist and method of manufacturing a semiconductor device using the same 审中-公开
标题翻译：去除光致抗蚀剂的方法和使用其制造半导体器件的方法
公开(公告)号：US20070066056A1
公开(公告)日：2007-03-22
申请号：US11447032
申请日：2006-06-06
申请人： Jong-Kyu Kim , Sung-Gil Choi , Jang-Bin Yim , Sang-Dong Kwon , Ki-Jeong Kim
发明人： Jong-Kyu Kim , Sung-Gil Choi , Jang-Bin Yim , Sang-Dong Kwon , Ki-Jeong Kim
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/31138 , G03F7/427 , H01J37/32091 , H01J2237/3342 , H01L27/10808 , H01L27/10852
摘要： Example embodiments of the present invention provide a method of removing a photoresist and a method of manufacturing a semiconductor device using the same. In a method of removing a photoresist and a method of manufacturing a semiconductor device, a plasma including active ions and radicals may be generated. The active ions may be modified into directional active ions. The photoresist may be etched using the directional active ions as main etching factors and/or the radicals as subsidiary etching factors. The photoresist may be completely removed from the semiconductor device such as a lower electrode. Thus, the likelihood of an increase in electrical resistance due to residual photoresist may decrease.
摘要翻译：本发明的示例性实施例提供一种去除光致抗蚀剂的方法和使用其制造半导体器件的方法。在去除光致抗蚀剂的方法和制造半导体器件的方法中，可以产生包括活性离子和自由基的等离子体。活性离子可以被修饰成定向活性离子。可以使用定向活性离子作为主要蚀刻因子和/或自由基作为辅助蚀刻因子来蚀刻光致抗蚀剂。光致抗蚀剂可以从诸如下电极的半导体器件完全去除。因此，残留光致抗蚀剂引起的电阻增加的可能性可能降低。

3. 发明申请

US20060289899A1 Semiconductor devices having fuses and methods of forming the same 有权
公开(公告)号：US20060289899A1
公开(公告)日：2006-12-28
申请号：US11447944
申请日：2006-06-07
申请人： Hyun-Chul Yoon , Jong-Kyu Kim , Jang-Bin Yim , Sang-Dong Kwon , Sung-Gil Choi
发明人： Hyun-Chul Yoon , Jong-Kyu Kim , Jang-Bin Yim , Sang-Dong Kwon , Sung-Gil Choi
IPC分类号： H01L27/10 , H01L21/82
CPC分类号： H01L27/101 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices having a plurality of fuses and methods of forming the same are provided. The semiconductor device having a fuse including a substrate having a cell region and/or a fuse box region. A first insulation interlayer may be formed on the substrate. A first etch stop layer may be formed on the first insulation interlayer. A metal wiring including a barrier layer, a metal layer and/or a capping layer may be formed on the first etch stop layer of the cell region. Fuses, spaced apart from each other, may be formed on the first etch stop layer of the fuse box region. Each fuse may include the barrier layer and/or the metal layer. A second insulation interlayer having an opening exposing the fuse box region may be formed on the metal wiring and/or the first etch stop layer. The etch stop layer may allow the fuses to be formed more uniformly and decrease the probability of breaking the fuses.

4. 发明申请

US20090184391A1 Semiconductor devices having fuses and methods of forming the same 审中-公开
公开(公告)号：US20090184391A1
公开(公告)日：2009-07-23
申请号：US12382168
申请日：2009-03-10
申请人： Hyun-Chul Yoon , Jong-Kyu Kim , Jang-Bin Yim , Sang-Dong Kwon , Sung-Gil Choi
发明人： Hyun-Chul Yoon , Jong-Kyu Kim , Jang-Bin Yim , Sang-Dong Kwon , Sung-Gil Choi
IPC分类号： H01L23/525
CPC分类号： H01L27/101 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices having a plurality of fuses and methods of forming the same are provided. The semiconductor device having a fuse including a substrate having a cell region and/or a fuse box region. A first insulation interlayer may be formed on the substrate. A first etch stop layer may be formed on the first insulation interlayer. A metal wiring including a barrier layer, a metal layer and/or a capping layer may be formed on the first etch stop layer of the cell region. Fuses, spaced apart from each other, may be formed on the first etch stop layer of the fuse box region. Each fuse may include the barrier layer and/or the metal layer. A second insulation interlayer having an opening exposing the fuse box region may be formed on the metal wiring and/or the first etch stop layer. The etch stop layer may allow the fuses to be formed more uniformly and decrease the probability of breaking the fuses.

5. 发明授权

US07510914B2 Semiconductor devices having fuses and methods of forming the same 有权
标题翻译：具有保险丝的半导体器件及其形成方法
公开(公告)号：US07510914B2
公开(公告)日：2009-03-31
申请号：US11447944
申请日：2006-06-07
申请人： Hyun-Chul Yoon , Jong-Kyu Kim , Jang-Bin Yim , Sang-Dong Kwon , Sung-Gil Choi
发明人： Hyun-Chul Yoon , Jong-Kyu Kim , Jang-Bin Yim , Sang-Dong Kwon , Sung-Gil Choi
IPC分类号： H01L21/82
CPC分类号： H01L27/101 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices having a plurality of fuses and methods of forming the same are provided. The semiconductor device having a fuse including a substrate having a cell region and/or a fuse box region. A first insulation interlayer may be formed on the substrate. A first etch stop layer may be formed on the first insulation interlayer. A metal wiring including a barrier layer, a metal layer and/or a capping layer may be formed on the first etch stop layer of the cell region. Fuses, spaced apart from each other, may be formed on the first etch stop layer of the fuse box region. Each fuse may include the barrier layer and/or the metal layer. A second insulation interlayer having an opening exposing the fuse box region may be formed on the metal wiring and/or the first etch stop layer. The etch stop layer may allow the fuses to be formed more uniformly and decrease the probability of breaking the fuses.
摘要翻译：提供具有多个保险丝的半导体器件及其形成方法。该半导体器件具有包括具有单元区域和/或保险丝盒区域的衬底的熔丝。可以在基板上形成第一绝缘中间层。可以在第一绝缘中间层上形成第一蚀刻停止层。可以在单元区域的第一蚀刻停止层上形成包括阻挡层，金属层和/或覆盖层的金属布线。彼此间隔开的保险丝可以形成在保险丝盒区域的第一蚀刻停止层上。每个熔断器可以包括阻挡层和/或金属层。具有暴露熔丝盒区域的开口的第二绝缘夹层可以形成在金属布线和/或第一蚀刻停止层上。蚀刻停止层可以允许保险丝更均匀地形成并且降低断开保险丝的可能性。

6. 发明申请

US20090117723A1 Methods of forming a conductive pattern in semiconductor devices and methods of manufacturing semiconductor devices having a conductive pattern 审中-公开
标题翻译：在半导体器件中形成导电图案的方法和制造具有导电图案的半导体器件的方法
公开(公告)号：US20090117723A1
公开(公告)日：2009-05-07
申请号：US12287945
申请日：2008-10-15
申请人： Jong-Kyu Kim , Bum-Soo Kim , Jong-Heui Song , Sang-Sup Jeong , Sung-Gil Choi , Kuk-Han Yoon
发明人： Jong-Kyu Kim , Bum-Soo Kim , Jong-Heui Song , Sang-Sup Jeong , Sung-Gil Choi , Kuk-Han Yoon
IPC分类号： H01L21/28 , H01L21/283
CPC分类号： H01L29/42324 , H01L21/02071 , H01L21/31122 , H01L21/31138 , H01L21/32139 , H01L27/11521 , H01L29/40114
摘要： In a method of forming a conductive pattern in a semiconductor device, a conductive layer including a metal is formed on a substrate. A mask including carbon is provided on the conductive layer, and the conductive pattern is formed on the substrate by etching the conductive layer using the mask as an etching mask. The mask is removed from the conductive pattern by an oxygen plasma ashing process. An oxidized portion of the conductive pattern is reduced. The conductive pattern may have a desired resistance by reducing the oxidized portion to improve electrical characteristics and reliability of the semiconductor device.
摘要翻译：在半导体器件中形成导电图案的方法中，在衬底上形成包括金属的导电层。在导电层上设置包含碳的掩模，并且通过使用掩模作为蚀刻掩模蚀刻导电层，在基板上形成导电图案。通过氧等离子体灰化处理将掩模从导电图案中去除。导电图案的氧化部分减少。导电图案可以通过减少氧化部分而具有期望的电阻，以改善半导体器件的电特性和可靠性。

7. 发明申请

US20100237466A1 SEMICONDUCTOR DEVICES 有权
标题翻译：半导体器件
公开(公告)号：US20100237466A1
公开(公告)日：2010-09-23
申请号：US12724450
申请日：2010-03-16
申请人： Jong-Kyu Kim , Sang-Sup Jeong , Sung-Gil Choi , Heung-Sik Park , Kuk-Han Yoon , Yong-Joon Choi
发明人： Jong-Kyu Kim , Sang-Sup Jeong , Sung-Gil Choi , Heung-Sik Park , Kuk-Han Yoon , Yong-Joon Choi
IPC分类号： H01L29/92
CPC分类号： H01L27/10852 , H01L28/91
摘要： A semiconductor device includes a lower electrode, a supporting member enclosing at least an upper portion of the lower electrode, a dielectric layer on the lower electrode and the supporting member, and an upper electrode disposed on the dielectric layer. The supporting member may have a first portion that extends over an upper part of the sidewall of the lower electrode, and a second portion covering the upper surface of the lower electrode. The first portion of the supporting member protrudes above the lower electrode.
摘要翻译：半导体器件包括下电极，至少包围下电极的上部的支撑构件，下电极上的电介质层和支撑构件，以及设置在电介质层上的上电极。支撑构件可以具有在下电极的侧壁的上部上延伸的第一部分和覆盖下电极的上表面的第二部分。支撑构件的第一部分突出在下电极的上方。

8. 发明授权

US07557026B2 Contact structure and method of forming the same 有权
标题翻译：接触结构及其形成方法
公开(公告)号：US07557026B2
公开(公告)日：2009-07-07
申请号：US11711118
申请日：2007-02-27
申请人： Jong-Kyu Kim , Sang-Sup Jeong , Sung-Gil Choi , Kuk-Han Yoon , Bum-Soo Kim
发明人： Jong-Kyu Kim , Sang-Sup Jeong , Sung-Gil Choi , Kuk-Han Yoon , Bum-Soo Kim
IPC分类号： H01L21/44
CPC分类号： H01L21/76838 , H01L21/76804 , H01L21/76816 , H01L21/76897 , H01L27/11521
摘要： In a method of forming a contact structure, first and second conductive structures may be formed on a lower structure to be spaced from each other. An insulating layer may be formed on the lower structure to cover the first and second conductive structures. A first hole exposing the first conductive structure may be formed through the insulating layer. A spacer may be formed on a sidewall of the first hole. A first contact electrically coupled to the first conductive structure may be formed in the first hole having the sidewall on which the spacer is formed. A portion of the insulating layer located between the spacers may be removed to form a second hole exposing the second conductive structure. A second contact electrically coupled to the second conductive structure may be formed in the second hole.
摘要翻译：在形成接触结构的方法中，第一和第二导电结构可以形成在下部结构上以彼此间隔开。可以在下部结构上形成绝缘层以覆盖第一和第二导电结构。露出第一导电结构的第一孔可以通过绝缘层形成。间隔件可以形成在第一孔的侧壁上。电耦合到第一导电结构的第一触点可以形成在具有形成间隔件的侧壁的第一孔中。可以去除位于间隔物之间的绝缘层的一部分，以形成暴露第二导电结构的第二孔。电耦合到第二导电结构的第二触点可以形成在第二孔中。

9. 发明申请

US20060046382A1 Method of forming a capacitor for a semiconductor device 审中-公开
标题翻译：形成用于半导体器件的电容器的方法
公开(公告)号：US20060046382A1
公开(公告)日：2006-03-02
申请号：US11206418
申请日：2005-08-17
申请人： Kuk-Han Yoon , Sang-Sup Jeong , Sung-Gil Choi , Jong-Kyu Kim
发明人： Kuk-Han Yoon , Sang-Sup Jeong , Sung-Gil Choi , Jong-Kyu Kim
IPC分类号： H01L21/8242
CPC分类号： H01L27/10817 , H01L27/10852 , H01L28/91
摘要： In an embodiment, a method of forming a capacitor for a semiconductor device of which structural stability is improved is shown. Cylindrical storage electrodes are formed in a matrix pattern on a substrate that includes an insulation interlayer having contacts therein so that a mold layer surrounds the cylindrical storage electrodes. Sacrificial plugs are formed with a cap within these electrodes. A stabilizing layer is formed on the etched mold layer and the cylindrical storage electrode by partially etching the mold layer. The stabilizing layer is etched until the sacrificial plug is exposed, thereby forming a spacer. While the sacrificial plug and the mold layer are fully removed, the spacer is partially removed, thereby forming a stabilizing member for supporting neighboring storage electrodes adjacent to each other. Accordingly, a structural stability of the capacitor is improved.
摘要翻译：在一个实施例中，示出了形成其结构稳定性提高的半导体器件的电容器的方法。圆柱形存储电极在基板上以矩阵图案形成，该基板包括其中具有触点的绝缘中间层，使得模具层围绕圆柱形存储电极。牺牲塞在这些电极内形成有盖。通过部分蚀刻模具层，在蚀刻的模具层和圆柱形存储电极上形成稳定层。蚀刻稳定层，直到牺牲塞被暴露，从而形成间隔物。尽管完全去除了牺牲塞和模具层，但是间隔件被部分地移除，从而形成用于支撑彼此相邻的相邻存储电极的稳定构件。因此，提高了电容器的结构稳定性。

10. 发明授权

US08704283B2 Semiconductor devices 有权
标题翻译：半导体器件
公开(公告)号：US08704283B2
公开(公告)日：2014-04-22
申请号：US12724450
申请日：2010-03-16
申请人： Jong-Kyu Kim , Sang-Sup Jeong , Sung-Gil Choi , Heung-Sik Park , Kuk-Han Yoon , Yong-Joon Choi
发明人： Jong-Kyu Kim , Sang-Sup Jeong , Sung-Gil Choi , Heung-Sik Park , Kuk-Han Yoon , Yong-Joon Choi
IPC分类号： H01L27/108
CPC分类号： H01L27/10852 , H01L28/91
摘要： A semiconductor device includes a lower electrode, a supporting member enclosing at least an upper portion of the lower electrode, a dielectric layer on the lower electrode and the supporting member, and an upper electrode disposed on the dielectric layer. The supporting member may have a first portion that extends over an upper part of the sidewall of the lower electrode, and a second portion covering the upper surface of the lower electrode. The first portion of the supporting member protrudes above the lower electrode.
摘要翻译：半导体器件包括下电极，至少包围下电极的上部的支撑构件，下电极上的电介质层和支撑构件，以及设置在电介质层上的上电极。支撑构件可以具有在下电极的侧壁的上部上延伸的第一部分和覆盖下电极的上表面的第二部分。支撑构件的第一部分突出在下电极的上方。

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