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1. 发明申请

US20060289899A1 Semiconductor devices having fuses and methods of forming the same 有权
公开(公告)号：US20060289899A1
公开(公告)日：2006-12-28
申请号：US11447944
申请日：2006-06-07
申请人： Hyun-Chul Yoon , Jong-Kyu Kim , Jang-Bin Yim , Sang-Dong Kwon , Sung-Gil Choi
发明人： Hyun-Chul Yoon , Jong-Kyu Kim , Jang-Bin Yim , Sang-Dong Kwon , Sung-Gil Choi
IPC分类号： H01L27/10 , H01L21/82
CPC分类号： H01L27/101 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices having a plurality of fuses and methods of forming the same are provided. The semiconductor device having a fuse including a substrate having a cell region and/or a fuse box region. A first insulation interlayer may be formed on the substrate. A first etch stop layer may be formed on the first insulation interlayer. A metal wiring including a barrier layer, a metal layer and/or a capping layer may be formed on the first etch stop layer of the cell region. Fuses, spaced apart from each other, may be formed on the first etch stop layer of the fuse box region. Each fuse may include the barrier layer and/or the metal layer. A second insulation interlayer having an opening exposing the fuse box region may be formed on the metal wiring and/or the first etch stop layer. The etch stop layer may allow the fuses to be formed more uniformly and decrease the probability of breaking the fuses.

2. 发明授权

US07510914B2 Semiconductor devices having fuses and methods of forming the same 有权
标题翻译：具有保险丝的半导体器件及其形成方法
公开(公告)号：US07510914B2
公开(公告)日：2009-03-31
申请号：US11447944
申请日：2006-06-07
申请人： Hyun-Chul Yoon , Jong-Kyu Kim , Jang-Bin Yim , Sang-Dong Kwon , Sung-Gil Choi
发明人： Hyun-Chul Yoon , Jong-Kyu Kim , Jang-Bin Yim , Sang-Dong Kwon , Sung-Gil Choi
IPC分类号： H01L21/82
CPC分类号： H01L27/101 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices having a plurality of fuses and methods of forming the same are provided. The semiconductor device having a fuse including a substrate having a cell region and/or a fuse box region. A first insulation interlayer may be formed on the substrate. A first etch stop layer may be formed on the first insulation interlayer. A metal wiring including a barrier layer, a metal layer and/or a capping layer may be formed on the first etch stop layer of the cell region. Fuses, spaced apart from each other, may be formed on the first etch stop layer of the fuse box region. Each fuse may include the barrier layer and/or the metal layer. A second insulation interlayer having an opening exposing the fuse box region may be formed on the metal wiring and/or the first etch stop layer. The etch stop layer may allow the fuses to be formed more uniformly and decrease the probability of breaking the fuses.
摘要翻译：提供具有多个保险丝的半导体器件及其形成方法。该半导体器件具有包括具有单元区域和/或保险丝盒区域的衬底的熔丝。可以在基板上形成第一绝缘中间层。可以在第一绝缘中间层上形成第一蚀刻停止层。可以在单元区域的第一蚀刻停止层上形成包括阻挡层，金属层和/或覆盖层的金属布线。彼此间隔开的保险丝可以形成在保险丝盒区域的第一蚀刻停止层上。每个熔断器可以包括阻挡层和/或金属层。具有暴露熔丝盒区域的开口的第二绝缘夹层可以形成在金属布线和/或第一蚀刻停止层上。蚀刻停止层可以允许保险丝更均匀地形成并且降低断开保险丝的可能性。

3. 发明申请

US20090184391A1 Semiconductor devices having fuses and methods of forming the same 审中-公开
公开(公告)号：US20090184391A1
公开(公告)日：2009-07-23
申请号：US12382168
申请日：2009-03-10
申请人： Hyun-Chul Yoon , Jong-Kyu Kim , Jang-Bin Yim , Sang-Dong Kwon , Sung-Gil Choi
发明人： Hyun-Chul Yoon , Jong-Kyu Kim , Jang-Bin Yim , Sang-Dong Kwon , Sung-Gil Choi
IPC分类号： H01L23/525
CPC分类号： H01L27/101 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices having a plurality of fuses and methods of forming the same are provided. The semiconductor device having a fuse including a substrate having a cell region and/or a fuse box region. A first insulation interlayer may be formed on the substrate. A first etch stop layer may be formed on the first insulation interlayer. A metal wiring including a barrier layer, a metal layer and/or a capping layer may be formed on the first etch stop layer of the cell region. Fuses, spaced apart from each other, may be formed on the first etch stop layer of the fuse box region. Each fuse may include the barrier layer and/or the metal layer. A second insulation interlayer having an opening exposing the fuse box region may be formed on the metal wiring and/or the first etch stop layer. The etch stop layer may allow the fuses to be formed more uniformly and decrease the probability of breaking the fuses.

4. 发明申请

US20070066056A1 Method of removing a photoresist and method of manufacturing a semiconductor device using the same 审中-公开
标题翻译：去除光致抗蚀剂的方法和使用其制造半导体器件的方法
公开(公告)号：US20070066056A1
公开(公告)日：2007-03-22
申请号：US11447032
申请日：2006-06-06
申请人： Jong-Kyu Kim , Sung-Gil Choi , Jang-Bin Yim , Sang-Dong Kwon , Ki-Jeong Kim
发明人： Jong-Kyu Kim , Sung-Gil Choi , Jang-Bin Yim , Sang-Dong Kwon , Ki-Jeong Kim
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/31138 , G03F7/427 , H01J37/32091 , H01J2237/3342 , H01L27/10808 , H01L27/10852
摘要： Example embodiments of the present invention provide a method of removing a photoresist and a method of manufacturing a semiconductor device using the same. In a method of removing a photoresist and a method of manufacturing a semiconductor device, a plasma including active ions and radicals may be generated. The active ions may be modified into directional active ions. The photoresist may be etched using the directional active ions as main etching factors and/or the radicals as subsidiary etching factors. The photoresist may be completely removed from the semiconductor device such as a lower electrode. Thus, the likelihood of an increase in electrical resistance due to residual photoresist may decrease.
摘要翻译：本发明的示例性实施例提供一种去除光致抗蚀剂的方法和使用其制造半导体器件的方法。在去除光致抗蚀剂的方法和制造半导体器件的方法中，可以产生包括活性离子和自由基的等离子体。活性离子可以被修饰成定向活性离子。可以使用定向活性离子作为主要蚀刻因子和/或自由基作为辅助蚀刻因子来蚀刻光致抗蚀剂。光致抗蚀剂可以从诸如下电极的半导体器件完全去除。因此，残留光致抗蚀剂引起的电阻增加的可能性可能降低。

5. 发明申请

US20070184694A1 Wiring structure, semiconductor device and methods of forming the same 审中-公开
标题翻译：接线结构，半导体器件及其形成方法
公开(公告)号：US20070184694A1
公开(公告)日：2007-08-09
申请号：US11592242
申请日：2006-11-03
申请人： Jong-Kyu Kim , Jong-Chul Park , Jang-Bin Yim , Sang-Dong Kwon , Ki-Jeong Kim , Sung-Gil Choi
发明人： Jong-Kyu Kim , Jong-Chul Park , Jang-Bin Yim , Sang-Dong Kwon , Ki-Jeong Kim , Sung-Gil Choi
IPC分类号： H01R3/08
CPC分类号： H01L21/76816 , H01L21/76814 , H01L21/76831 , H01L21/76847 , H01L23/485 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： Example embodiments relate to a wiring structure, a semiconductor device and methods of forming the wiring structure. The wiring structure may include a first contact plug, a second contact plug, a protecting layer pattern and an insulating structure. The first contact plug may be provided on a semiconductor substrate. The second contact plug may be provided on the first contact plug to be electrically connected to the first contact plug. The protecting layer pattern may encompass an upper sidewall of the first contact plug and a sidewall of the second contact plug to retard chemicals from infiltrating into an interface between the first and second contact plugs. The insulating structure may encompass the first contact plug, the second contact plug and the protecting layer pattern.
摘要翻译：示例性实施例涉及布线结构，半导体器件和形成布线结构的方法。布线结构可以包括第一接触插塞，第二接触插塞，保护层图案和绝缘结构。第一接触插塞可以设置在半导体衬底上。第二接触插头可以设置在第一接触插塞上以电连接到第一接触插塞。保护层图案可以包括第一接触插塞的上侧壁和第二接触插塞的侧壁，以阻止化学品渗入第一和第二接触插塞之间的界面。绝缘结构可以包括第一接触插塞，第二接触插塞和保护层图案。

6. 发明申请

US20080214009A1 Methods of Forming a Recess Structure and Methods of Manufacturing a Semiconductor Device Having a Recessed-Gate Structure 审中-公开
标题翻译：形成凹陷结构的方法和制造具有嵌入门结构的半导体器件的方法
公开(公告)号：US20080214009A1
公开(公告)日：2008-09-04
申请号：US12020841
申请日：2008-01-28
申请人： Chi-Hoon Lee , Jong-Chul Park , Tae-Woo Lee , Tae-Woo Kang , Jang-Bin Yim
发明人： Chi-Hoon Lee , Jong-Chul Park , Tae-Woo Lee , Tae-Woo Kang , Jang-Bin Yim
IPC分类号： H01L21/311
CPC分类号： H01L21/3083 , H01L29/4236 , H01L29/42376 , H01L29/66553 , H01L29/66621
摘要： Methods of forming a recess structure having a gentle curvature are provided. Such methods include forming a hard mask on a substrate, forming a first preliminary recess on the substrate using the hard mask as an etching mask and forming a spacer on a sidewall of the first preliminary recess. Methods may include forming a second preliminary recess from the first preliminary recess using the spacer as an etching mask and forming the recess structure having an enlarged lower portion from the second preliminary recess using the spacer as an etching mask.
摘要翻译：提供了形成具有平缓曲率的凹陷结构的方法。这样的方法包括在基板上形成硬掩模，使用硬掩模作为蚀刻掩模在基板上形成第一预备凹槽，并在第一初步凹槽的侧壁上形成间隔物。方法可以包括使用间隔件作为蚀刻掩模从第一预备凹部形成第二预备凹槽，并且使用间隔件作为蚀刻掩模形成具有从第二预备凹部放大的下部的凹部结构。

7. 发明申请

US20070047304A1 Non-volatile semiconductor memory device and method of manufacturing the same 审中-公开
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20070047304A1
公开(公告)日：2007-03-01
申请号：US11508919
申请日：2006-08-24
申请人： Seong-Soo Lee , Young-Wook Park , Jang-Bin Yim , Bum-Su Kim , Du-Hyun Cho
发明人： Seong-Soo Lee , Young-Wook Park , Jang-Bin Yim , Bum-Su Kim , Du-Hyun Cho
IPC分类号： G11C11/34
CPC分类号： H01L27/115 , H01L27/11521
摘要： In a non-volatile memory device having a relatively high operation performance and a method of manufacturing the same, a substrate may be prepared to include an active region on which a conductive structure is located and defined by a field region in which an isolation layer is formed. A tunnel oxide layer may be formed on the active region of the substrate. A floating gate pattern may be formed on the tunnel oxide layer, and may include a lower part having a first width that is formed on the tunnel oxide layer and an upper part having a second width that is formed on the lower part, where the second width is substantially smaller than the first width. A dielectric layer pattern may be formed on the floating gate pattern, and a control gate pattern may be formed on the dielectric layer pattern. Accordingly, the non-volatile memory device may have an improved efficiency in programming and erasing data.
摘要翻译：在具有较高操作性能的非易失性存储器件及其制造方法中，衬底可以被制备为包括有源区，导电结构位于该有源区上，该区域由隔离层为形成。可以在衬底的有源区上形成隧道氧化物层。可以在隧道氧化物层上形成浮置栅极图案，并且可以包括形成在隧道氧化物层上的第一宽度的下部和形成在下部的第二宽度的上部，宽度基本上小于第一宽度。可以在浮置栅极图案上形成电介质层图案，并且可以在电介质层图案上形成控制栅极图案。因此，非易失性存储器件可以提高编程和擦除数据的效率。

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