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1. 发明申请

US20060194418A1 Smooth surface liquid phase epitaxial germanium 有权
标题翻译：光滑表面液相外延锗
公开(公告)号：US20060194418A1
公开(公告)日：2006-08-31
申请号：US11339017
申请日：2006-01-25
申请人： Jong-Jan Lee , Jer-Shen Maa , Douglas Tweet , David Evans , Allen Burmaster
发明人： Jong-Jan Lee , Jer-Shen Maa , Douglas Tweet , David Evans , Allen Burmaster
IPC分类号： H01L21/20 , H01L21/311
CPC分类号： C30B19/00 , C30B29/08 , H01L21/02381 , H01L21/02488 , H01L21/02532 , H01L21/02623 , H01L21/02639 , H01L21/30625 , H01L21/7624 , H01L27/14683 , H01L27/14689 , H01L29/16 , H01L29/78 , H01L31/028 , H01L31/105 , H01L31/1126 , H01L31/1136 , H01L31/1804 , H01L31/1808 , Y02E10/547 , Y02P70/521
摘要： A method is provided for forming a liquid phase epitaxial (LPE) germanium (Ge)-on-insulator (GOI) thin-film with a smooth surface. The method provides a silicon (Si) wafer, forms a silicon nitride insulator layer overlying the Si wafer, and selectively etches the silicon nitride insulator layer, forming a Si seed access region. Then, the method conformally deposits Ge overlying the silicon nitride insulator layer and Si seed access region, forming a Ge layer with a first surface roughness, and smoothes the Ge layer using a chemical-mechanical polish (CMP) process. Typically, the method encapsulates the Ge layer and anneals the Ge layer to form a LPE Ge layer. A Ge layer is formed with a second surface roughness, less than the first surface roughness. In some aspects, the method forms an active device in the LPE Ge layer.
摘要翻译：提供一种形成具有光滑表面的液相外延（LPE）锗（Ge） - 绝缘体（GOI）薄膜的方法。该方法提供硅（Si）晶片，形成覆盖Si晶片的氮化硅绝缘体层，并且选择性地蚀刻氮化硅绝缘体层，形成Si种子接入区域。然后，该方法共同沉积覆盖氮化硅绝缘体层和Si种子访问区域的Ge，形成具有第一表面粗糙度的Ge层，并且使用化学机械抛光（CMP）工艺平滑Ge层。通常，该方法封装Ge层并退火Ge层以形成LPE Ge层。 Ge层形成有小于第一表面粗糙度的第二表面粗糙度。在某些方面，该方法在LPE Ge层中形成有源器件。

2. 发明申请

US20050153524A1 Strained silicon on insulator from film transfer and relaxation by hydrogen implantation 有权
标题翻译：绝缘体上的应变硅通过氢注入从膜转移和弛豫
公开(公告)号：US20050153524A1
公开(公告)日：2005-07-14
申请号：US10755615
申请日：2004-01-12
申请人： Jer-shen Maa , Jong-Jan Lee , Douglas Tweet , David Evans , Allen Burmaster , Sheng Hsu
发明人： Jer-shen Maa , Jong-Jan Lee , Douglas Tweet , David Evans , Allen Burmaster , Sheng Hsu
IPC分类号： H01L21/762 , H01L21/02 , H01L21/30 , H01L21/46 , H01L27/12
CPC分类号： H01L21/76254
摘要： Transistors fabricated on SSOI (Strained Silicon On Insulator) substrate, which comprises a strained silicon layer disposed directly on an insulator layer, have enhanced device performance due to the strain-induced band modification of the strained silicon device channel and the limited silicon volume because of the insulator layer. The present invention discloses a SSOI substrate fabrication process comprising various novel approaches. One is the use of a thin relaxed SiGe layer as the strain-induced seed layer to facilitate integration and reduce processing cost. Another is the formation of split implant microcracks deep in the silicon substrate to reduce the number of threading dislocations reaching the strained silicon layer. And lastly is the two step annealing/thinning process for the strained silicon/SiGe multilayer film transfer without blister or flaking formation.
摘要翻译：包含直接设置在绝缘体层上的应变硅层的SSOI（应变绝缘体硅）基板上制造的晶体管由于应变诱导的应变硅器件通道的带隙修改而增加了器件性能，并且由于绝缘体层。本发明公开了一种包括各种新方法的SSOI衬底制造工艺。一个是使用薄的松弛SiGe层作为应变诱导的种子层，以促进整合并降低加工成本。另一个是在硅衬底深部形成分裂的植入物微裂纹，以减少到达应变硅层的穿透位错的数量。最后是对应变硅/ SiGe多层膜转移的两步退火/变薄处理，没有起泡或剥落形成。

3. 发明申请

US20060073708A1 Strained silicon on insulator from film transfer and relaxation by hydrogen implantation 有权
标题翻译：绝缘体上的应变硅通过氢注入从膜转移和弛豫
公开(公告)号：US20060073708A1
公开(公告)日：2006-04-06
申请号：US11284326
申请日：2005-11-21
申请人： Jer-shen Maa , Jong-Jan Lee , Douglas Tweet , David Evans , Allen Burmaster , Sheng Hsu
发明人： Jer-shen Maa , Jong-Jan Lee , Douglas Tweet , David Evans , Allen Burmaster , Sheng Hsu
IPC分类号： H01L21/324
CPC分类号： H01L21/76254
摘要： Transistors fabricated on SSOI (Strained Silicon On Insulator) substrate, which comprises a strained silicon layer disposed directly on an insulator layer, have enhanced device performance due to the strain-induced band modification of the strained silicon device channel and the limited silicon volume because of the insulator layer. The present invention discloses SSOI substrate fabrication processes comprising various novel approaches. One is the use of a thin relaxed SiGe layer as the strain-induced seed layer to facilitate integration and reduce processing cost. Another is the formation of split implant microcracks deep in the silicon substrate to reduce the number of threading dislocations reaching the strained silicon layer. And lastly is a two step annealing/thinning process for the strained silicon/SiGe multilayer film transfer without blister or flaking formation.
摘要翻译：包含直接设置在绝缘体层上的应变硅层的SSOI（应变绝缘体硅）基板上制造的晶体管由于应变诱导的应变硅器件通道的带隙修改而增加了器件性能，并且由于绝缘体层。本发明公开了包含各种新颖方法的SSOI衬底制造工艺。一个是使用薄的松弛SiGe层作为应变诱导的种子层，以促进整合并降低加工成本。另一个是在硅衬底深部形成分裂的植入物微裂纹，以减少到达应变硅层的穿透位错的数量。最后是对应变硅/ SiGe多层膜转移进行两步退火/变薄处理，无需起泡或剥落形成。

4. 发明申请

US20070290288A1 Floating body germanium phototransistor having a photo absorption threshold bias region 有权
标题翻译：具有光吸收阈值偏置区域的浮体锗光电晶体管
公开(公告)号：US20070290288A1
公开(公告)日：2007-12-20
申请号：US11894938
申请日：2007-08-22
申请人： Sheng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas Tweet
发明人： Sheng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas Tweet
IPC分类号： H01L31/10
CPC分类号： H01L31/1136
摘要： A floating body germanium (Ge) phototransistor with a photo absorption threshold bias region, and an associated fabrication process are presented. The method includes: providing a p-doped Silicon (Si) substrate; selectively forming an insulator layer overlying a first surface of the Si substrate; forming an epitaxial Ge layer overlying the insulator layer; forming a channel region in the Ge layer; forming a gate dielectric, gate electrode, and gate spacers; forming source/drain (S/D) regions in the Ge layer; and, forming a photo absorption threshold bias region in the Ge layer, adjacent the channel region. In one aspect, the second S/D region has a length, longer than the first S/D length. The photo absorption threshold bias region underlies the second S/D region. Alternately, the second S/D region is separated from the channel by an offset, and the photo absorption threshold bias region is the offset in the Ge layer, after a light p-doping.
摘要翻译：提出了具有光吸收阈值偏置区域的浮体锗（Ge）光电晶体管，以及相关的制造工艺。该方法包括：提供p掺杂硅（Si）衬底; 选择性地形成覆盖在所述Si衬底的第一表面上的绝缘体层; 形成覆盖绝缘体层的外延Ge层; 在Ge层中形成沟道区; 形成栅极电介质，栅电极和栅极间隔物; 在Ge层中形成源极/漏极（S / D）区域; 并且在Ge层中形成邻近沟道区的光吸收阈值偏置区域。在一个方面，第二S / D区域具有比第一S / D长度更长的长度。光吸收阈值偏置区域位于第二S / D区域的下方。或者，第二S / D区域与沟道分离偏移，光吸收阈值偏置区域是在光p掺杂之后的Ge层中的偏移。

5. 发明申请

US20060281232A1 Method of growing a germanium epitaxial film on insulator for use in fabrication of a CMOS integrated circuit 有权
标题翻译：在绝缘体上生长用于制造CMOS集成电路的锗外延膜的方法
公开(公告)号：US20060281232A1
公开(公告)日：2006-12-14
申请号：US11149891
申请日：2005-06-10
申请人： Sheng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas Tweet
发明人： Sheng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas Tweet
IPC分类号： H01L21/84
CPC分类号： H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/1203 , H01L29/78684
摘要： A method of fabricating a silicon-germanium CMOS includes preparing a silicon substrate wafer; depositing an insulating layer on the silicon substrate wafer; patterning and etching the insulating layer; depositing a layer of polycrystalline germanium on the insulating layer and on at least a portion of the silicon substrate wafer; patterning and etching the polycrystalline germanium; encapsulating the polycrystalline germanium with an insulating material; rapidly thermally annealing the wafer at a temperature sufficient to melt the polycrystalline germanium; cooling the wafer to promote liquid phase epitaxy of the polycrystalline germanium, thereby forming a single crystal germanium layer; and completing the CMOS device.
摘要翻译：制造硅 - 锗CMOS的方法包括制备硅衬底晶片; 在硅衬底晶片上沉积绝缘层; 图案化和蚀刻绝缘层; 在所述绝缘层和所述硅衬底晶片的至少一部分上沉积多晶锗层; 图案化和蚀刻多晶锗; 用绝缘材料封装多晶锗; 在足以熔化多晶锗的温度下快速热退火晶片; 冷却晶片以促进多晶锗的液相外延，从而形成单晶锗层; 并完成CMOS设备。

6. 发明申请

US20060194415A1 Germanium infrared sensor for CMOS imagers 有权
标题翻译：锗红外传感器用于CMOS成像器
公开(公告)号：US20060194415A1
公开(公告)日：2006-08-31
申请号：US11069422
申请日：2005-02-28
申请人： Jong-Jan Lee , Jer-Shen Maa , Sheng Hsu , Douglas Tweet
发明人： Jong-Jan Lee , Jer-Shen Maa , Sheng Hsu , Douglas Tweet
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L27/14634 , H01L27/14649 , H01L27/14689 , H01L27/1469 , H01L31/028 , H01L31/103 , H01L31/1804 , H01L31/1808 , H01L31/1864 , Y02E10/547 , Y02P70/521
摘要： A method of fabricating a germanium infrared sensor for a CMOS imager includes preparation a donor wafer, including: ion implantation into a silicon wafer to form a P+ silicon layer; growing an epitaxial germanium layer on the P+ silicon layer, forming a silicon-germanium interface; cyclic annealing; and implanting hydrogen ions to a depth at least as deep as the P+ silicon layer to form a defect layer; preparing a handling wafer, including: fabricating a CMOS integrated circuit on a silicon substrate; depositing a layer of refractory metal; treating the surfaces of the donor wafer and the handling wafer for bonding; bonding the handling wafer and the donor wafer to form a bonded structure; splitting the bonded structure along the defect layer; depositing a layer of indium tin oxide on the germanium layer; completing the IR sensor.
摘要翻译：制造用于CMOS成像器的锗红外传感器的方法包括制备施主晶片，其包括：离子注入到硅晶片中以形成P +硅层; 在P +硅层上生长外延锗层，形成硅 - 锗界面; 循环退火; 以及将氢离子注入至少与P +硅层一样深的深度以形成缺陷层; 制备处理晶片，包括：在硅衬底上制造CMOS集成电路; 沉积难熔金属层; 处理供体晶片的表面和用于结合的处理晶片; 结合处理晶片和施主晶片以形成结合结构; 沿着缺陷层分离粘结结构; 在锗层上沉积一层氧化铟锡; 完成IR传感器。

7. 发明申请

US20050070115A1 Method of making relaxed silicon-germanium on insulator via layer transfer with stress reduction 失效
标题翻译：通过层压转移在绝缘体上制备松弛硅锗的方法
公开(公告)号：US20050070115A1
公开(公告)日：2005-03-31
申请号：US10677005
申请日：2003-09-30
申请人： Jer-Shen Maa , Jong-Jan Lee , Douglas Tweet , Sheng Hsu
发明人： Jer-Shen Maa , Jong-Jan Lee , Douglas Tweet , Sheng Hsu
IPC分类号： H01L21/20 , H01L21/302 , H01L21/461 , H01L21/762
CPC分类号： H01L21/76254
摘要： A method of forming a silicon-germanium layer on an insulator includes depositing a layer of silicon-germanium on a silicon substrate to form a silicon/silicon-germanium portion; implanting hydrogen ions into the silicon substrate between about 500 Å to 1 μm below a silicon-germanium/silicon interface; bonding the silicon/silicon-germanium portion to an insulator substrate to form a couplet; thermally annealing the couplet in a first thermal annealing step to split the couplet; patterning and etching the silicon-germanium-on-insulator portion to remove portions of the silicon and SiGe layers; etching the silicon-germanium-on-insulator portion to remove the remaining silicon layer; thermally annealing the silicon-germanium-on-insulator portion in a second annealing step to relaxed the SiGe layer; and depositing a layer of strained silicon about the SiGe layer.
摘要翻译：在绝缘体上形成硅 - 锗层的方法包括在硅衬底上沉积硅 - 锗层以形成硅/硅 - 锗部分; 在硅 - 锗/硅界面之下的约500埃至1微米处将氢离子注入到硅衬底中; 将硅/硅锗部分接合到绝缘体基板上以形成对联体; 在第一热退火步骤中对联接件进行热退火以分离联接件; 图案化和蚀刻绝缘体上硅部分以去除部分硅和SiGe层; 蚀刻绝缘体上硅部分以除去剩余的硅层; 在第二退火步骤中对绝缘体上硅部分进行热退火以松弛SiGe层; 以及在SiGe层周围沉积一层应变硅。

8. 发明申请

US20070170536A1 Liquid phase epitaxial GOI photodiode with buried high resistivity germanium layer 审中-公开
标题翻译：液相外延GOI光电二极管，埋置高电阻率锗层
公开(公告)号：US20070170536A1
公开(公告)日：2007-07-26
申请号：US11339011
申请日：2006-01-25
申请人： Sheng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas Tweet
发明人： Sheng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas Tweet
IPC分类号： H01L31/00
CPC分类号： H01L31/1055 , H01L31/1808 , H01L31/1872 , Y02E10/50
摘要： A device and associated method are provided for fabricating a liquid phase epitaxial (LPE) Germanium-on-Insulator (GOI) photodiode with buried high resistivity Germanium (Ge) layer. The method provides a silicon (Si) substrate, and forms a bottom insulator overlying the Si substrate with a Si seed access area. Then, a Ge P-I-N diode is formed with an n +-doped (n+) mesa, a p+-doped (p+) Ge bottom insulator interface and mesa lateral interface, and a high resistivity Ge layer interposed between the p+ Ge and n+ Ge. A metal electrode is formed overlying a region of the p+ Ge lateral interface, and a transparent electrode is formed overlying the n+ Ge mesa. In one aspect, the method deposits a silicon nitride layer temporary cap overlying the high resistivity Ge layer, and an annealing is performed to epitaxially crystallize the Ge bottom interface and high resistivity Ge layer.
摘要翻译：提供了一种用于制造具有埋置的高电阻率锗（Ge）层的液相外延（LPE）绝缘体锗绝缘体（GOI）光电二极管的器件和相关方法。该方法提供硅（Si）衬底，并且形成具有Si种子存取区域的覆盖Si衬底的底部绝缘体。然后，形成具有n +掺杂（n +）台面，p +掺杂（p +）Ge底部绝缘体界面和台面侧面界面的Ge P-I-N二极管，以及插入在p + Ge和n + Ge之间的高电阻率Ge层。在p + Ge侧面界面的区域上形成金属电极，形成覆盖n + Ge台面的透明电极。在一个方面，该方法沉积覆盖高电阻率Ge层的氮化硅层临时盖，并进行退火以使Ge底界面和高电阻率Ge层外延结晶。

9. 发明申请

US20070141744A1 Method of fabricating a low, dark-current germanium-on-silicon pin photo detector 有权
标题翻译：制造低，暗电流硅 - 硅引脚光电探测器的方法
公开(公告)号：US20070141744A1
公开(公告)日：2007-06-21
申请号：US11312967
申请日：2005-12-19
申请人： Jong-Jan Lee , Douglas Tweet , Jer-Shen Maa , Sheng Hsu
发明人： Jong-Jan Lee , Douglas Tweet , Jer-Shen Maa , Sheng Hsu
IPC分类号： H01L21/00
CPC分类号： H01L31/105 , H01L31/1808 , H01L31/1864 , Y02E10/50 , Y02P70/521 , Y10S438/933
摘要： A method of fabricating a low, dark-current germanium-on-silicon PIN photo detector includes preparing a P-type silicon wafer; implanting the P-type silicon wafer with boron ions; activating the boron ions to form a P+ region on the silicon wafer; forming a boron-doped germanium layer on the P+ silicon surface; depositing an intrinsic germanium layer on the born-doped germanium layer; cyclic annealing, including a relatively high temperature first anneal step and a relatively low temperature second anneal step; repeating the first and second anneal steps for about twenty cycles, thereby forcing crystal defects to the P+ germanium layer; implanting ions in the surface of germanium layer to form an N+ germanium surface layer and a PIN diode; activating the N+ germanium surface layer by thermal anneal; and completing device according to known techniques to form a low dark-current germanium-on-silicon PIN photodetector.
摘要翻译：制造低，暗电流锗硅PIN光检测器的方法包括制备P型硅晶片; 用硼离子注入P型硅晶片; 激活硼离子以在硅晶片上形成P +区; 在P +硅表面上形成硼掺杂锗层; 在天然掺杂锗层上沉积本征锗层; 循环退火，包括相对高温的第一退火步骤和相对低温的第二退火步骤; 重复第一和第二退火步骤约20个循环，由此迫使晶体缺陷到P +锗层; 在锗层表面注入离子以形成N +锗表面层和PIN二极管; 通过热退火激活N +锗表面层; 并根据已知技术完成器件以形成低暗电流锗硅PIN光电探测器。

10. 发明申请

US20070001163A1 Floating body germanium phototransistor 有权
标题翻译：浮体锗光电晶体管
公开(公告)号：US20070001163A1
公开(公告)日：2007-01-04
申请号：US11174035
申请日：2005-07-01
申请人： Jong-Jan Lee , Sheng Hsu , Jer-Shen Maa , Douglas Tweet
发明人： Jong-Jan Lee , Sheng Hsu , Jer-Shen Maa , Douglas Tweet
IPC分类号： H01L31/00
CPC分类号： H01L31/1136 , H01L31/028 , H01L31/1808 , Y02E10/547
摘要： A floating body germanium (Ge) phototransistor and associated fabrication process are presented. The method includes: providing a silicon (Si) substrate; selectively forming an insulator layer overlying the Si substrate; forming an epitaxial Ge layer overlying the insulator layer using a liquid phase epitaxy (LPE) process; forming a channel region in the Ge layer; forming a gate dielectric, gate electrode, and gate spacers overlying the channel region; and, forming source/drain regions in the Ge layer. The LPE process involves encapsulating the Ge with materials having a melting temperature greater than a first temperature, and melting the Ge using a temperature lower than the first temperature. The LPE process includes: forming a dielectric layer overlying deposited Ge; melting the Ge; and, in response to cooling the Ge, laterally propagating an epitaxial growth front into the Ge from an underlying Si substrate surface.
摘要翻译：提出了一种浮体锗（Ge）光电晶体管及其制造工艺。该方法包括：提供硅（Si）衬底; 选择性地形成覆盖Si衬底的绝缘体层; 使用液相外延（LPE）工艺形成覆盖绝缘体层的外延Ge层; 在Ge层中形成沟道区; 形成覆盖所述沟道区的栅极电介质，栅电极和栅极间隔; 并且在Ge层中形成源/漏区。 LPE工艺包括用具有大于第一温度的熔化温度的材料包封Ge，并且使用低于第一温度的温度来熔化Ge。 LPE工艺包括：形成覆盖沉积Ge的介电层; 融化Ge; 并且响应于冷却Ge，将外延生长前沿从下面的Si衬底表面横向传播到Ge中。

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