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1. 发明授权

US09159732B2 Semiconductor device with buried gate and method for fabricating the same 有权
标题翻译：具有埋栅的半导体器件及其制造方法
公开(公告)号：US09159732B2
公开(公告)日：2015-10-13
申请号：US13553307
申请日：2012-07-19
申请人： Jong-Han Shin , Jum-Yong Park
发明人： Jong-Han Shin , Jum-Yong Park
IPC分类号： H01L29/66 , H01L27/108 , H01L29/423
CPC分类号： H01L27/10876 , H01L27/10855 , H01L27/10888 , H01L29/4236
摘要： A method for fabricating a semiconductor device includes forming landing plugs over a substrate, forming a trench by etching the substrate between the landing plugs, forming a buried gate to partially fill the trench, forming a gap-fill layer to gap-fill an upper side of the buried gate, forming protruding portions of the landing plugs, and trimming the protruding portions of the landing plugs.
摘要翻译：一种用于制造半导体器件的方法包括在衬底上形成覆盖层，通过在层间塞之间蚀刻衬底形成沟槽，形成掩埋栅极以部分填充沟槽，形成间隙填充层以间隙填充上侧，形成所述着陆塞的突出部分，以及修剪所述着陆塞的突出部分。

2. 发明授权

US09257436B2 Semiconductor device with buried gates and fabrication method thereof 有权
标题翻译：具有埋栅的半导体器件及其制造方法
公开(公告)号：US09257436B2
公开(公告)日：2016-02-09
申请号：US13325552
申请日：2011-12-14
申请人： Jong-Han Shin
发明人： Jong-Han Shin
IPC分类号： H01L21/336 , H01L27/108 , H01L29/423
CPC分类号： H01L29/4236 , H01L27/1052 , H01L27/10873 , H01L27/10876 , H01L27/10888 , H01L27/10894 , H01L29/42352 , H01L29/42356
摘要： A semiconductor device includes a substrate having a cell region and a peripheral region, a buried gate formed over the substrate of the cell region, a peripheral gate formed over the substrate of the peripheral region and comprising a conductive layer, an inter-layer dielectric layer that covers the substrate, and a peripheral bit line formed inside the inter-layer dielectric layer and contacting the conductive layer.
摘要翻译：半导体器件包括具有单元区域和外围区域的衬底，形成在单元区域的衬底上的掩埋栅极，形成在周边区域的衬底上的外围栅极，并且包括导电层，层间电介质层覆盖衬底以及形成在层间电介质层内部并与导电层接触的外围位线。

3. 发明申请

US20110156262A1 SEMICONDUCTOR DEVICE WITH BURIED GATE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：具有开口门的半导体器件及其制造方法
公开(公告)号：US20110156262A1
公开(公告)日：2011-06-30
申请号：US12827385
申请日：2010-06-30
申请人： Jong-Han Shin , Jum-Yong Park
发明人： Jong-Han Shin , Jum-Yong Park
IPC分类号： H01L29/41 , H01L21/28
CPC分类号： H01L27/10876 , H01L27/10855 , H01L27/10888 , H01L29/4236
摘要： A method for fabricating a semiconductor device includes forming landing plugs over a substrate, forming a trench by etching the substrate between the landing plugs, forming a buried gate to partially fill the trench, forming a gap-fill layer to gap-fill an upper side of the buried gate, forming protruding portions of the landing plugs, and trimming the protruding portions of the landing plugs.
摘要翻译：一种用于制造半导体器件的方法包括在衬底上形成覆盖层，通过在层间塞之间蚀刻衬底形成沟槽，形成掩埋栅极以部分填充沟槽，形成间隙填充层以间隙填充上侧，形成所述着陆塞的突出部分，以及修剪所述着陆塞的突出部分。

4. 发明申请

US20090117739A1 METHOD FOR FORMING PATTERN IN SEMICONDUCTOR DEVICE 失效
标题翻译：在半导体器件中形成图案的方法
公开(公告)号：US20090117739A1
公开(公告)日：2009-05-07
申请号：US11965582
申请日：2007-12-27
申请人： Jong-Han Shin , Hyung-Soon Park , Cheol-Hwi Ryu , Jum-Yong Park , Sung-Jun Kim
发明人： Jong-Han Shin , Hyung-Soon Park , Cheol-Hwi Ryu , Jum-Yong Park , Sung-Jun Kim
IPC分类号： H01L21/306
CPC分类号： H01L21/0337 , H01L21/0334 , H01L27/105 , H01L27/1052 , H01L27/10894
摘要： A method for forming a pattern in a semiconductor device includes forming an etch-target layer over a substrate, wherein the substrate includes a first region having a smaller pattern than the first region, forming a sacrificial layer and a passivation layer over the etch-target layer, etching the passivation layer and the sacrificial layer to form stack structures including a sacrificial pattern and a passivation pattern, forming spacers over sidewalls of the stack structures, forming a mask pattern covering the second region, removing a portion of the passivation pattern in the first region exposed by the mask pattern to expose a portion of the sacrificial pattern in the first region, removing the exposed portion of the sacrificial pattern in the first region, and etching the etch-target layer to form an etch-target pattern using the spacers in the first and second regions and the stack structure formed between the spacers in the second region.
摘要翻译：在半导体器件中形成图案的方法包括在衬底上形成蚀刻目标层，其中衬底包括具有比第一区域更小的图案的第一区域，在蚀刻靶上形成牺牲层和钝化层蚀刻钝化层和牺牲层以形成包括牺牲图案和钝化图案的堆叠结构，在堆叠结构的侧壁上形成间隔物，形成覆盖第二区域的掩模图案，从而去除钝化层的一部分第一区域由掩模图案曝光以暴露第一区域中的牺牲图案的一部分，去除第一区域中的牺牲图案的暴露部分，以及蚀刻蚀刻目标层，以使用间隔物在第一区域和第二区域中形成叠层结构，并且在第二区域中形成在间隔物之间。

5. 发明授权

US08623727B2 Method for fabricating semiconductor device with buried gate 失效
标题翻译：具有埋栅的半导体器件的制造方法
公开(公告)号：US08623727B2
公开(公告)日：2014-01-07
申请号：US13326810
申请日：2011-12-15
申请人： Jong-Han Shin , Kyung-Bo Kim
发明人： Jong-Han Shin , Kyung-Bo Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/10876 , H01L23/485 , H01L27/10855 , H01L27/10885 , H01L29/1037 , H01L29/4236 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating a semiconductor device includes forming a hard mask pattern over a substrate, forming an isolation layer for defining an active region by using the hard mask pattern, forming a buried gate in and across the active region and the isolation layer over the substrate, forming an inter-layer dielectric layer over the substrate, forming a storage node contact hole that exposes the hard mask pattern by selectively etching the inter-layer dielectric layer, extending the storage node contact hole to expose the active region by removing the hard mask pattern exposed under the storage node contact hole, and forming a storage node contact plug that fills the extended storage node contact hole.
摘要翻译：一种用于制造半导体器件的方法包括在衬底上形成硬掩模图案，通过使用硬掩模图案形成用于限定有源区的隔离层，在有源区和跨衬底上的隔离层中形成掩埋栅极在衬底上形成层间电介质层，形成存储节点接触孔，通过选择性地蚀刻层间电介质层来暴露硬掩模图案，通过去除硬掩模来延伸存储节点接触孔以暴露有源区在存储节点接触孔下暴露的图案，并形成填充扩展存储节点接触孔的存储节点接触插塞。

6. 发明授权

US08404543B2 Method for fabricating semiconductor device with buried gate 有权
标题翻译：具有埋栅的半导体器件的制造方法
公开(公告)号：US08404543B2
公开(公告)日：2013-03-26
申请号：US12623719
申请日：2009-11-23
申请人： Jong-Han Shin , Cheol-Hwi Ryu , Sung-Jun Kim
发明人： Jong-Han Shin , Cheol-Hwi Ryu , Sung-Jun Kim
IPC分类号： H01L21/336
CPC分类号： H01L21/76897 , H01L21/743 , H01L27/10876 , H01L29/4236
摘要： A method for fabricating a semiconductor device with a buried gate includes: etching a substrate to form a plurality of trenches; forming a plurality of buried gates that fill lower portions of the trenches; forming a plurality of sealing layers that gap-fill upper portions of the trenches and have protrusions higher than a top surface of the substrate; forming an inter-layer insulation layer over the whole surface of the substrate including the sealing layers; and etching the inter-layer insulation layer to form a contact hole that is aligned with a space between the protrusions of the sealing layers.
摘要翻译：一种用于制造具有掩埋栅极的半导体器件的方法包括：蚀刻衬底以形成多个沟槽; 形成填充沟槽下部的多个掩埋栅极; 形成多个密封层，所述多个密封层间隙地填充所述沟槽的上部并且具有高于所述衬底的顶表面的突出部; 在包括所述密封层的所述基板的整个表面上形成层间绝缘层; 并且蚀刻层间绝缘层以形成与密封层的突起之间的空间对准的接触孔。

7. 发明授权

US07994056B2 Method for forming pattern in semiconductor device 失效
标题翻译：在半导体器件中形成图案的方法
公开(公告)号：US07994056B2
公开(公告)日：2011-08-09
申请号：US11965582
申请日：2007-12-27
申请人： Jong-Han Shin , Hyung-Soon Park , Cheol-Hwi Ryu , Jum-Yong Park , Sung-Jun Kim
发明人： Jong-Han Shin , Hyung-Soon Park , Cheol-Hwi Ryu , Jum-Yong Park , Sung-Jun Kim
IPC分类号： H01L21/301 , H01L21/461 , H01L21/311 , C03C15/00 , C03C25/68 , C23F1/00
CPC分类号： H01L21/0337 , H01L21/0334 , H01L27/105 , H01L27/1052 , H01L27/10894
摘要： A method for forming a pattern in a semiconductor device includes forming an etch-target layer over a substrate, wherein the substrate includes a first region having a smaller pattern than the first region, forming a sacrificial layer and a passivation layer over the etch-target layer, etching the passivation layer and the sacrificial layer to form stack structures including a sacrificial pattern and a passivation pattern, forming spacers over sidewalls of the stack structures, forming a mask pattern covering the second region, removing a portion of the passivation pattern in the first region exposed by the mask pattern to expose a portion of the sacrificial pattern in the first region, removing the exposed portion of the sacrificial pattern in the first region, and etching the etch-target layer to form an etch-target pattern using the spacers in the first and second regions and the stack structure formed between the spacers in the second region.
摘要翻译：在半导体器件中形成图案的方法包括在衬底上形成蚀刻目标层，其中衬底包括具有比第一区域更小的图案的第一区域，在蚀刻靶上形成牺牲层和钝化层蚀刻钝化层和牺牲层以形成包括牺牲图案和钝化图案的堆叠结构，在堆叠结构的侧壁上形成间隔物，形成覆盖第二区域的掩模图案，从而去除钝化层中的钝化图案的一部分第一区域由掩模图案曝光以暴露第一区域中的牺牲图案的一部分，去除第一区域中的牺牲图案的暴露部分，以及蚀刻蚀刻目标层，以使用间隔物在第一区域和第二区域中形成叠层结构，并且在第二区域中形成在间隔物之间。

8. 发明申请

US20100237405A1 SEMICONDUCTOR DEVICE WITH VERTICAL TRANSISTOR AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：具有垂直晶体管的半导体器件及其制造方法
公开(公告)号：US20100237405A1
公开(公告)日：2010-09-23
申请号：US12493176
申请日：2009-06-27
申请人： Jong-Han Shin
发明人： Jong-Han Shin
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66666 , H01L27/10876 , H01L29/7827
摘要： A semiconductor device with a vertical transistor includes a plurality of active pillars, a plurality of vertical gates surrounding sidewalls of the active pillars; a plurality of word lines having exposed sidewalls whose surfaces are higher than the active pillars and connecting the adjacent vertical gates together, and a plurality of spacers surrounding the exposed sidewalls of the word lines over the vertical gates.
摘要翻译：具有垂直晶体管的半导体器件包括多个有源支柱，围绕有源支柱侧壁的多个垂直栅极; 多个字线具有暴露的侧壁，其表面高于有源柱并将相邻的垂直栅极连接在一起，以及围绕垂直栅极的字线暴露的侧壁围绕的多个间隔物。

9. 发明授权

US5633989A Artificial neural circuit using pulse coding 失效
标题翻译：人工神经电路采用脉冲编码
公开(公告)号：US5633989A
公开(公告)日：1997-05-27
申请号：US298286
申请日：1994-08-31
申请人： Jong-Han Shin , Jong-Geon Shin
发明人： Jong-Han Shin , Jong-Geon Shin
IPC分类号： G06G7/60 , G06F15/18 , G06N3/06 , G06N3/063
CPC分类号： G06N3/0635
摘要： Disclosed is an artificial neural circuit using a pulse coding such as a stochastic pulse coding or a noise feedback pulse coding, the circuit comprising a synapse circuit section for producing and absorbing a current signal proportional to a weight voltage signal upon an externally applied current signal being supplied; a neuron body circuit section for spacio-temporally integrating output signal of the synapse circuit section to produce an analog voltage signal; and an axon hillock circuit for converting the analog voltage signal into a pulse train using a predetermined reference signal. The synapse circuit section including a first input terminal for receiving a first reference voltage; a second input terminal for receiving a second reference voltage; a third input terminal for receiving a third reference voltage; a fourth terminal for receiving the weight voltage signal; a first transistor having drain and source connected to the first reference voltage and a junction point, respectively, and gate connected to the fourth input terminal; a second transistor having drain and source connected to the junction point and the second input terminal, respectively, and gate connected to the third input terminal; and a third transistor having drain and source connected respectively to the junction point and an output terminal of the synapse circuit section, and gate connected to an input terminal for receiving the externally applied current signal.
摘要翻译：公开了使用诸如随机脉冲编码或噪声反馈脉冲编码的脉冲编码的人造神经电路，该电路包括突触电路部分，用于在外部施加的电流信号时产生和吸收与重量电压信号成比例的电流信号供应; 用于对突触电路部分的输出信号进行时空积分以产生模拟电压信号的神经元体电路部分; 以及用于使用预定参考信号将模拟电压信号转换成脉冲串的轴突小丘电路。所述突触电路部分包括用于接收第一参考电压的第一输入端; 用于接收第二参考电压的第二输入端; 用于接收第三参考电压的第三输入端; 用于接收重量电压信号的第四端子; 第一晶体管，其漏极和源极分别连接到第一参考电压和接合点，栅极连接到第四输入端; 第二晶体管，其漏极和源极分别连接到所述连接点和所述第二输入端子，并且栅极连接到所述第三输入端子; 以及第三晶体管，其漏极和源极分别连接到所述连接点和所述突触电路部分的输出端子，并且栅极连接到用于接收外部施加的电流信号的输入端子。

10. 发明授权

US08492257B2 Semiconductor device with vertical transistor and method for fabricating the same 有权
标题翻译：具有垂直晶体管的半导体器件及其制造方法
公开(公告)号：US08492257B2
公开(公告)日：2013-07-23
申请号：US13339085
申请日：2011-12-28
申请人： Jong-Han Shin
发明人： Jong-Han Shin
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L29/66666 , H01L27/10876 , H01L29/7827
摘要： A semiconductor device with a vertical transistor includes a plurality of active pillars; a plurality of vertical gates surrounding sidewalls of the active pillars; a plurality of word lines having exposed sidewalls whose surfaces are higher than the active pillars and connecting the adjacent vertical gates together; and a plurality of spacers surrounding the exposed sidewalls of the word lines over the vertical gates.
摘要翻译：具有垂直晶体管的半导体器件包括多个有源支柱; 围绕所述活动柱的侧壁的多个垂直门; 多个字线具有暴露的侧壁，其表面高于有源柱并将相邻的垂直栅极连接在一起; 以及围绕垂直门上的字线的暴露的侧壁包围的多个间隔物。

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