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1. 发明申请

US20090201727A1 READ METHOD OF MEMORY DEVICE 有权
标题翻译：读存储器件的方法
公开(公告)号：US20090201727A1
公开(公告)日：2009-08-13
申请号：US12422870
申请日：2009-04-13
申请人： Jong Hyun WANG , Jun Seop CHUNG , Seok Jin JOO
发明人： Jong Hyun WANG , Jun Seop CHUNG , Seok Jin JOO
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06
CPC分类号： G11C16/28 , G06F11/1072 , G11C11/5642 , G11C29/00
摘要： A read method of a memory device including a MLC includes the steps of performing a data read operation according to a first read command; determining whether error correction of the read data is possible; if, as a result of the determination, error correction is difficult, performing a data read operation according to a second read command; determining whether error correction of read data is possible according to the second read command; and if, as a result of the determination, error correction is difficult, performing a data read operation according to a Nth (N≧3, N is an integer) read command.
摘要翻译：包括MLC的存储器件的读取方法包括以下步骤：根据第一读取命令执行数据读取操作; 确定读取数据的纠错是否可行; 如果作为确定的结果，难以进行纠错，则根据第二读取命令执行数据读取操作; 根据第二读取命令确定读取数据的纠错是否可行; 并且如果作为确定的结果，难以进行纠错，则根据Nth（N> = 3，N是整数）读取命令执行数据读取操作。

2. 发明申请

US20080205136A1 READ METHOD OF MEMORY DEVICE 有权
标题翻译：读存储器件的方法
公开(公告)号：US20080205136A1
公开(公告)日：2008-08-28
申请号：US11771963
申请日：2007-06-29
申请人： Jong Hyun WANG , Jun Seop Chung , Seok Jin Joo
发明人： Jong Hyun WANG , Jun Seop Chung , Seok Jin Joo
IPC分类号： G11C11/34
CPC分类号： G11C16/28 , G06F11/1072 , G11C11/5642 , G11C29/00
摘要： A read method of a memory device including a MLC includes the steps of performing a data read operation according to a first read command; determining whether error correction of the read data is possible; if, as a result of the determination, error correction is difficult, performing a data read operation according to a second read command; determining whether error correction of read data is possible according to the second read command; and if, as a result of the determination, error correction is difficult, performing a data read operation according to a Nth (N≧3, N is an integer) read command.
摘要翻译：包括MLC的存储器件的读取方法包括以下步骤：根据第一读取命令执行数据读取操作; 确定读取数据的纠错是否可行; 如果作为确定的结果，难以进行纠错，则根据第二读取命令执行数据读取操作; 根据第二读取命令确定读取数据的纠错是否可行; 如果作为确定的结果，难以进行纠错，则根据N（N> = 3，N是整数）读取命令执行数据读取操作。

3. 发明申请

US20100284224A1 FLASH MEMORY DEVICE AND ERASE METHOD USING THE SAME 有权
标题翻译：闪存存储器件和使用其的擦除方法
公开(公告)号：US20100284224A1
公开(公告)日：2010-11-11
申请号：US12839261
申请日：2010-07-19
申请人： Jong Hyun WANG
发明人： Jong Hyun WANG
IPC分类号： G11C16/04
CPC分类号： G11C16/12 , G11C16/0483
摘要： A flash memory device includes a plurality of memory blocks and a plurality of block selection circuits corresponding to the plurality of memory blocks. All of the block selection circuits are sequentially operated in response to block control signals, or two or more of the block selection circuits are operated in response to the block control signals.
摘要翻译：闪速存储器件包括多个存储器块和对应于多个存储器块的多个块选择电路。响应于块控制信号，顺序地操作所有块选择电路，或者响应于块控制信号操作两个或多个块选择电路。

4. 发明申请

US20090172482A1 METHODS FOR PERFORMING FAIL TEST, BLOCK MANAGEMENT, ERASING AND PROGRAMMING IN A NONVOLATILE MEMORY DEVICE 失效
标题翻译：在非易失性存储器件中执行失败测试，块管理，擦除和编程的方法
公开(公告)号：US20090172482A1
公开(公告)日：2009-07-02
申请号：US12130994
申请日：2008-05-30
申请人： Jong Hyun WANG , Chae Kyu Jang , Se Chun Park
发明人： Jong Hyun WANG , Chae Kyu Jang , Se Chun Park
IPC分类号： G11C29/08 , G06F11/26
CPC分类号： G11C29/44 , G11C29/82 , G11C2029/1208 , G11C2029/4402
摘要： Methods for performing a fail test, block management, erase operations and program operations are used in a nonvolatile memory device having a block switch devoid of a fuse and a PMOS transistor. A method for performing a fail test in a nonvolatile memory device includes performing a fail test for a memory cell block; storing good block information in a block information store associated with the corresponding block when the memory cell block is a good block; and repeating the performing and storing steps for all memory cell blocks.
摘要翻译：在具有不具有熔丝和PMOS晶体管的块开关的非易失性存储器件中使用用于执行故障测试，块管理，擦除操作和编程操作的方法。用于在非易失性存储器件中执行故障测试的方法包括执行存储器单元块的故障测试; 当所述存储器单元块是良好块时，将良好块信息存储在与相应块相关联的块信息存储器中; 并重复执行和存储所有存储单元块的步骤。

5. 发明申请

US20100008138A1 METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE 有权
标题翻译：编程非易失性存储器件的方法
公开(公告)号：US20100008138A1
公开(公告)日：2010-01-14
申请号：US12361217
申请日：2009-01-28
申请人： Jong Hyun WANG
发明人： Jong Hyun WANG
IPC分类号： G11C16/00 , G11C16/06
CPC分类号： G11C16/10 , G11C16/30
摘要： According to an aspect of a method of programming a nonvolatile memory device, a first program operation command is input, and a program operation is executed according to a program start voltage stored in a program start voltage storage unit. Here, a program voltage, which is applied at a time point at which a memory cell programmed higher than a verify voltage while the program operation is performed occurs for the first time, is updated to a program start voltage.
摘要翻译：根据非易失性存储器件编程方法的一个方面，输入第一程序操作命令，并且根据存储在程序启动电压存储单元中的程序启动电压来执行程序操作。这里，在第一次进行编程操作时，在编程高于验证电压的存储单元的时间点应用的编程电压被更新为程序启动电压。

6. 发明申请

US20080175064A1 METHOD OF PROGRAMMING DATA IN A FLASH MEMORY DEVICE 失效
标题翻译：在闪速存储器件中编程数据的方法
公开(公告)号：US20080175064A1
公开(公告)日：2008-07-24
申请号：US11771792
申请日：2007-06-29
申请人： Jong Hyun WANG
发明人： Jong Hyun WANG
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454 , G11C2211/5621
摘要： A method of programming a most significant bit (MSB) data to a multi-level cell in a flash memory device including first and second cells includes performing a first program operation on the first cell using a first program voltage, the first cell being in a first state when the first program operation is performed on the first cell; if the first cell is determined to be in a second state after the first program operation, defining a second program voltage based on a result of comparing the first program voltage with a start voltage predefined for a second program operation; and performing the second program operation on the second cell using the second program voltage that has been defined according to a result of the comparison between the first program voltage and the start voltage.
摘要翻译：一种将最高有效位（MSB）数据编程到包括第一和第二单元的闪存器件中的多电平单元的方法包括使用第一编程电压对第一单元执行第一编程操作，第一单元位于当在第一单元上执行第一编程操作时的第一状态; 如果在第一编程操作之后确定第一单元处于第二状态，则基于将第一编程电压与为第二编程操作预定的启动电压进行比较的结果来定义第二编程电压; 以及使用根据第一编程电压和起始电压之间的比较结果定义的第二编程电压对第二单元执行第二编程操作。

7. 发明申请

US20120306470A1 DOWN-CONVERTING VOLTAGE GENERATING CIRCUIT 有权
标题翻译：下变频电压发生电路
公开(公告)号：US20120306470A1
公开(公告)日：2012-12-06
申请号：US13339034
申请日：2011-12-28
申请人： Chae Kyu JANG , Jong Hyun WANG , Sang Don LEE
发明人： Chae Kyu JANG , Jong Hyun WANG , Sang Don LEE
IPC分类号： G05F3/08
CPC分类号： G05F1/56
摘要： A down-converting voltage generating circuit includes a reference voltage providing unit, an initial setting unit, a driving unit, and a driving force control unit. The reference voltage providing unit provides a reference voltage to a first node. The initial setting unit drops a voltage level of the first node to substantially a level of a ground voltage when an initial setting signal is activated. The driving unit drives a down-converted voltage derived from an external voltage in response to the voltage level of the first node. The driving force control unit is connected to the driving unit, and controls a driving force for driving the down-converted voltage of the driving unit in response to the initial setting signal.
摘要翻译：下变频电压发生电路包括基准电压提供单元，初始设定单元，驱动单元和驱动力控制单元。参考电压提供单元向第一节点提供参考电压。当初始设置信号被激活时，初始设置单元将第一节点的电压电平降低到接地电压的大致水平。驱动单元驱动响应于第一节点的电压电平从外部电压导出的下变频电压。驱动力控制单元连接到驱动单元，并且响应于初始设置信号控制用于驱动驱动单元的下变频电压的驱动力。

8. 发明申请

US20100302830A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20100302830A1
公开(公告)日：2010-12-02
申请号：US12650091
申请日：2009-12-30
申请人： Jong Hyun WANG
发明人： Jong Hyun WANG
IPC分类号： G11C5/06 , G11C7/00
CPC分类号： G11C5/063
摘要： A semiconductor memory device having a number of chips, each of the chips including a chip enable detection unit configured to simultaneously output a first signal and a second signal in response to a chip enable signal, a chip operation detection unit configured to output an operation state signal in response to the first signal, and an internal circuit configured to operate in response to a power source voltage and a control signal in response to the second signal being received.
摘要翻译：一种具有多个芯片的半导体存储器件，每个芯片包括芯片使能检测单元，其被配置为响应于芯片使能信号同时输出第一信号和第二信号;芯片操作检测单元，被配置为输出操作状态响应于第一信号的信号，以及被配置为响应于接收到的第二信号而响应于电源电压和控制信号而工作的内部电路。

9. 发明申请

US20100008145A1 METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE 有权
标题翻译：编程非易失性存储器件的方法
公开(公告)号：US20100008145A1
公开(公告)日：2010-01-14
申请号：US12361231
申请日：2009-01-28
申请人： Jong Hyun WANG
发明人： Jong Hyun WANG
IPC分类号： G11C16/06
CPC分类号： G11C16/10
摘要： A method of programming nonvolatile memory devices. According to one programming method program operation is performed by applying a dummy program pulse having a pulse width wider than a pulse width of a program start pulse. A program operation is performed by applying the program start pulse. It is then verified whether a program has been completed as a result of the program operation. According to another programming method, a program operation is performed by applying a step-shaped dummy program pulse, which has a second pulse width and has been increased by a second step voltage. A program operation is performed by applying a program pulse having a first step voltage and a first pulse width. It is then verified whether a program has been completed as a result of the program operation.
摘要翻译：一种编程非易失性存储器件的方法。根据一种编程方法，通过应用具有比编程开始脉冲的脉冲宽度更宽的脉冲宽度的虚拟编程脉冲来执行程序操作。通过应用程序启动脉冲来执行编程操作。然后，由程序运行结果验证程序是否已经完成。根据另一编程方法，通过应用具有第二脉冲宽度并已经增加了第二阶梯电压的阶梯形虚拟编程脉冲来执行编程操作。通过施加具有第一阶跃电压和第一脉冲宽度的编程脉冲来执行编程操作。然后，由程序运行结果验证程序是否已经完成。

10. 发明申请

US20080158953A1 NON-VOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING A MULTI LEVEL CELL IN THE SAME 有权
标题翻译：非易失性记忆体装置及其编程多级细胞的方法
公开(公告)号：US20080158953A1
公开(公告)日：2008-07-03
申请号：US11765518
申请日：2007-06-20
申请人： Jong Hyun WANG , Se Chun Park , Seong Hun Park
发明人： Jong Hyun WANG , Se Chun Park , Seong Hun Park
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C2211/5642
摘要： A non-volatile memory device of the present invention includes a page buffer having a bit line selecting circuit, a first register, a second register, a data comparing circuit, a first bit line voltage controller, and a second bit line voltage controller. The bit line selecting circuit couples selectively a certain bit line to a sensing node. The first register and the second register store given data. The data comparing circuit compares the data stored in the first register with the data stored in the second register, and transmits the comparison result to the sensing node. The first bit line voltage controller applies a voltage of low level to the bit line in accordance with a voltage level of the data stored in the first register. The second bit line voltage controller applies a selected first voltage of high level to the bit line in accordance with the data stored in the second register.
摘要翻译：本发明的非易失性存储器件包括具有位线选择电路，第一寄存器，第二寄存器，数据比较电路，第一位线电压控制器和第二位线电压控制器的页缓冲器。位线选择电路将特定位线选择性地耦合到感测节点。第一个寄存器和第二个寄存器存储给定的数据。数据比较电路将存储在第一寄存器中的数据与存储在第二寄存器中的数据进行比较，并将比较结果发送到感测节点。第一位线电压控制器根据存储在第一寄存器中的数据的电压电平向位线施加低电平的电压。第二位线电压控制器根据存储在第二寄存器中的数据将所选择的高电平的第一电压施加到位线。

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