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1. 发明授权

US06449692B1 Microprocessor circuits, systems, and methods with combined on-chip pixel and non-pixel cache structure 有权
标题翻译：具有组合片上像素和非像素缓存结构的微处理器电路，系统和方法
公开(公告)号：US06449692B1
公开(公告)日：2002-09-10
申请号：US09212034
申请日：1998-12-15
申请人： Steven D. Krueger , Jonathan H. Shiell , Ian Chen
发明人： Steven D. Krueger , Jonathan H. Shiell , Ian Chen
IPC分类号： G06F1208
CPC分类号： G06F12/0897 , G06F3/14 , G06F12/0848 , G06F12/0875 , G09G2360/121
摘要： A computer system (8) comprising a central processing unit (12) and a memory hierarchy. The memory hierarchy comprises a first cache memory (16) and a second cache memory (26). The first cache memory is operable to store non-pixel-information, wherein the non-pixel information is accessible for processing by the central processing unit. The second cache memory is higher in the memory hierarchy than the first cache memory, and has a number of storage locations operable to store non-pixel information (26b) and pixel data (26a). Lastly, the computer system comprises cache control circuitry (24) for dynamically apportioning the number of storage locations such that a first group of the storage locations are for storing non-pixel information and such that a second group of the storage locations are for storing pixel data.
摘要翻译：一种包括中央处理单元（12）和存储器层级的计算机系统（8）。存储器层级包括第一高速缓存存储器（16）和第二高速缓存存储器（26）。第一高速缓冲存储器可操作以存储非像素信息，其中非像素信息可被中央处理单元处理。第二高速缓冲存储器在存储器层级中高于第一高速缓冲存储器，并且具有可操作用于存储非像素信息（26b）和像素数据（26a）的多个存储位置。最后，计算机系统包括高速缓存控制电路（24），用于动态分配存储位置的数量，使得第一组存储位置用于存储非像素信息，并且第二组存储位置用于存储像素数据。

2. 发明授权

US6065125A SMM power management circuits, systems, and methods 失效
标题翻译： SMM电源管理电路，系统和方法
公开(公告)号：US6065125A
公开(公告)日：2000-05-16
申请号：US741876
申请日：1996-10-30
申请人： Jonathan H. Shiell , Ian Chen
发明人： Jonathan H. Shiell , Ian Chen
IPC分类号： G06F1/32 , G06F13/14
CPC分类号： G06F1/3203
摘要： Circuits, systems, and methods relating to operating a computer system operable in a system manager mode (24). The method includes various steps. The first step (34) occurs during operation of the computer system (10) at a time other than start-up, and receives user power management data from a user of the computer system. The second step (38) stores the user power management data in memory space (30) accessible by the system management mode. The third step (40) accesses the user power management data from the memory space. Finally, the fourth step (42) controls at least one peripheral (14, 16, 18, 20) of the computer system in response to the accessed user power management data.
摘要翻译：与操作以系统管理器模式操作的计算机系统相关的电路，系统和方法（24）。该方法包括各种步骤。第一步骤（34）在计算机系统（10）的操作期间发生在除了启动之外的时间，并且从计算机系统的用户接收用户电力管理数据。第二步骤（38）将用户电源管理数据存储在可由系统管理模式访问的存储器空间（30）中。第三步（40）从存储器空间访问用户电源管理数据。最后，第四步骤（42）响应于所访问的用户电源管理数据来控制计算机系统的至少一个外围设备（14,16,18,20）。

3. 发明授权

US06032225A Microprocessor system with burstable, non-cacheable memory access support 失效
标题翻译：微处理器系统具有可突发，不可缓存的内存访问支持
公开(公告)号：US06032225A
公开(公告)日：2000-02-29
申请号：US769194
申请日：1996-12-18
申请人： Jonathan H. Shiell , Ashwini K. Nanda , Ian Chen , Steven D. Krueger
发明人： Jonathan H. Shiell , Ashwini K. Nanda , Ian Chen , Steven D. Krueger
IPC分类号： G06F12/08 , G06F13/28 , G06F12/00
CPC分类号： G06F13/28 , G06F12/0888
摘要： A microprocessor-based system (2) is disclosed, based on an x86-architecture microprocessor (5). The system includes a memory address space (30) and a input/output address space (40), where input/output operations are performed in an I/O mapped manner. According to a first embodiment of the invention, burstable access is performed to areas of the main memory (32) which are blocked from cache access, by the microprocessor (5) asserting the cache request signal (CACHE#) in combination with the control signal (M/IO#) indicating that an I/O operation is requested. The memory controller (10) interprets this combination as a burst request to the non-cacheable memory location (32), indicates the grant of burst access by asserting the cache acknowledge control signal (KEN#), and the burst memory access is then effected. According to a second embodiment of the invention, burst access to non-cacheable memory space (32) is acknowledged by the memory controller (60) by way of a burst acknowledge signal (BEN#) that is separate from the cache acknowledgment signal (KEN#).
摘要翻译：基于x86架构的微处理器（5）公开了一种基于微处理器的系统（2）。该系统包括存储器地址空间（30）和输入/输出地址空间（40），其中以I / O映射方式执行输入/输出操作。根据本发明的第一实施例，微处理器（5）结合控制信号来确定高速缓存请求信号（CACHE＃），对主存储器（32）的被高速缓存访问阻止的区域执行突发存取（M / IO＃），表示请求I / O操作。存储器控制器（10）将该组合解释为对非可缓存存储器位置（32）的突发请求，指示通过断言高速缓存确认控制信号（KEN＃）来准许突发存取，然后实现突发存储器访问。根据本发明的第二实施例，通过与高速缓存确认信号（KEN）分离的突发确认信号（BEN＃），由存储器控制器（60）确认对非可缓存存储器空间（32）的突发访问＃）。

4. 发明授权

US5950012A Single chip microprocessor circuits, systems, and methods for self-loading patch micro-operation codes and patch microinstruction codes 失效
标题翻译：单片微处理器电路，系统和方法，用于自动加载补丁微操作代码和补丁微指令代码
公开(公告)号：US5950012A
公开(公告)日：1999-09-07
申请号：US813770
申请日：1997-03-07
申请人： Jonathan H. Shiell , Ian Chen
发明人： Jonathan H. Shiell , Ian Chen
IPC分类号： G06F9/24 , G06F9/26 , G06F9/30 , G06F9/318 , G06F9/38 , G06F9/445
CPC分类号： G06F9/30087 , G06F8/64 , G06F8/65 , G06F8/66 , G06F9/24 , G06F9/268 , G06F9/30003 , G06F9/3004 , G06F9/30076 , G06F9/30145 , G06F9/3017 , G06F9/328 , G06F9/3802
摘要： In a method embodiment (34), the method operates a computer system (10) having a type of configuration and including a single integrated circuit microprocessor (24). The microprocessor operates in response to codes and has an instruction set. The method involves various steps, including determining (40) the type of the configuration. In response to the type of the configuration, the method selects (42) a set of patch codes from a plurality of sets of patch codes. The method also issues (54) a patch request instruction from the instruction set, and it stores (56) the selected set of patch codes to a memory space accessible by the microprocessor. Other circuits, systems, and methods are also disclosed and claimed
摘要翻译：在方法实施例（34）中，该方法操作具有一种类型的配置并包括单个集成电路微处理器（24）的计算机系统（10）。微处理器响应于代码进行操作并具有指令集。该方法涉及各种步骤，包括确定（40）配置的类型。响应于配置的类型，该方法从多组补丁码中选择（42）一组补丁码。该方法还发出（54）来自指令集的补丁请求指令，并且将所选择的补丁代码集合存储（56）到由微处理器可访问的存储器空间。还公开并要求保护其他电路，系统和方法

5. 发明授权

US5963721A Microprocessor system with capability for asynchronous bus transactions 失效
标题翻译：具有异步总线事务能力的微处理器系统
公开(公告)号：US5963721A
公开(公告)日：1999-10-05
申请号：US777322
申请日：1996-12-27
申请人： Jonathan H. Shiell , Ian Chen , Robert W. Milhaupt
发明人： Jonathan H. Shiell , Ian Chen , Robert W. Milhaupt
IPC分类号： G06F12/08 , G06F3/00
CPC分类号： G06F12/0811
摘要： A microprocessor-based data processing system (2) in which asynchronous bus transactions are performed is disclosed. The disclosed embodiments include one or more microprocessors (5) of the x86-architecture type, compatible with the P54C bus protocol, preferably Pentium-compatible microprocessors, as the central processing units (CPUs) of the system. A CPU (5.sub.r) requests an asynchronous bus transaction, in a first disclosed embodiment, by presenting a combination of control signals that is unused in conventional x86-architecture systems; the controller chipset (27) determines whether the transaction may be performed in an asynchronous manner, and later returns an acknowledge or non-acknowledge code to the requesting CPU (5.sub.r). The microprocessors (5) include certain pins, in this first embodiment, corresponding to conventional Pentium-compatible output pins but which now have receiver circuitry for receiving the acknowledge and non-acknowledge codes, along with the transaction identifier. If the transaction is accepted as asynchronous, the identifier is used to later identify the transaction when access is granted. A second disclosed embodiment provides an immediate indication of the acceptability of the requested transaction as of the asynchronous type, so that unacceptable transactions may be immediately processed in synchronous fashion. A third disclosed embodiment uses an additional terminal to indicate the acknowledge or non-acknowledge response.
摘要翻译：公开了一种其中执行异步总线事务的基于微处理器的数据处理系统（2）。所公开的实施例包括x86架构类型的一个或多个微处理器（5），与该系统的中央处理单元（CPU）的P54C总线协议（最好是Pentium兼容微处理器）兼容。在第一公开实施例中，CPU（5r）通过呈现在常规x86架构系统中未使用的控制信号的组合来请求异步总线事务; 控制器芯片组（27）确定是否可以以异步方式执行事务，并且稍后向请求CPU（5r）返回确认或非确认代码。微处理器（5）包括某些引脚，在该第一实施例中，对应于常规的奔腾兼容的输出引脚，但是现在具有用于接收确认和非确认代码的接收器电路以及事务标识符。如果事务被接受为异步，则当访问被授予时，该标识符用于稍后识别事务。第二个公开的实施例提供了所述异步类型所请求的交易的可接受性的即时指示，使得不可接受的交易可以以同步的方式被立即处理。第三个公开的实施例使用附加终端来指示确认或非确认响应。

6. 发明授权

US08957909B2 System and method for compensating for drift in a display of a user interface state 有权
标题翻译：用于补偿用户界面状态显示中漂移的系统和方法
公开(公告)号：US08957909B2
公开(公告)日：2015-02-17
申请号：US13165690
申请日：2011-06-21
申请人： Benjamin E. Joseph , Ian Chen
发明人： Benjamin E. Joseph , Ian Chen
IPC分类号： G09G5/00 , G09G5/08 , A63F9/24 , A63F13/00 , G06F3/038 , G06F3/0346
CPC分类号： G06F3/038 , G06F3/0346
摘要： A system, a non-transitory computer readable storage medium including instructions, and a method for adjusting a displayed user interface in accordance with a navigational state of a human interface device. For each measurement epoch, a base set of operations are performed, including: determining an unmodified user interface state in accordance with the navigational state, and generating current user interface data. Upon detecting an error introducing state, additional operations are performed, including: determining a modified user interface state; adjusting the current user interface data in accordance with the modified user interface state; and determining a user interface state error. Upon detecting an error compensating state, additional operations are performed, including: determining a compensation adjustment and adjusting the current user interface data and user interface state error in accordance with the compensation adjustment. The current user interface data enables a current user interface to be displayed.
摘要翻译：一种系统，包括指令的非暂时性计算机可读存储介质，以及根据人机界面装置的导航状态来调整显示的用户界面的方法。对于每个测量纪元，执行基本操作集合，包括：根据导航状态确定未修改的用户界面状态，以及生成当前用户界面数据。在检测到错误引入状态时，执行附加操作，包括：确定修改的用户界面状态; 根据修改的用户界面状态调整当前用户界面数据; 并确定用户界面状态错误。在检测到错误补偿状态时，执行附加操作，包括：根据补偿调整确定补偿调整并调整当前用户界面数据和用户界面状态错误。当前的用户界面数据可以显示当前的用户界面。

7. 发明授权

US08576169B2 System and method for determining an attitude of a device undergoing dynamic acceleration 失效
公开(公告)号：US08576169B2
公开(公告)日：2013-11-05
申请号：US12338991
申请日：2008-12-18
申请人： Kevin A. Shaw , Ian Chen
发明人： Kevin A. Shaw , Ian Chen
IPC分类号： G06F3/033
CPC分类号： G06F3/0346 , G06F3/017
摘要： A system and a method for determining an attitude of a device undergoing dynamic acceleration is presented. A first attitude measurement is calculated based on a magnetic field measurement received from a magnetometer of the device and a first acceleration measurement received from a first accelerometer of the device. A second attitude measurement is calculated based on the magnetic field measurement received from the magnetometer of the device and a second acceleration measurement received from a second accelerometer of the device. A correction factor is calculated based at least in part on a difference of the first attitude measurement and the second attitude measurement. The correction factor is then applied to the first attitude measurement to produce a corrected attitude measurement for the device.

8. 发明申请

US20130253821A1 System and Method for Determining a Uniform External Magnetic Field 有权
标题翻译：用于确定均匀外部磁场的系统和方法
公开(公告)号：US20130253821A1
公开(公告)日：2013-09-26
申请号：US13849447
申请日：2013-03-22
申请人： Benjamin E. Joseph , Ian Chen , Debbie Meduna
发明人： Benjamin E. Joseph , Ian Chen , Debbie Meduna
IPC分类号： G01C21/16
CPC分类号： G01C21/165 , G01C17/38 , G06F3/0346
摘要： A processing apparatus, optionally integrated into a device having a plurality of sensors including a magnetometer, generates navigational state estimates for the device. The processing apparatus has a magnetometer-assisted mode of operation in which measurements from the magnetometer are used to estimate the navigational state and an alternate mode of operation in which the navigational state of the device is estimated without measurements from the magnetometer. For a respective time period, the processing apparatus operates in the alternate mode of operation. During the respective time period, the processing apparatus collects a plurality of magnetometer measurements and determines whether they meet measurement-consistency requirements. If the measurements meet the measurement-consistency requirements, the processing apparatus transitions to the magnetometer-assisted mode of operation. If the measurements do not meet the measurement-consistency requirements, the processing apparatus continues to operate in the alternate mode of operation.
摘要翻译：可选地集成到具有包括磁力计的多个传感器的装置中的处理装置产生装置的导航状态估计。处理装置具有磁力计辅助操作模式，其中使用来自磁力计的测量来估计导航状态以及替代操作模式，其中在没有来自磁力计的测量的情况下估计装置的导航状态。对于相应的时间段，处理装置在替代操作模式下操作。在各个时间段期间，处理装置收集多个磁力计测量值并确定它们是否满足测量一致性要求。如果测量符合测量一致性要求，则处理设备转换到磁力计辅助操作模式。如果测量不符合测量一致性要求，则处理设备继续在备用操作模式下操作。

9. 发明授权

US08223121B2 Host system and method for determining an attitude of a device undergoing dynamic acceleration 有权
标题翻译：用于确定正在进行动态加速的设备的姿态的主机系统和方法
公开(公告)号：US08223121B2
公开(公告)日：2012-07-17
申请号：US12338996
申请日：2008-12-18
申请人： Kevin A. Shaw , Ian Chen
发明人： Kevin A. Shaw , Ian Chen
IPC分类号： G06F3/033
CPC分类号： G06F3/0346 , G06F3/017
摘要： A system and a method for determining an attitude of a device undergoing dynamic acceleration is presented. A first attitude measurement is calculated based on a magnetic field measurement received from a magnetometer of the device and a first acceleration measurement received from a first accelerometer of the device. A second attitude measurement is calculated based on the magnetic field measurement received from the magnetometer of the device and a second acceleration measurement received from a second accelerometer of the device. A correction factor is calculated based at least in part on a difference of the first attitude measurement and the second attitude measurement. The correction factor is then applied to the first attitude measurement to produce a corrected attitude measurement for the device.
摘要翻译：提出了一种用于确定正在进行动态加速的装置的姿态的系统和方法。基于从装置的磁力计接收的磁场测量和从装置的第一加速度计接收到的第一加速度测量来计算第一姿势测量。基于从装置的磁力计接收的磁场测量和从装置的第二加速度计接收到的第二加速度测量来计算第二姿态测量。至少部分地基于第一姿态测量和第二姿态测量的差异来计算校正因子。然后将校正因子应用于第一姿态测量以产生针对该装置的校正姿态测量。

10. 发明授权

US5710911A Clock control circuits, systems and methods 失效
公开(公告)号：US5710911A
公开(公告)日：1998-01-20
申请号：US484096
申请日：1995-06-07
申请人： James J. Walsh , Joseph Joe , Ian Chen , Yutaka Takahashi
发明人： James J. Walsh , Joseph Joe , Ian Chen , Yutaka Takahashi
IPC分类号： G06F1/26 , G06F1/04 , G06F1/06 , G06F1/10 , G06F1/16 , G06F1/32 , G06F3/00 , G06F9/30 , G06F1/08
CPC分类号： G06F1/1632 , G06F1/10 , G06F1/32
摘要： A microprocessor device (102) includes a central processing unit (702) having a clock input, a clock generator (OSC, PLL) of clock pulses, a logic circuit (708) having an output to supply a clock control signal (SUSP), and a clock gate (3610) fed by the clock pulses and having a clock gate output (CPU.sub.-- CLK) coupled to the clock input of the central processing unit. The clock gate (3610) responds to the clock control signal (SUSP) to prevent said clock pulses (CPU.sub.-- CLK) from reaching the central processing unit within one clock cycle of a change in said clock control signal. Other devices, systems and methods are also disclosed.

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