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1. 发明授权

US4820974A Method for measuring a characteristic of semiconductor memory device 失效
标题翻译：用于测量半导体存储器件的特性的方法
公开(公告)号：US4820974A
公开(公告)日：1989-04-11
申请号：US941626
申请日：1986-12-11
申请人： Joji Katsura , Seiji Yamaguchi , Kazuhiko Tsuji , Eisuke Ichinohe
发明人： Joji Katsura , Seiji Yamaguchi , Kazuhiko Tsuji , Eisuke Ichinohe
IPC分类号： H01L27/10 , G11C11/413 , G11C29/00 , G11C29/02 , G11C29/50 , G11C29/56 , G01R31/28 , G01R31/26
CPC分类号： G11C29/021 , G11C29/02 , G11C29/50 , G11C11/41 , G11C2029/5006
摘要： Method for measuring power supply current, e.g., standby current of a random access memory in which, before starting measurement of the power supply current, data is read-out from memory cell of the random access memory and opposite data is written in the memory cell so that the random access memory enters into an unstabilized state. By use of this method, the measurement of the maximum power supply current can be conducted precisely.
摘要翻译：用于测量电源电流的方法，例如随机存取存储器的待机电流，其中在开始测量电源电流之前，从随机存取存储器的存储单元读出数据并将相对数据写入存储单元使得随机存取存储器进入不稳定状态。通过这种方法，可以精确地进行最大电源电流的测量。

2. 发明授权

US4672584A CMOS integrated circuit 失效
标题翻译： CMOS集成电路
公开(公告)号：US4672584A
公开(公告)日：1987-06-09
申请号：US691701
申请日：1985-01-15
申请人： Kazuhiko Tsuji , Seiji Yamaguchi , Eisuke Ichinohe
发明人： Kazuhiko Tsuji , Seiji Yamaguchi , Eisuke Ichinohe
IPC分类号： H01L21/74 , H01L21/822 , H01L27/04 , H01L27/08 , H01L27/092 , H01L29/76 , H01L29/78 , H01L29/94 , H01L27/02
CPC分类号： H01L27/0921
摘要： A CMOS integrated circuit includes a P-channel type MOS transistor which is formed on an N-type silicon substrate, an N-channel type MOS transistor which is formed on a P well formed in the substrate, and parasitic bipolar transistors which are electrically connected to each other to form a kind of thyristor structure. A power supply voltage is applied to a source electrode of the P-channel type MOS transistor through a part of the substrate which presents a resistance. The resistance is electrically connected to the parasitic bipolar transistor of the thyristor structure to thereby prevent the occurrence of a latch-up phenomenon in which a large current continuously flows through the parasitic bipolar transistors and may destroy the CMOS integrated circuit. Because of the prevention of the latch-up phenomenon, the CMOS integrated circuit is always maintained in good condition.
摘要翻译： CMOS集成电路包括形成在N型硅衬底上的P沟道型MOS晶体管，形成在形成于衬底中的P阱上的N沟道型MOS晶体管和电连接的寄生双极晶体管彼此形成一种晶闸管结构。通过存在电阻的基板的一部分，将电源电压施加到P沟道型MOS晶体管的源电极。电阻电连接到晶闸管结构的寄生双极晶体管，从而防止大电流连续流过寄生双极晶体管的闩锁现象的发生，并可能破坏CMOS集成电路。由于防止闭锁现象，CMOS集成电路始终保持良好状态。

3. 发明授权

US4712194A Static random access memory 失效
标题翻译：静态随机存取存储器
公开(公告)号：US4712194A
公开(公告)日：1987-12-08
申请号：US739875
申请日：1985-05-31
申请人： Seiji Yamaguchi , Eisuke Ichinohe , Johji Katsura
发明人： Seiji Yamaguchi , Eisuke Ichinohe , Johji Katsura
IPC分类号： G11C11/419 , G11C7/00
CPC分类号： G11C11/419
摘要： The static random access memory reduces the access time thereof and reduces the power consumption thereof during its time of operation, and employs a circuit arrangement such that not only is the logical amplitude of each bit line diminished during a read-out operation, but the bit line is precharged after a write operation is accomplished during a write operation.
摘要翻译：静态随机存取存储器减少其访问时间并减少其在操作时的功耗，并且采用电路装置，使得不仅读出操作期间每个位线的逻辑振幅减小，而且位在写操作完成写操作之后，线被预充电。

4. 发明授权

US4872161A Bus circuit for eliminating undesired voltage amplitude 失效
标题翻译：用于消除不需要的电压幅度的总线电路
公开(公告)号：US4872161A
公开(公告)日：1989-10-03
申请号：US171469
申请日：1988-03-21
申请人： Eisuke Ichinohe
发明人： Eisuke Ichinohe
IPC分类号： H04L12/40
CPC分类号： H04L12/40045 , H04L12/40
摘要： A bus circuit capable of realizing a high speed data transfer cycle by eliminating undesired voltage amplitude of the data bus lines, includes a plurality of data bus lines, a potential initializing circuit for setting the initial potential of these data bus lines, an output port circuit for delivering data to these data bus lines, and an input port circuit for feeding data from these data bus lines. At least one of the data bus lines is a potential sensing line, and the sensing line is coupled to an inverting output circuit for inverting the initial potential from the output port circuit, and the potential change of this inverting output means is detected by a data firm judging means connected to the sensing line, and the output port circuit is deactivated by a control circuit in accordance with a judgement signal from the data firm judging circuit.
摘要翻译：能够通过消除数据总线的不需要的电压振幅实现高速数据传输周期的总线电路包括多条数据总线，用于设定这些数据总线的初始电位的电位初始化电路，输出端口电路用于将数据传送到这些数据总线，以及用于从这些数据总线传送数据的输入端口电路。至少一条数据总线是一个电位感测线，感测线耦合到反向输出电路，用于使输出端口电路的初始电位反相，并且该反相输出装置的电位变化由数据固定判断装置连接到感测线，并且输出端口电路根据来自数据公司判断电路的判断信号由控制电路去激活。

5. 发明授权

US4069067A Method of making a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US4069067A
公开(公告)日：1978-01-17
申请号：US667445
申请日：1976-03-16
申请人： Eisuke Ichinohe
发明人： Eisuke Ichinohe
IPC分类号： H01L21/033 , H01L21/285 , H01L29/78 , H01L21/26
CPC分类号： H01L21/033 , H01L21/28525 , H01L29/78 , Y10S148/141
摘要： A semiconductor device is described comprising a semiconductor substrate, plural impurity-diffused regions formed in the substrate, an insulation layer formed so as to cover selected parts of the substrate, plural low-resistance semiconductor regions isolated from each other by the insulation layer and at least some of them contacting said diffused regions and conductive regions disposed in a manner to contact said low-resistance semiconductor regions, respectively.Thus, the low-resistance semiconductor regions serve as connection means between the diffused region and the conductive region, which means serves to uniform contacting level, thereby decreasing the size of the device.
摘要翻译：描述了一种半导体器件，其包括半导体衬底，形成在衬底中的多个杂质扩散区域，形成为覆盖衬底的选定部分的绝缘层，由绝缘层彼此隔离的多个低电阻半导体区域，以及其中至少一部分分别以与所述低电阻半导体区域接触的方式接触所述扩散区域和导电区域。

6. 发明授权

US4523301A Associative memory 失效
标题翻译：关联记忆
公开(公告)号：US4523301A
公开(公告)日：1985-06-11
申请号：US499912
申请日：1983-06-01
申请人： Hiroshi Kadota , Eisuke Ichinohe
发明人： Hiroshi Kadota , Eisuke Ichinohe
IPC分类号： G11C15/04 , G11C11/40
CPC分类号： G11C15/04
摘要： An associative memory comprises memory cells arrayed in columns and rows, a pair of complementary bit lines disposed for each column of the memory cells, a word line disposed for each row of the memory cells, and a sense line disposed also for each row of the memory cells. Each memory cell includes a bistable circuit provided by a pair of cross-coupled inverters, a pair of first switching elements connected between the two nodal points of the bistable circuit and the bit lines respectively to be controlled depending on the potential of the word line, and a pair of second switching elements and a pair of diodes or like circuit elements having a rectifying characteristic connected in series between the bit lines and the sense line respectively. These second switching elements are controlled depending on the potentials of the two nodal points respectively in the bistable circuit. A load element, a sensing amplifier and a tri-state driver circuit are connected to the sense line. An input reference data bit pattern is applied in complementary fashion to the bit lines, and coincidence or non-coincidence between the input reference data and the stored data is discriminated by checking the output of the sensing amplifier connected to each sense line.
摘要翻译：相关存储器包括排列成列和行的存储单元，为存储单元的每一列设置的一对互补位线，为存储单元的每一行设置的字线，以及还用于每行存储单元的读出线记忆细胞每个存储单元包括由一对交叉耦合的反相器提供的双稳态电路，分别连接在双稳态电路的两个结点之间的一对第一开关元件和分别根据字线的电位进行控制的位线，以及一对第二开关元件和一对具有串联连接在位线和感测线之间的整流特性的二极管或类似电路元件。这些第二开关元件根据双稳态电路中的两个节点的电位进行控制。负载元件，感测放大器和三态驱动电路连接到感测线。以与位线互补的方式施加输入参考数据位模式，通过检查连接到每个感测线的感测放大器的输出来区分输入参考数据和存储数据之间的一致或非重合。

7. 发明授权

US4750026A C MOS IC and method of making the same 失效
标题翻译： C MOS IC及其制作方法
公开(公告)号：US4750026A
公开(公告)日：1988-06-07
申请号：US799556
申请日：1985-11-19
申请人： Shigeo Kuninobu , Eisuke Ichinohe
发明人： Shigeo Kuninobu , Eisuke Ichinohe
IPC分类号： H01L21/822 , H01L21/82 , H01L23/528 , H01L27/04 , H01L27/092 , H01L27/118 , H01L27/02
CPC分类号： H01L23/528 , H01L27/092 , H01L27/11807 , H01L2924/0002 , Y10S257/923
摘要： In a C MOS IC as shown in FIG. 7(A) and FIG. 8, the IC comprises vertical row of horizontally long blocks, each block comprising p-type MOS transistor region and n-type MOS transistor region, the IC comprises horizontal wirings of aluminum (31, 32, 33) and vertical wirings of polycrystalline silicon (61, 62, 63, 64, 65, 41, 42), with insulation films on the upper side and on the lower side of the polycrystalline silicon film, between the rows (I, II, . . .), said horizontal aluminum wirings (31, 32, 33) and said polycrystalline silicon wiring (61, 62 . . ., 41, 42) being appropriately connected through openings (105, 105 . . .) formed in said insulation film inbetween, said vertical polycrystalline silicon wirings being connected through aluminum wirings in said blocks.
摘要翻译：在如图1所示的C MOS IC中。图7（A）如图8所示，IC包括垂直排的水平长块，每个块包括p型MOS晶体管区域和n型MOS晶体管区域，IC包括铝（31,32,33）的水平布线和多晶硅的垂直布线 61,22,63,64,65,41,42），在多层硅膜的上侧和下侧上具有在行（I，II ...）之间的绝缘膜，所述水平铝布线（31,32,33），并且所述多晶硅布线（61,62 ...，41,42）通过形成在所述绝缘膜之间的开口（105,105 ...）适当地连接，所述垂直多晶硅布线是通过所述块中的铝布线连接。

8. 发明授权

US4181537A Method of fabricating an insulated gate field effect device 失效
标题翻译：制造绝缘栅场效应器件的方法
公开(公告)号：US4181537A
公开(公告)日：1980-01-01
申请号：US805576
申请日：1977-06-10
申请人： Eisuke Ichinohe
发明人： Eisuke Ichinohe
IPC分类号： H01L29/78 , H01L21/033 , H01L21/336 , H01L21/76 , H01L21/762 , H01G7/00 , H01L7/44 , H01L11/14 , H01L29/04
CPC分类号： H01L29/66575 , H01L21/033 , H01L21/76202 , H01L29/41783
摘要： This invention provides a method of making an improved gate structure in which the gate electrode is self-aligned with respect to the field isolation oxide regions.Gate constituting layers are formed on a substrate prior to formation of the field isolation oxide regions. An oxidation barrier layer is provided on such layers, also covering the other regions which should be formed into the source and drain regions, etc. By etching off the oxidation barrier layer above the field isolation regions, the boundary edges of the gate on the field isolation regions are formed. Then oxidation is performed using the oxidation barrier as a masking pattern to form the field isolation oxide regions. The field isolation oxide regions and the gate thus formed completely coincide with each other at their boundary edges.
摘要翻译：本发明提供一种制造栅极结构的改进方法，其中栅电极相对于场隔离氧化物区域自对准。在形成场隔离氧化物区域之前，在衬底上形成栅极构成层。在这样的层上设置有氧化阻挡层，也覆盖应形成源极和漏极区域的其它区域等。通过在场隔离区域上蚀刻氧化阻挡层，场上栅极的边界边缘形成隔离区。然后使用氧化屏障进行氧化作为掩模图案以形成场隔离氧化物区域。这样形成的场隔离氧化物区域和栅极在其边界边缘处完全相互重合。

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