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    • 5. 发明授权
    • Isolation trenches for memory devices
    • 存储器件的隔离沟槽
    • US07439157B2
    • 2008-10-21
    • US11129884
    • 2005-05-16
    • Zailong BianJohn SmytheJanos FucskoMichael Violette
    • Zailong BianJohn SmytheJanos FucskoMichael Violette
    • H01L21/76
    • H01L21/76232H01L27/11517
    • A method includes removing a portion of a substrate to define an isolation trench; forming a first dielectric layer on exposed surfaces of the substrate in the trench; forming a second dielectric layer on at least the first dielectric layer, the second dielectric layer containing a different dielectric material than the first dielectric layer; depositing a third dielectric layer to fill the trench; removing an upper portion of the third dielectric layer from the trench and leaving a lower portion covering a portion of the second dielectric layer; oxidizing the lower portion of the third dielectric layer after removing the upper portion; removing an exposed portion of the second dielectric layer from the trench, thereby exposing a portion of the first dielectric layer; and forming a fourth dielectric layer in the trench covering the exposed portion of the first dielectric layer.
    • 一种方法包括去除衬底的一部分以限定隔离沟槽; 在所述沟槽中的所述衬底的暴露表面上形成第一电介质层; 在至少所述第一介电层上形成第二电介质层,所述第二电介质层含有与所述第一电介质层不同的电介质材料; 沉积第三介电层以填充沟槽; 从沟槽移除第三电介质层的上部并留下覆盖第二介电层的一部分的下部; 在除去上部之后氧化第三电介质层的下部; 从所述沟槽去除所述第二电介质层的暴露部分,从而暴露所述第一介电层的一部分; 以及在所述沟槽中形成覆盖所述第一介电层的暴露部分的第四电介质层。
    • 6. 发明申请
    • Isolation trenches for memory devices
    • 存储器件的隔离沟槽
    • US20050287731A1
    • 2005-12-29
    • US11129884
    • 2005-05-16
    • Zailong BianJohn SmytheJanos FucskoMichael Violette
    • Zailong BianJohn SmytheJanos FucskoMichael Violette
    • H01L21/762H01L21/8238H01L21/8247H01L29/788
    • H01L21/76232H01L27/11517
    • A method includes removing a portion of a substrate to define an isolation trench; forming a first dielectric layer on exposed surfaces of the substrate in the trench; forming a second dielectric layer on at least the first dielectric layer, the second dielectric layer containing a different dielectric material than the first dielectric layer; depositing a third dielectric layer to fill the trench; removing an upper portion of the third dielectric layer from the trench and leaving a lower portion covering a portion of the second dielectric layer; oxidizing the lower portion of the third dielectric layer after removing the upper portion; removing an exposed portion of the second dielectric layer from the trench, thereby exposing a portion of the first dielectric layer; and forming a fourth dielectric layer in the trench covering the exposed portion of the first dielectric layer.
    • 一种方法包括去除衬底的一部分以限定隔离沟槽; 在所述沟槽中的所述衬底的暴露表面上形成第一电介质层; 在至少所述第一介电层上形成第二电介质层,所述第二电介质层含有与所述第一电介质层不同的电介质材料; 沉积第三介电层以填充沟槽; 从沟槽移除第三电介质层的上部并留下覆盖第二介电层的一部分的下部; 在除去上部之后氧化第三电介质层的下部; 从所述沟槽去除所述第二电介质层的暴露部分,从而暴露所述第一介电层的一部分; 以及在所述沟槽中形成覆盖所述第一介电层的暴露部分的第四电介质层。
    • 7. 发明授权
    • Methods of forming a non-volatile resistive oxide memory array
    • 形成非易失性电阻氧化物存储器阵列的方法
    • US08637113B2
    • 2014-01-28
    • US13354163
    • 2012-01-19
    • Gurtej SandhuJohn SmytheBhaskar Srinivasan
    • Gurtej SandhuJohn SmytheBhaskar Srinivasan
    • C23C18/00C23C20/00C23C28/00C23C30/00H01C17/06
    • H01L27/101H01L21/0271Y10S438/947
    • A method of forming a non-volatile resistive oxide memory array includes forming a plurality of one of conductive word lines or conductive bit lines over a substrate. Metal oxide-comprising material is formed over the plurality of said one of the word lines or bit lines. A series of elongated trenches is provided over the plurality of said one of the word lines or bit lines. A plurality of self-assembled block copolymer lines is formed within individual of the trenches in registered alignment with and between the trench sidewalls. A plurality of the other of conductive word lines or conductive bit lines is provided from said plurality of self-assembled block copolymer lines to form individually programmable junctions comprising said metal oxide-comprising material where the word lines and bit lines cross one another.
    • 形成非易失性电阻氧化物存储器阵列的方法包括在衬底上形成多个导电字线或导电位线。 含金属氧化物的材料形成在多条所述一条字线或位线中。 在多个所述一条字线或位线之间提供一系列细长的沟槽。 多个自组装嵌段共聚物线形成在沟槽中的各个内,与沟槽侧壁之间对准并且在沟槽侧壁之间形成。 从所述多个自组装嵌段共聚物线路提供多个导电字线或导电位线,以形成包含所述金属氧化物的材料的单独可编程的结,其中字线和位线彼此交叉。