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1. 发明授权

US06888752B2 Method of reducing disturbs in non-volatile memory 有权
公开(公告)号：US06888752B2
公开(公告)日：2005-05-03
申请号：US10613098
申请日：2003-07-01
申请人： John S. Mangan , Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
发明人： John S. Mangan , Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
IPC分类号： G11C16/02 , G11C16/12 , G11C16/04
CPC分类号： G11C7/12 , G11C16/12 , G11C16/3427 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50012 , G11C2029/1204
摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.

2. 发明授权

US06717851B2 Method of reducing disturbs in non-volatile memory 有权
标题翻译：减少非易失性存储器中的干扰的方法
公开(公告)号：US06717851B2
公开(公告)日：2004-04-06
申请号：US09759835
申请日：2001-01-10
申请人： John S. Mangan , Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
发明人： John S. Mangan , Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
IPC分类号： G11C1604
CPC分类号： G11C7/12 , G11C16/12 , G11C16/3427 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50012 , G11C2029/1204
摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.
摘要翻译：在非易失性存储器中，在阵列位线上的电压电平改变时产生的未选择字线中产生的位移电流可能导致干扰。提出了减少这些电流的技术。在第一方面，减少了在字线上同时编程的单元的数量。在非易失性存储器中，存储器单元阵列由多个单元组成，并且单元被组合成共享公共字线的平面，避免同一平面内的单元的同时编程。多个单元可以并行编程，但是它们被布置成处于分开的平面中。这是通过选择并行编程的单元数量及其顺序，使得所有编程在一起的单元都来自不同的平面，通过比较要编程的单元以查看是否来自同一平面，或者组合这些。在第二个互补方面，位线上的电压电平改变的速率是可调节的。通过监视干扰的频率，或者基于设备的应用，可以调整位线驱动器改变位线电压的速率。这可以通过外部设置速率或由控制器基于设备性能和产生的数据错误量来实现。

3. 发明授权

US07468915B2 Method of reducing disturbs in non-volatile memory 有权
标题翻译：减少非易失性存储器中的干扰的方法
公开(公告)号：US07468915B2
公开(公告)日：2008-12-23
申请号：US11538521
申请日：2006-10-04
申请人： Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
发明人： Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
IPC分类号： G11C11/34
CPC分类号： G11C7/12 , G11C16/12 , G11C16/3427 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50012 , G11C2029/1204
摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.
摘要翻译：在非易失性存储器中，在阵列位线上的电压电平改变时产生的未选择字线中产生的位移电流可能导致干扰。提出了减少这些电流的技术。在第一方面，减少了在字线上同时编程的单元的数量。在非易失性存储器中，存储器单元阵列由多个单元组成，并且单元被组合成共享公共字线的平面，避免同一平面内的单元的同时编程。多个单元可以并行编程，但是它们被布置成处于分开的平面中。这是通过选择并行编程的单元数量及其顺序，使得所有编程在一起的单元都来自不同的平面，通过比较要编程的单元以查看是否来自同一平面，或者组合这些。在第二个互补方面，位线上的电压电平改变的速率是可调节的。通过监视干扰的频率，或者基于设备的应用，可以调整位线驱动器改变位线电压的速率。这可以通过外部设置速率或由控制器基于设备性能和产生的数据错误量来实现。

4. 发明授权

US06977844B2 Method of reducing disturbs in non-volatile memory 失效
标题翻译：减少非易失性存储器中的干扰的方法
公开(公告)号：US06977844B2
公开(公告)日：2005-12-20
申请号：US11054084
申请日：2005-02-08
申请人： Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
发明人： Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
IPC分类号： G11C16/02 , G11C16/12 , G11C16/04
CPC分类号： G11C7/12 , G11C16/12 , G11C16/3427 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50012 , G11C2029/1204
摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.
摘要翻译：在非易失性存储器中，在阵列位线上的电压电平改变时产生的未选择字线中产生的位移电流可能导致干扰。提出了减少这些电流的技术。在第一方面，减少了在字线上同时编程的单元的数量。在非易失性存储器中，存储器单元阵列由多个单元组成，并且单元被组合成共享公共字线的平面，避免同一平面内的单元的同时编程。多个单元可以并行编程，但是它们被布置成处于分开的平面中。这是通过选择并行编程的单元数量及其顺序，使得所有编程在一起的单元都来自不同的平面，通过比较要编程的单元以查看是否来自同一平面，或者组合这些。在第二个互补方面，位线上的电压电平改变的速率是可调节的。通过监视干扰的频率，或者基于设备的应用，可以调整位线驱动器改变位线电压的速率。这可以通过外部设置速率或由控制器基于设备性能和产生的数据错误量来实现。

5. 发明授权

US07145804B2 Method of reducing disturbs in non-volatile memory 有权
公开(公告)号：US07145804B2
公开(公告)日：2006-12-05
申请号：US11238911
申请日：2005-09-28
申请人： Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
发明人： Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker N. Quader
IPC分类号： G11C11/34
CPC分类号： G11C7/12 , G11C16/12 , G11C16/3427 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50012 , G11C2029/1204
摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.

6. 发明授权

US06570785B1 Method of reducing disturbs in non-volatile memory 有权
标题翻译：减少非易失性存储器中的干扰的方法
公开(公告)号：US06570785B1
公开(公告)日：2003-05-27
申请号：US09703083
申请日：2000-10-31
申请人： John S. Mangan , Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang
发明人： John S. Mangan , Daniel C. Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang
IPC分类号： G11C1610
CPC分类号： G11C16/12
摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage is adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.
摘要翻译：在非易失性存储器中，在阵列位线上的电压电平改变时产生的未选择字线中产生的位移电流可能导致干扰。提出了减少这些电流的技术。在第一方面，减少了在字线上同时编程的单元的数量。在非易失性存储器中，存储器单元阵列由多个单元组成，并且单元被组合成共享公共字线的平面，避免同一平面内的单元的同时编程。多个单元可以并行编程，但是它们被布置成处于分开的平面中。这是通过选择并行编程的单元数量及其顺序，使得所有编程在一起的单元都来自不同的平面，通过比较要编程的单元以查看是否来自同一平面，或者组合这些。在第二个互补方面，位线上的电压电平改变的速率是可调节的。通过监视干扰的频率，或者基于设备的应用，调整位线驱动器改变位线电压的速率。这可以通过外部设置速率或由控制器基于设备性能和产生的数据错误量来实现。

7. 发明申请

US20100020616A1 Soft Errors Handling in EEPROM Devices 有权
标题翻译： EEPROM设备中的软错误处理
公开(公告)号：US20100020616A1
公开(公告)日：2010-01-28
申请号：US12572098
申请日：2009-10-01
申请人： Daniel L. Auclair , Jeffrey Craig , John S. Mangan , Robert D. Norman , Daniel C. Guterman , Sanjay Mehrotra
发明人： Daniel L. Auclair , Jeffrey Craig , John S. Mangan , Robert D. Norman , Daniel C. Guterman , Sanjay Mehrotra
IPC分类号： G11C16/04
CPC分类号： G11C29/028 , G06F11/1068 , G06F11/1072 , G06F2201/81 , G11C16/04 , G11C16/10 , G11C16/3431 , G11C29/50 , G11C29/50004 , G11C29/52 , G11C2029/5004 , G11C2029/5006
摘要： Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.
摘要翻译：正常使用固态存储器（如EEPROM或闪存EEPROM）时会发生软错误。存储器单元的编程阈值电压从原来的预期电平漂移导致软错误。在正常读取期间，最初不容易检测到该误差，直到累积漂移变得如此严重以致其发展为硬错误。数据可能会丢失，如果这些硬错误足够的可以在存储器中发出可用的纠错码。一种存储器件及其技术能够在整个使用存储器件的过程中检测这些漂移并且将每个存储器单元的阈值电压基本上保持在其预期的水平，从而抵抗将软错误发展成硬错误。

8. 发明授权

US07548461B2 Soft errors handling in EEPROM devices 失效
公开(公告)号：US07548461B2
公开(公告)日：2009-06-16
申请号：US10874825
申请日：2004-06-22
申请人： Daniel L. Auclair , Jeffrey Craig , John S. Mangan , Robert D. Norman , Daniel C. Guterman , Sanjay Mehrotra
发明人： Daniel L. Auclair , Jeffrey Craig , John S. Mangan , Robert D. Norman , Daniel C. Guterman , Sanjay Mehrotra
IPC分类号： G11C11/34
CPC分类号： G11C29/028 , G06F11/1068 , G06F11/1072 , G06F2201/81 , G11C16/04 , G11C16/10 , G11C16/3431 , G11C29/50 , G11C29/50004 , G11C29/52 , G11C2029/5004 , G11C2029/5006
摘要： Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.

9. 发明授权

US07616484B2 Soft errors handling in EEPROM devices 失效
标题翻译： EEPROM器件中的软错误处理
公开(公告)号：US07616484B2
公开(公告)日：2009-11-10
申请号：US10974366
申请日：2004-10-26
申请人： Daniel L. Auclair , Jeffrey Craig , John S. Mangan , Robert D. Norman , Daniel C. Guterman , Sanjay Mehrotra
发明人： Daniel L. Auclair , Jeffrey Craig , John S. Mangan , Robert D. Norman , Daniel C. Guterman , Sanjay Mehrotra
IPC分类号： G11C16/06 , G11C16/04 , G11C29/00 , G08C25/00
CPC分类号： G11C29/028 , G06F11/1068 , G06F11/1072 , G06F2201/81 , G11C16/04 , G11C16/10 , G11C16/3431 , G11C29/50 , G11C29/50004 , G11C29/52 , G11C2029/5004 , G11C2029/5006
摘要： Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.
摘要翻译：正常使用固态存储器（如EEPROM或闪存EEPROM）时会发生软错误。存储器单元的编程阈值电压从原来的预期电平漂移导致软错误。在正常读取期间，最初不容易检测到该误差，直到累积漂移变得如此严重以致其发展为硬错误。数据可能会丢失，如果这些硬错误足够的可以在存储器中发出可用的纠错码。一种存储器件及其技术能够在整个使用存储器件的过程中检测这些漂移并且将每个存储器单元的阈值电压基本上保持在其预期的水平，从而抵抗将软错误发展成硬错误。

10. 发明授权

US6049899A Soft errors handling in EEPROM devices 失效
公开(公告)号：US6049899A
公开(公告)日：2000-04-11
申请号：US113800
申请日：1998-07-08
申请人： Daniel L. Auclair , Jeffrey Craig , John S. Mangan , Robert D. Norman , Daniel C. Guterman , Sanjay Mehrotra
发明人： Daniel L. Auclair , Jeffrey Craig , John S. Mangan , Robert D. Norman , Daniel C. Guterman , Sanjay Mehrotra
IPC分类号： G06F11/10 , G11C16/10 , G11C29/50 , G11C29/52 , H03M13/00
CPC分类号： G11C29/028 , G11C16/10 , G11C16/3431 , G11C29/50 , G11C29/50004 , G11C29/52 , G06F11/1068 , G06F11/1072 , G06F2201/81 , G11C16/04 , G11C2029/5004 , G11C2029/5006
摘要： Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.

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