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1. 发明授权

US07809982B2 Reconfigurable computing machine and related systems and methods 有权
标题翻译：可重构计算机及相关系统和方法
公开(公告)号：US07809982B2
公开(公告)日：2010-10-05
申请号：US11243508
申请日：2005-10-03
申请人： John Rapp , Chandan Mathur , Scott Hellenbach , Mark Jones , Joseph A. Capizzi
发明人： John Rapp , Chandan Mathur , Scott Hellenbach , Mark Jones , Joseph A. Capizzi
IPC分类号： G06F11/00
CPC分类号： G06F17/5054 , G06F9/54 , G06F11/1407 , G06F11/1417 , G06F11/142 , G06F11/2025 , G06F11/2028 , G06F11/2035 , G06F11/2038 , G06F11/2051 , G06F13/1694 , G06F15/7867 , G06F15/8053 , G06F17/505 , H04Q9/00
摘要： A computing machine comprises an electronic circuit operable to perform a function, a programmable integrated circuit such as an FPGA, and a processor. The processor is operable to detect a failure of the electronic circuit and to configure the programmable integrated circuit to perform the function of the electronic circuit in response to detecting the failure. Alternatively, the computing machine comprises a hardwired pipeline operable to perform a function and a processor operable to detect a failure of the pipeline and to perform the function in response to detecting the failure. By allowing a first type of circuit (e.g., an FPGA) to take over for a failed second type of circuit (e.g., a processor), such a computing machine can be fault-tolerant without having redundant versions of each component, and may thus be less expensive and smaller than computing machines of comparable computing power.
摘要翻译：计算机包括可执行功能的电子电路，诸如FPGA的可编程集成电路和处理器。处理器可操作以检测电子电路的故障并且配置可编程集成电路以响应于检测到故障来执行电子电路的功能。或者，计算机包括可操作以执行功能的硬连线管线和可操作以检测管道故障并且响应于检测到故障而执行功能的处理器。通过允许第一类电路（例如，FPGA）接管故障的第二类电路（例如，处理器），这样的计算机可以是容错的，而不需要每个组件的冗余版本，并且因此可以比较可靠的计算能力的计算机更便宜，更小。

2. 发明授权

US07676649B2 Computing machine with redundancy and related systems and methods 有权
标题翻译：具有冗余和相关系统和方法的计算机
公开(公告)号：US07676649B2
公开(公告)日：2010-03-09
申请号：US11243507
申请日：2005-10-03
申请人： John Rapp , Chandan Mathur , Scott Hellenbach , Mark Jones , Joseph A. Capizzi
发明人： John Rapp , Chandan Mathur , Scott Hellenbach , Mark Jones , Joseph A. Capizzi
IPC分类号： G06F15/76 , G06F11/00 , G06F11/16 , G06F9/00
CPC分类号： G06F17/5054 , G06F9/54 , G06F11/1407 , G06F11/1417 , G06F11/142 , G06F11/2025 , G06F11/2028 , G06F11/2035 , G06F11/2038 , G06F11/2051 , G06F13/1694 , G06F15/7867 , G06F15/8053 , G06F17/505 , H04Q9/00
摘要： According to an embodiment of the invention, a computing machine comprises a pipeline accelerator, a host processor coupled to the pipeline accelerator, and a redundant processor, a redundant pipeline unit, or both, coupled to the host processor and to the pipeline accelerator. The computing machine may also include a system-restore server and a system-restore bus that allow the machine to periodically save the machine states in case of a failure. Such a computing machine has a fault-tolerant scheme that is often more flexible than conventional schemes. For example, if the pipeline accelerator has more extra “space” than the host processor, then one can add to the computing machine one or more redundant pipeline units that can provide redundancy to both the pipeline and the host processor. Therefore, the computing machine can include redundancy for the host processor even though it has no redundant processing units.
摘要翻译：根据本发明的实施例，计算机器包括流水线加速器，耦合到流水线加速器的主机处理器，以及耦合到主机处理器和流水线加速器的冗余处理器，冗余流水线单元或两者。计算机还可以包括系统恢复服务器和系统恢复总线，其允许机器在发生故障的情况下周期性地保存机器状态。这样的计算机具有通常比常规方案更灵活的容错方案。例如，如果流水线加速器具有比主处理器更多的“空间”，则可以向计算机添加一个或多个冗余流水线单元，其可以为流水线和主机处理器提供冗余。因此，即使计算机没有冗余处理单元，计算机也可以包括主机处理器的冗余。

3. 发明申请

US20060101307A1 Reconfigurable computing machine and related systems and methods 有权
标题翻译：可重构计算机及相关系统和方法
公开(公告)号：US20060101307A1
公开(公告)日：2006-05-11
申请号：US11243508
申请日：2005-10-03
申请人： John Rapp , Chandan Mathur , Scott Hellenbach , Mark Jones , Joseph Capizzi
发明人： John Rapp , Chandan Mathur , Scott Hellenbach , Mark Jones , Joseph Capizzi
IPC分类号： G06F11/00
CPC分类号： G06F17/5054 , G06F9/54 , G06F11/1407 , G06F11/1417 , G06F11/142 , G06F11/2025 , G06F11/2028 , G06F11/2035 , G06F11/2038 , G06F11/2051 , G06F13/1694 , G06F15/7867 , G06F15/8053 , G06F17/505 , H04Q9/00
摘要： A computing machine comprises an electronic circuit operable to perform a function, a programmable integrated circuit such as an FPGA, and a processor. The processor is operable to detect a failure of the electronic circuit and to configure the programmable integrated circuit to perform the function of the electronic circuit in response to detecting the failure. Alternatively, the computing machine comprises a hardwired pipeline operable to perform a function and a processor operable to detect a failure of the pipeline and to perform the function in response to detecting the failure. By allowing a first type of circuit (e.g., an FPGA) to take over for a failed second type of circuit (e.g., a processor), such a computing machine can be fault-tolerant without having redundant versions of each component, and may thus be less expensive and smaller than computing machines of comparable computing power.
摘要翻译：计算机包括可执行功能的电子电路，诸如FPGA的可编程集成电路和处理器。处理器可操作以检测电子电路的故障并且配置可编程集成电路以响应于检测到故障来执行电子电路的功能。或者，计算机包括可操作以执行功能的硬连线管线和可操作以检测管道故障并且响应于检测到故障而执行功能的处理器。通过允许第一类电路（例如，FPGA）接管故障的第二类电路（例如，处理器），这样的计算机可以是容错的，而不需要每个组件的冗余版本，并且因此可以比较可靠的计算能力的计算机更便宜，更小。

4. 发明申请

US20060101250A1 Configurable computing machine and related systems and methods 审中-公开
标题翻译：可配置的计算机及相关系统和方法
公开(公告)号：US20060101250A1
公开(公告)日：2006-05-11
申请号：US11243459
申请日：2005-10-03
申请人： John Rapp , Chandan Mathur , Scott Hellenbach , Mark Jones , Joseph Capizzi
发明人： John Rapp , Chandan Mathur , Scott Hellenbach , Mark Jones , Joseph Capizzi
IPC分类号： G06F9/44
CPC分类号： G06F17/5054 , G06F9/54 , G06F11/1407 , G06F11/1417 , G06F11/142 , G06F11/2025 , G06F11/2028 , G06F11/2035 , G06F11/2038 , G06F11/2051 , G06F13/1694 , G06F15/7867 , G06F15/8053 , G06F17/505 , H04Q9/00
摘要： A computing machine includes programmable integrated circuits, a configuration registry, and a processor. The registry stores a file that defines a circuit having portions, and the processor is, in response to the file, operable to instantiate one of the circuit portions on one of the programmable integrated circuits. Consequently, by accessing a file that defines a circuit, such a computing machine can often instantiate the circuit on a pipeline accelerator regardless of the hardware that compose the accelerator and despite modifications to the circuit or to the hardware. That is, the computing machine can often “fit” the circuit into the pipeline accelerator regardless of its composition.
摘要翻译：计算机包括可编程集成电路，配置注册表和处理器。注册表存储定义具有部分的电路的文件，并且处理器响应于文件可操作以实例化其中一个可编程集成电路中的一个电路部分。因此，通过访问定义电路的文件，这种计算机器可以经常在线路加速器上实例化电路，而不考虑构成加速器的硬件，并且尽管修改了电路或硬件。也就是说，计算机通常可以将电路“适配”到管道加速器中，而不管其组成如何。

5. 发明申请

US20060101253A1 Computing machine with redundancy and related systems and methods 有权
标题翻译：具有冗余的计算机及相关系统和方法
公开(公告)号：US20060101253A1
公开(公告)日：2006-05-11
申请号：US11243507
申请日：2005-10-03
申请人： John Rapp , Chandan Mathur , Scott Hellenbach , Mark Jones , Joseph Capizzi
发明人： John Rapp , Chandan Mathur , Scott Hellenbach , Mark Jones , Joseph Capizzi
IPC分类号： G06F9/44
CPC分类号： G06F17/5054 , G06F9/54 , G06F11/1407 , G06F11/1417 , G06F11/142 , G06F11/2025 , G06F11/2028 , G06F11/2035 , G06F11/2038 , G06F11/2051 , G06F13/1694 , G06F15/7867 , G06F15/8053 , G06F17/505 , H04Q9/00
摘要： According to an embodiment of the invention, a computing machine comprises a pipeline accelerator, a host processor coupled to the pipeline accelerator, and a redundant processor, a redundant pipeline unit, or both, coupled to the host processor and to the pipeline accelerator. The computing machine may also include a system-restore server and a system-restore bus that allow the machine to periodically save the machine states in case of a failure. Such a computing machine has a fault-tolerant scheme that is often more flexible than conventional schemes. For example, if the pipeline accelerator has more extra “space” than the host processor, then one can add to the computing machine one or more redundant pipeline units that can provide redundancy to both the pipeline and the host processor. Therefore, the computing machine can include redundancy for the host processor even though it has no redundant processing units.
摘要翻译：根据本发明的实施例，计算机器包括流水线加速器，耦合到流水线加速器的主机处理器，以及耦合到主机处理器和流水线加速器的冗余处理器，冗余流水线单元或两者。计算机还可以包括系统恢复服务器和系统恢复总线，其允许机器在发生故障的情况下周期性地保存机器状态。这样的计算机具有通常比常规方案更灵活的容错方案。例如，如果流水线加速器具有比主处理器更多的“空间”，则可以向计算机添加一个或多个冗余流水线单元，其可以为流水线和主机处理器提供冗余。因此，即使计算机没有冗余处理单元，计算机也可以包括主机处理器的冗余。

6. 发明授权

US07418574B2 Configuring a portion of a pipeline accelerator to generate pipeline date without a program instruction 有权
标题翻译：配置流水线加速器的一部分，以生成没有程序指令的流水线日期
公开(公告)号：US07418574B2
公开(公告)日：2008-08-26
申请号：US10684102
申请日：2003-10-09
申请人： Chandan Mathur , Scott Hellenbach , John W. Rapp , Larry Jackson , Mark Jones , Troy Cherasaro
发明人： Chandan Mathur , Scott Hellenbach , John W. Rapp , Larry Jackson , Mark Jones , Troy Cherasaro
IPC分类号： G06F15/76
CPC分类号： G06F15/7867 , G06Q40/08
摘要： A peer-vector machine includes a host processor and a hardwired pipeline accelerator. The host processor executes a program, and, in response to the program, generates host data, and the pipeline accelerator generates pipeline data from the host data. Alternatively, the pipeline accelerator generates the pipeline data, and the host processor generates the host data from the pipeline data. Because the peer-vector machine includes both a processor and a pipeline accelerator, it can often process data more efficiently than a machine that includes only processors or only accelerators. For example, one can design the peer-vector machine so that the host processor performs decision-making and non-mathematically intensive operations and the accelerator performs non-decision-making and mathematically intensive operations. By shifting the mathematically intensive operations to the accelerator, the peer-vector machine often can, for a given clock frequency, process data at a speed that surpasses the speed at which a processor-only machine can process the data.
摘要翻译：对等矢量机包括主处理器和硬连线管道加速器。主机处理器执行程序，响应于程序生成主机数据，流水线加速器从主机数据生成流水线数据。或者，流水线加速器生成流水线数据，并且主机处理器从流水线数据生成主机数据。由于同向向量机同时包含处理器和流水线加速器，所以它通常可以比仅包含处理器或仅加速器的机器更有效地处理数据。例如，可以设计对等矢量机，以便主机处理器执行决策和非数学密集型操作，并且加速器执行非决策和数学密集型操作。通过将数学密集型操作转移到加速器，对于给定的时钟频率，对等矢量机器可以以超过仅处理器机器处理数据的速度的速度处理数据。

7. 发明授权

US07987341B2 Computing machine using software objects for transferring data that includes no destination information 有权
标题翻译：计算机使用软件对象传输不包含目的地信息的数据
公开(公告)号：US07987341B2
公开(公告)日：2011-07-26
申请号：US10684053
申请日：2003-10-09
申请人： Chandan Mathur , Scott Hellenbach , John W. Rapp
发明人： Chandan Mathur , Scott Hellenbach , John W. Rapp
IPC分类号： G06F9/00 , G06F15/76 , G06F3/00
CPC分类号： G06F15/7867 , G06Q40/08
摘要： A computing machine includes a first buffer and a processor coupled to the buffer. The processor executes an application, a first data-transfer object, and a second data-transfer object, publishes data under the control of the application, loads the published data into the buffer under the control of the first data-transfer object, and retrieves the published data from the buffer under the control of the second data-transfer object. Alternatively, the processor retrieves data and loads the retrieved data into the buffer under the control of the first data-transfer object, unloads the data from the buffer under the control of the second data-transfer object, and processes the unloaded data under the control of the application. Where the computing machine is a peer-vector machine that includes a hardwired pipeline accelerator coupled to the processor, the buffer and data-transfer objects facilitate the transfer of data between the application and the accelerator.
摘要翻译：计算机包括第一缓冲器和耦合到缓冲器的处理器。处理器执行应用程序，第一数据传输对象和第二数据传输对象，在应用程序的控制下发布数据，在第一数据传输对象的控制下将发布的数据加载到缓冲器中，并检索来自缓冲区的已发布数据在第二个数据传输对象的控制下。或者，处理器在第一数据传输对象的控制下检索数据并将检索到的数据加载到缓冲器中，在第二数据传输对象的控制下从缓冲器中卸载数据，并在控制下处理卸载的数据的应用程序。在计算机是包括耦合到处理器的硬连线管道加速器的对等矢量机的情况下，缓冲器和数据传输对象便于在应用和加速器之间的数据传送。

8. 发明申请

US20060230377A1 Computer-based tool and method for designing an electronic circuit and related system 审中-公开
标题翻译：基于计算机的工具和设计电子电路及相关系统的方法
公开(公告)号：US20060230377A1
公开(公告)日：2006-10-12
申请号：US11243509
申请日：2005-10-03
申请人： John Rapp , Scott Hellenbach , T. Kurian , D. Schooley , Troy Cherasaro
发明人： John Rapp , Scott Hellenbach , T. Kurian , D. Schooley , Troy Cherasaro
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F9/54 , G06F11/1407 , G06F11/1417 , G06F11/142 , G06F11/2025 , G06F11/2028 , G06F11/2035 , G06F11/2038 , G06F11/2051 , G06F13/1694 , G06F15/7867 , G06F15/8053 , G06F17/505 , H04Q9/00
摘要： A computer-based circuit-design tool includes a front end, an interpreter coupled to the front end, and a generator coupled the interpreter. The front end receives symbols that define an algorithm, and the interpreter parses the algorithm into respective algorithm portions. The generator identifies a corresponding circuit template for each of the algorithm portions, each template defining a circuit for executing the respective algorithm portion, and interconnects the identified templates such that the interconnected templates define a circuit that is operable to execute the algorithm. As compared to prior design tools, this tool may decrease the time and effort required to design a circuit for instantiation on a programmable logic integrated circuit (PLIC) or on an application-specific integrated circuit (ASIC) by allowing one to construct the circuit from previously written templates that define previously tested and debugged circuits.
摘要翻译：基于计算机的电路设计工具包括前端，耦合到前端的解释器和耦合解释器的发生器。前端接收定义算法的符号，解释器将算法解析成各自的算法部分。发生器为每个算法部分识别相应的电路模板，每个模板定义用于执行相应算法部分的电路，并且互连所识别的模板，使得互连的模板定义可操作以执行算法的电路。与现有的设计工具相比，该工具可以通过允许一个构造电路从而减少在可编程逻辑集成电路（PLIC）或专用集成电路（ASIC）上设计用于实例化的电路所需的时间和精力以前编写的模板定义了以前测试和调试的电路。

9. 发明申请

US20060085781A1 Library for computer-based tool and related system and method 审中-公开
标题翻译：基于计算机的工具及相关系统和方法库
公开(公告)号：US20060085781A1
公开(公告)日：2006-04-20
申请号：US11243506
申请日：2005-10-03
申请人： John Rapp , Scott Hellenbach , T. Kurian , D. Schooley
发明人： John Rapp , Scott Hellenbach , T. Kurian , D. Schooley
IPC分类号： G06F17/50 , H03K19/00
CPC分类号： G06F17/5054 , G06F9/54 , G06F11/1407 , G06F11/1417 , G06F11/142 , G06F11/2025 , G06F11/2028 , G06F11/2035 , G06F11/2038 , G06F11/2051 , G06F13/1694 , G06F15/7867 , G06F15/8053 , G06F17/505 , H04Q9/00
摘要： A library includes one or more circuit templates and an interface template. The one or more circuit templates each define a respective circuit operable to execute a respective algorithm or portion thereof. And the interface template defines a hardware layer operable to interface one of the circuits to pins of a programmable logic circuit when the layer and the one circuit are instantiated on the programmable logic circuit. Such a library may shorten the time and reduce the effort that an engineer expends designing a circuit for instantiation on a PLIC or ASIC by allowing the engineer to build the circuit from templates of previously designed and debugged circuits.
摘要翻译：库包括一个或多个电路模板和接口模板。一个或多个电路模板各限定可操作以执行相应算法或其一部分的相应电路。并且接口模板定义了一个硬件层，当层和一个电路在可编程逻辑电路上被实例化时，该层可操作用于将一个电路连接到可编程逻辑电路的引脚。这样的图书馆可以缩短时间，并减少工程师通过允许工程师从先前设计和调试的电路的模板构建电路而花费在PLIC或ASIC上设计电路的努力。

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