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1. 发明授权

US07418574B2 Configuring a portion of a pipeline accelerator to generate pipeline date without a program instruction 有权
标题翻译：配置流水线加速器的一部分，以生成没有程序指令的流水线日期
公开(公告)号：US07418574B2
公开(公告)日：2008-08-26
申请号：US10684102
申请日：2003-10-09
申请人： Chandan Mathur , Scott Hellenbach , John W. Rapp , Larry Jackson , Mark Jones , Troy Cherasaro
发明人： Chandan Mathur , Scott Hellenbach , John W. Rapp , Larry Jackson , Mark Jones , Troy Cherasaro
IPC分类号： G06F15/76
CPC分类号： G06F15/7867 , G06Q40/08
摘要： A peer-vector machine includes a host processor and a hardwired pipeline accelerator. The host processor executes a program, and, in response to the program, generates host data, and the pipeline accelerator generates pipeline data from the host data. Alternatively, the pipeline accelerator generates the pipeline data, and the host processor generates the host data from the pipeline data. Because the peer-vector machine includes both a processor and a pipeline accelerator, it can often process data more efficiently than a machine that includes only processors or only accelerators. For example, one can design the peer-vector machine so that the host processor performs decision-making and non-mathematically intensive operations and the accelerator performs non-decision-making and mathematically intensive operations. By shifting the mathematically intensive operations to the accelerator, the peer-vector machine often can, for a given clock frequency, process data at a speed that surpasses the speed at which a processor-only machine can process the data.
摘要翻译：对等矢量机包括主处理器和硬连线管道加速器。主机处理器执行程序，响应于程序生成主机数据，流水线加速器从主机数据生成流水线数据。或者，流水线加速器生成流水线数据，并且主机处理器从流水线数据生成主机数据。由于同向向量机同时包含处理器和流水线加速器，所以它通常可以比仅包含处理器或仅加速器的机器更有效地处理数据。例如，可以设计对等矢量机，以便主机处理器执行决策和非数学密集型操作，并且加速器执行非决策和数学密集型操作。通过将数学密集型操作转移到加速器，对于给定的时钟频率，对等矢量机器可以以超过仅处理器机器处理数据的速度的速度处理数据。

2. 发明申请

US20080222337A1 Pipeline accelerator having multiple pipeline units and related computing machine and method 有权
标题翻译：具有多个流水线单元的管道加速器及相关的计算机和方法
公开(公告)号：US20080222337A1
公开(公告)日：2008-09-11
申请号：US12151116
申请日：2008-05-02
申请人： Kenneth R. Schulz , John W. Rapp , Larry Jackson , Mark Jones , Troy Cherasaro
发明人： Kenneth R. Schulz , John W. Rapp , Larry Jackson , Mark Jones , Troy Cherasaro
IPC分类号： G06F1/12 , G06F13/14
CPC分类号： G06F15/7867 , G06Q40/08
摘要： A pipeline accelerator includes a bus and a plurality of pipeline units, each unit coupled to the bus and including at least one respective hardwired-pipeline circuit. By including a plurality of pipeline units in the pipeline accelerator, one can increase the accelerator's data-processing performance as compared to a single-pipeline-unit accelerator. Furthermore, by designing the pipeline units so that they communicate via a common bus, one can alter the number of pipeline units, and thus alter the configuration and functionality of the accelerator, by merely coupling or uncoupling pipeline units to or from the bus. This eliminates the need to design or redesign the pipeline-unit interfaces each time one alters one of the pipeline units or alters the number of pipeline units within the accelerator.
摘要翻译：流水线加速器包括总线和多个流水线单元，每个单元耦合到总线并且包括至少一个相应的硬连线流水线电路。通过在流水线加速器中包括多个流水线单元，与单管道单元加速器相比，可以增加加速器的数据处理性能。此外，通过设计流水线单元使得它们通过公共总线进行通信，只需将流水线单元耦合或从母线解耦即可改变流水线单元的数量，从而改变加速器的配置和功能。这样就无需设计或重新设计流水线单元接口，每次更换流水线单元之一或改变加速器中的流水线单元数量。

3. 发明授权

US07373432B2 Programmable circuit and related computing machine and method 有权
标题翻译：可编程电路及相关计算机及方法
公开(公告)号：US07373432B2
公开(公告)日：2008-05-13
申请号：US10684057
申请日：2003-10-09
申请人： John W. Rapp , Larry Jackson , Mark Jones , Troy Cherasaro
发明人： John W. Rapp , Larry Jackson , Mark Jones , Troy Cherasaro
IPC分类号： G06F3/00 , G06F15/76 , H03K19/00
CPC分类号： G06F15/7867 , G06Q40/08
摘要： A programmable circuit receives configuration data from an external source, stores the firmware in a memory, and then downloads the firmware from the memory. Such a programmable circuit allows a system, such as a computing machine, to modify the programmable circuit's configuration, thus eliminating the need for manually reprogramming the configuration memory. For example, if the programmable circuit is an FPGA that is part of a pipeline accelerator, a processor coupled to the accelerator can modify the configuration of the FPGA. More specifically, the processor retrieves from a configuration registry firmware that represents the modified configuration, and sends the firmware to the FPGA, which then stores the firmware in a memory such as an electrically erasable and programmable read-only memory (EEPROM). Next, the FPGA downloads the firmware from the memory into its configuration registers, and thus reconfigures itself to have the modified configuration.
摘要翻译：可编程电路从外部源接收配置数据，将固件存储在存储器中，然后从存储器下载固件。这样的可编程电路允许诸如计算机的系统修改可编程电路的配置，从而消除对手动重新编程配置存储器的需要。例如，如果可编程电路是作为流水线加速器一部分的FPGA，则耦合到加速器的处理器可以修改FPGA的配置。更具体地说，处理器从表示修改的配置的配置注册表固件中检索，并将固件发送到FPGA，FPGA将固件存储在诸如电可擦除可编程只读存储器（EEPROM）的存储器中。接下来，FPGA将固件从存储器下载到其配置寄存器中，从而将其重新配置为具有修改的配置。

4. 发明授权

US08250341B2 Pipeline accelerator having multiple pipeline units and related computing machine and method 有权
标题翻译：具有多个流水线单元的管道加速器及相关的计算机和方法
公开(公告)号：US08250341B2
公开(公告)日：2012-08-21
申请号：US12151116
申请日：2008-05-02
申请人： Kenneth R Schulz , John W Rapp , Larry Jackson , Mark Jones , Troy Cherasaro
发明人： Kenneth R Schulz , John W Rapp , Larry Jackson , Mark Jones , Troy Cherasaro
IPC分类号： G06F15/00
CPC分类号： G06F15/7867 , G06Q40/08
摘要： A pipeline accelerator includes a bus and a plurality of pipeline units, each unit coupled to the bus and including at least one respective hardwired-pipeline circuit. By including a plurality of pipeline units in the pipeline accelerator, one can increase the accelerator's data-processing performance as compared to a single-pipeline-unit accelerator. Furthermore, by designing the pipeline units so that they communicate via a common bus, one can alter the number of pipeline units, and thus alter the configuration and functionality of the accelerator, by merely coupling or uncoupling pipeline units to or from the bus. This eliminates the need to design or redesign the pipeline-unit interfaces each time one alters one of the pipeline units or alters the number of pipeline units within the accelerator.
摘要翻译：流水线加速器包括总线和多个流水线单元，每个单元耦合到总线并且包括至少一个相应的硬连线流水线电路。通过在流水线加速器中包括多个流水线单元，与单管道单元加速器相比，可以增加加速器的数据处理性能。此外，通过设计流水线单元使得它们通过公共总线进行通信，只需将流水线单元耦合到或从母线解耦即可改变流水线单元的数量，从而改变加速器的配置和功能。这样就无需设计或重新设计流水线单元接口，每次更换流水线单元之一或改变加速器中的流水线单元数量。

5. 发明授权

US07386704B2 Pipeline accelerator including pipeline circuits in communication via a bus, and related system and method 有权
标题翻译：管道加速器，包括通过总线进行通信的管道电路，以及相关的系统和方法
公开(公告)号：US07386704B2
公开(公告)日：2008-06-10
申请号：US10683932
申请日：2003-10-09
申请人： Kenneth R. Schulz , John W. Rapp , Larry Jackson , Mark Jones , Troy Cherasaro
发明人： Kenneth R. Schulz , John W. Rapp , Larry Jackson , Mark Jones , Troy Cherasaro
IPC分类号： G06F9/38
CPC分类号： G06F15/7867 , G06Q40/08
摘要： A pipeline accelerator includes a bus and a plurality of pipeline units, each unit coupled to the bus and including at least one respective hardwired-pipeline circuit. By including a plurality of pipeline units in the pipeline accelerator, one can increase the accelerator's data-processing performance as compared to a single-pipeline-unit accelerator. Furthermore, by designing the pipeline units so that they communicate via a common bus, one can alter the number of pipeline units, and thus alter the configuration and functionality of the accelerator, by merely coupling or uncoupling pipeline units to or from the bus. This eliminates the need to design or redesign the pipeline-unit interfaces each time one alters one of the pipeline units or alters the number of pipeline units within the accelerator.
摘要翻译：流水线加速器包括总线和多个流水线单元，每个单元耦合到总线并且包括至少一个相应的硬连线流水线电路。通过在流水线加速器中包括多个流水线单元，与单管道单元加速器相比，可以增加加速器的数据处理性能。此外，通过设计流水线单元使得它们通过公共总线进行通信，只需将流水线单元耦合或从母线解耦即可改变流水线单元的数量，从而改变加速器的配置和功能。这样就无需设计或重新设计流水线单元接口，每次更换流水线单元之一或改变加速器中的流水线单元数量。

6. 发明申请

US20060230377A1 Computer-based tool and method for designing an electronic circuit and related system 审中-公开
标题翻译：基于计算机的工具和设计电子电路及相关系统的方法
公开(公告)号：US20060230377A1
公开(公告)日：2006-10-12
申请号：US11243509
申请日：2005-10-03
申请人： John Rapp , Scott Hellenbach , T. Kurian , D. Schooley , Troy Cherasaro
发明人： John Rapp , Scott Hellenbach , T. Kurian , D. Schooley , Troy Cherasaro
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F9/54 , G06F11/1407 , G06F11/1417 , G06F11/142 , G06F11/2025 , G06F11/2028 , G06F11/2035 , G06F11/2038 , G06F11/2051 , G06F13/1694 , G06F15/7867 , G06F15/8053 , G06F17/505 , H04Q9/00
摘要： A computer-based circuit-design tool includes a front end, an interpreter coupled to the front end, and a generator coupled the interpreter. The front end receives symbols that define an algorithm, and the interpreter parses the algorithm into respective algorithm portions. The generator identifies a corresponding circuit template for each of the algorithm portions, each template defining a circuit for executing the respective algorithm portion, and interconnects the identified templates such that the interconnected templates define a circuit that is operable to execute the algorithm. As compared to prior design tools, this tool may decrease the time and effort required to design a circuit for instantiation on a programmable logic integrated circuit (PLIC) or on an application-specific integrated circuit (ASIC) by allowing one to construct the circuit from previously written templates that define previously tested and debugged circuits.
摘要翻译：基于计算机的电路设计工具包括前端，耦合到前端的解释器和耦合解释器的发生器。前端接收定义算法的符号，解释器将算法解析成各自的算法部分。发生器为每个算法部分识别相应的电路模板，每个模板定义用于执行相应算法部分的电路，并且互连所识别的模板，使得互连的模板定义可操作以执行算法的电路。与现有的设计工具相比，该工具可以通过允许一个构造电路从而减少在可编程逻辑集成电路（PLIC）或专用集成电路（ASIC）上设计用于实例化的电路所需的时间和精力以前编写的模板定义了以前测试和调试的电路。

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