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1. 发明申请

US20080209099A1 APPARATUS AND METHODS FOR CLUSTERING MULTIPLE INDEPENDENT PCI EXPRESS HIERARCHIES 有权
标题翻译：用于聚集多个独立PCI表达分层的装置和方法
公开(公告)号：US20080209099A1
公开(公告)日：2008-08-28
申请号：US11680366
申请日：2007-02-28
申请人： John R. Kloeppner , Dennis E. Gates , Robert E. Stubbs , Mohamad H. El-Batal , Russell J. Henry , Charles E. Nichols
发明人： John R. Kloeppner , Dennis E. Gates , Robert E. Stubbs , Mohamad H. El-Batal , Russell J. Henry , Charles E. Nichols
IPC分类号： G06F13/36
CPC分类号： G06F13/4022
摘要： Apparatus, systems and methods for clustering multiple PCI Express hierarchies to enable access of components in different hierarchies. Each PCI Express hierarchy includes a root device as well as a cluster port for coupling each hierarchy to each other hierarchy of a physical cluster through a PCI Express switched fabric. Memory addresses and transaction IDs are re-mapped by the cluster port of each hierarchy to partition the PCI Express space of the system of multiple hierarchies. A first portion of the partitioned space is reserved for access to local components within a hierarchy. A second portion of the space is used to access remote components of other hierarchies from within a different first hierarchy. The address and transaction ID values exchanged in such remote transactions are re-mapped and used by the cluster port of each hierarchy to route exchanges between hierarchies using standard PCIe root devices, endpoint devices, and switches.
摘要翻译：用于聚类多个PCI Express层次结构的装置，系统和方法，以使得能够访问不同层次的组件。每个PCI Express层次结构包括根设备以及通过PCI Express交换结构将每个层次结构耦合到物理集群的每个其他层次结构的集群端口。内存地址和事务ID由每个层次结构的群集端口重新映射，以分区多层次系统的PCI Express空间。保留分区空间的第一部分用于访问层次结构中的本地组件。空间的第二部分用于从不同的第一层次结构中访问其他层次结构的远程组件。在这种远程事务中交换的地址和事务ID值被每个层次结构的集群端口重新映射和使用，以使用标准PCIe根设备，端点设备和交换机在层次结构之间路由交换。

2. 发明授权

US09019708B2 Apparatus and systems having storage devices in a side accessible drive sled 有权
标题翻译：具有存储装置的装置和系统在侧面可接近的驱动滑板中
公开(公告)号：US09019708B2
公开(公告)日：2015-04-28
申请号：US13217650
申请日：2011-08-25
申请人： Macen Shinsato , Mohamad H. El-Batal , Robert E. Stubbs , Jason M. Stuhlsatz , John R. Kloeppner
发明人： Macen Shinsato , Mohamad H. El-Batal , Robert E. Stubbs , Jason M. Stuhlsatz , John R. Kloeppner
IPC分类号： H05K7/16 , H05K5/00 , G06F1/18 , G11B33/12
CPC分类号： G06F1/181 , G06F1/187 , G11B33/128
摘要： Apparatus and systems for improved access to storage devices from the sides of sleds mounted in storage enclosures. Embodiments provide apparatus and systems for a sled in a storage enclosure that provides access to storage devices on either side of the sled when the sled is slid forward out of its enclosure. Multiple sleds may be enclosed within a single enclosure to permit access to a portion of the storage devices in the enclosure hence reducing the problems of instability of the rack if the enclosure is mounted near the top of the rack.
摘要翻译：用于改进从安装在存储外壳中的雪橇侧面进入存储设备的装置和系统。实施例提供了一种用于存储壳体中的滑轨的装置和系统，当滑板向前滑出其外壳时，可提供对滑板两侧的存储设备的访问。多个滑板可以封闭在单个外壳内，以允许访问外壳中的一部分存储设备，从而如果外壳安装在机架顶部附近，则可以减少机架的不稳定性问题。

3. 发明授权

US07562176B2 Apparatus and methods for clustering multiple independent PCI express hierarchies 有权
标题翻译：用于聚类多个独立PCI表现层次的装置和方法
公开(公告)号：US07562176B2
公开(公告)日：2009-07-14
申请号：US11680366
申请日：2007-02-28
申请人： John R. Kloeppner , Dennis E. Gates , Robert E. Stubbs , Mohamad H. El-Batal , Russell J. Henry , Charles E. Nichols
发明人： John R. Kloeppner , Dennis E. Gates , Robert E. Stubbs , Mohamad H. El-Batal , Russell J. Henry , Charles E. Nichols
IPC分类号： G06F13/36 , G06F13/20 , G06F13/00 , G06F15/16
CPC分类号： G06F13/4022
摘要： Apparatus, systems and methods for clustering multiple PCI Express hierarchies to enable access of components in different hierarchies. Each PCI Express hierarchy includes a root device as well as a cluster port for coupling each hierarchy to each other hierarchy of a physical cluster through a PCI Express switched fabric. Memory addresses and transaction IDs are re-mapped by the cluster port of each hierarchy to partition the PCI Express space of the system of multiple hierarchies. A first portion of the partitioned space is reserved for access to local components within a hierarchy. A second portion of the space is used to access remote components of other hierarchies from within a different first hierarchy. The address and transaction ID values exchanged in such remote transactions are re-mapped and used by the cluster port of each hierarchy to route exchanges between hierarchies using standard PCIe root devices, endpoint devices, and switches.
摘要翻译：用于聚类多个PCI Express层次结构的装置，系统和方法，以使得能够访问不同层次的组件。每个PCI Express层次结构包括根设备以及通过PCI Express交换结构将每个层次结构耦合到物理集群的每个其他层次结构的集群端口。内存地址和事务ID由每个层次结构的群集端口重新映射，以分区多层次系统的PCI Express空间。保留分区空间的第一部分用于访问层次结构中的本地组件。空间的第二部分用于从不同的第一层次结构中访问其他层次结构的远程组件。在这种远程事务中交换的地址和事务ID值被每个层次结构的集群端口重新映射和使用，以使用标准PCIe根设备，端点设备和交换机在层次结构之间路由交换。

4. 发明授权

US08756371B2 Methods and apparatus for improved raid parity computation in a storage controller 有权
标题翻译：用于在存储控制器中改进雷达奇偶校验计算的方法和装置
公开(公告)号：US08756371B2
公开(公告)日：2014-06-17
申请号：US13271397
申请日：2011-10-12
申请人： Randy K. Hall , Dennis E. Gates , Randolph W Sterns , John R. Kloeppner , Mohamad H. El-Batal
发明人： Randy K. Hall , Dennis E. Gates , Randolph W Sterns , John R. Kloeppner , Mohamad H. El-Batal
IPC分类号： G06F12/16 , G06F11/10 , G06F11/20 , G06F12/12 , G06F3/06
CPC分类号： G06F11/1076 , G06F3/061 , G06F3/0658 , G06F3/0689 , G06F11/1092 , G06F11/2094 , G06F12/123 , G06F2211/1057 , G06F2211/1059
摘要： Methods and apparatus for improved calculation of redundancy information in RAID storage controllers. Features and aspects hereof provide for a firmware/software element (FPE) for generating redundancy information in combination with a custom logic circuit (HPE) designed to generate redundancy information. A scheduler element operable on a processor of a storage controller along with the FPE determines which of the FPE and HPE is best suited to rapidly complete a new redundancy computation operation and activates or queues the new operation for performance by the selected component.
摘要翻译：改进RAID存储控制器中冗余信息计算的方法和设备。其特征和方面提供了用于产生冗余信息的固件/软件元件（FPE）以及用于生成冗余信息的定制逻辑电路（HPE）。可与FPE一起在存储控制器的处理器上操作的调度器元件确定FPE和HPE中的哪一个最适合于快速完成新的冗余计算操作，并激活或排队新的操作以供所选择的组件执行性能。

5. 发明申请

US20130205065A1 METHODS AND STRUCTURE FOR AN IMPROVED SOLID-STATE DRIVE FOR USE IN CACHING APPLICATIONS 审中-公开
标题翻译：改进的固态驱动器在缓存应用中的使用方法和结构
公开(公告)号：US20130205065A1
公开(公告)日：2013-08-08
申请号：US13365050
申请日：2012-02-02
申请人： John R. Kloeppner , Mohamad H. El-Batal
发明人： John R. Kloeppner , Mohamad H. El-Batal
IPC分类号： G06F12/00
CPC分类号： G06F12/0868 , G06F2212/214 , G11C5/144
摘要： Methods and structure for an improved solid-state drive (SSD) for use in caching applications. An improved SSD comprises both volatile and non-volatile memory. The volatile memory provides improved performance as compared to present SSDs for use in caching application. The improved SSD senses impending failure of external power applied to the SSD and, while adequate power remains, copies cached data from the volatile memory to the non-volatile memory to retain the data through the power loss. In some embodiments, a local power source may be present to assure sufficient time for the SSD to save cached data in the non-volatile memory. Since the volatile memory (e.g., DRAM) is used for the primary caching function and the non-volatile memory is rarely used, performance, reliability and cost goals are achieved for write cache applications.
摘要翻译：用于缓存应用程序的改进固态驱动器（SSD）的方法和结构。改进的SSD包括易失性和非易失性存储器。与用于缓存应用程序的现有SSD相比，易失性存储器提供了改进的性能。改进的SSD感测到施加到SSD的外部电源即将发生的故障，并且在足够的功率保持的情况下，将缓存的数据从易失性存储器复制到非易失性存储器以通过功率损耗来保留数据。在一些实施例中，可以存在本地电源以确保足够的时间来使SSD将缓存的数据保存在非易失性存储器中。由于易失性存储器（例如，DRAM）用于初级高速缓存功能，并且非易失性存储器很少被使用，所以为写入高速缓存应用实现了性能，可靠性和成本目标。

6. 发明申请

US20130050955A1 APPARATUS AND SYSTEMS HAVING STORAGE DEVICES IN A SIDE ACCESSIBLE DRIVE SLED 有权
标题翻译：具有可接受驱动的SLED中的存储设备的设备和系统
公开(公告)号：US20130050955A1
公开(公告)日：2013-02-28
申请号：US13217650
申请日：2011-08-25
申请人： Macen Shinsato , Mohamad H. El-Batal , Robert E. Stubbs , Jason M. Stuhlsatz , John R. Kloeppner
发明人： Macen Shinsato , Mohamad H. El-Batal , Robert E. Stubbs , Jason M. Stuhlsatz , John R. Kloeppner
IPC分类号： H05K7/16
CPC分类号： G06F1/181 , G06F1/187 , G11B33/128
摘要： Apparatus and systems for improved access to storage devices from the sides of sleds mounted in storage enclosures. Embodiments provide apparatus and systems for a sled in a storage enclosure that provides access to storage devices on either side of the sled when the sled is slid forward out of its enclosure. Multiple sleds may be enclosed within a single enclosure to permit access to a portion of the storage devices in the enclosure hence reducing the problems of instability of the rack if the enclosure is mounted near the top of the rack.
摘要翻译：用于改进从安装在存储外壳中的雪橇侧面进入存储设备的装置和系统。实施例提供了一种用于存储壳体中的滑轨的装置和系统，当滑板向前滑出其外壳时，可提供对滑板两侧的存储设备的访问。多个滑板可以封闭在单个外壳内，以允许访问外壳中的一部分存储设备，从而如果外壳安装在机架顶部附近，则可以减少机架的不稳定性问题。

7. 发明申请

US20130097376A1 METHODS AND APPARATUS FOR IMPROVED RAID PARITY COMPUTATION IN A STORAGE CONTROLLER 有权
标题翻译：用于存储控制器中改进的RAID奇偶校验的方法和装置
公开(公告)号：US20130097376A1
公开(公告)日：2013-04-18
申请号：US13271397
申请日：2011-10-12
申请人： Randy K. Hall , Dennis E. Gates , Randolph W. Sterns , John R. Kloeppner , Mohamad H. El-Batal
发明人： Randy K. Hall , Dennis E. Gates , Randolph W. Sterns , John R. Kloeppner , Mohamad H. El-Batal
IPC分类号： G06F12/16
CPC分类号： G06F11/1076 , G06F3/061 , G06F3/0658 , G06F3/0689 , G06F11/1092 , G06F11/2094 , G06F12/123 , G06F2211/1057 , G06F2211/1059
摘要： Methods and apparatus for improved calculation of redundancy information in RAID storage controllers. Features and aspects hereof provide for a firmware/software element (FPE) for generating redundancy information in combination with a custom logic circuit (HPE) designed to generate redundancy information. A scheduler element operable on a processor of a storage controller along with the FPE determines which of the FPE and HPE is best suited to rapidly complete a new redundancy computation operation and activates or queues the new operation for performance by the selected component.
摘要翻译：改进RAID存储控制器中冗余信息计算的方法和设备。其特征和方面提供了用于产生冗余信息的固件/软件元件（FPE）以及用于生成冗余信息的定制逻辑电路（HPE）。可与FPE一起在存储控制器的处理器上操作的调度器元件确定FPE和HPE中的哪一个最适合于快速完成新的冗余计算操作，并激活或排队新的操作以供所选择的组件执行性能。

8. 发明授权

US06356969B1 Methods and apparatus for using interrupt score boarding with intelligent peripheral device 有权
标题翻译：使用智能外设的中断分数登机方法和装置
公开(公告)号：US06356969B1
公开(公告)日：2002-03-12
申请号：US09373864
申请日：1999-08-13
申请人： Rodney A DeKoning , Dennis E. Gates , Keith W. Holt , John R. Kloeppner
发明人： Rodney A DeKoning , Dennis E. Gates , Keith W. Holt , John R. Kloeppner
IPC分类号： G06F1324
CPC分类号： G06F3/0611 , G06F3/0613 , G06F3/0658 , G06F3/0689 , G06F13/24
摘要： In one embodiment, the present invention provides a storage system controller (10) having a main processor (12), a memory (14) and a device interface (18) adapted to interface with a peripheral component (28-32). The controller further includes an interrupt management scoreboard (24) adapted to receive a plurality of writes from the peripheral component(s) prior to interrupting the main processor. The main processor identifies a group of tasks to be executed, and sets up the scoreboard to await the completion of the tasks before interrupting the main processor.
摘要翻译：在一个实施例中，本发明提供一种具有主处理器（12），存储器（14）和适于与外围组件（28-32）接口的设备接口（18）的存储系统控制器（10）。所述控制器还包括适于在中断所述主处理器之前从所述外围组件接收多个写入的中断管理记分板（24）。主处理器识别要执行的一组任务，并设置记分板以等待完成任务，然后中断主处理器。

9. 发明授权

US09110796B2 Apparatus and circuitry for memory-based collection and verification of data integrity information 有权
标题翻译：用于基于存储器的收集和验证数据完整性信息的装置和电路
公开(公告)号：US09110796B2
公开(公告)日：2015-08-18
申请号：US12360193
申请日：2009-01-27
申请人： Dennis E. Gates , John R. Kloeppner
发明人： Dennis E. Gates , John R. Kloeppner
IPC分类号： G06F12/00 , G06F13/00 , G06F11/07 , G06F12/08
CPC分类号： G06F11/0727 , G06F11/0763 , G06F12/0802
摘要： Apparatus and circuitry are provided for supporting collection and/or verification of data integrity information. A circuitry in a storage controller is provided for creating and/or verifying a Data Integrity Block (“DIB”). The circuitry comprises a processor interface for coupling with the processor of the storage controller. The circuitry also comprises a memory interface for coupling with a cache memory of the storage controller. By reading a plurality of Data Integrity Fields (“DIFs”) from the cache memory through the memory interface based on information received from the processor, the DIB is created in that each DIF in the DIB corresponds to a respective data block.
摘要翻译：提供装置和电路用于支持数据完整性信息的收集和/或验证。提供存储控制器中用于创建和/或验证数据完整性块（“DIB”）的电路。电路包括用于与存储控制器的处理器耦合的处理器接口。电路还包括用于与存储控制器的高速缓冲存储器耦合的存储器接口。通过基于从处理器接收的信息通过存储器接口从高速缓冲存储器读取多个数据完整性字段（“DIF”），创建DIB，DIB中的每个DIF对应于相应的数据块。

10. 发明授权

US07676617B2 Posted memory write verification 有权
标题翻译：发布内存写验证
公开(公告)号：US07676617B2
公开(公告)日：2010-03-09
申请号：US12059449
申请日：2008-03-31
申请人： John R. Kloeppner
发明人： John R. Kloeppner
IPC分类号： G06F13/42 , G06F11/00
CPC分类号： G06F13/4243
摘要： A method for verifying the proper communication of data packets from an initiator device on a PCIe data bus to a target device on the data bus. A target-specific counter on the initiator is synchronized to an initiator-specific counter on the target with the same value. The initiator writes the value of the target-specific counter into the tag field of the packet header, and also writes an identifier of the initiator into the header. Then the initiator sends the packet to the target on the PCIe data bus. Upon receipt of the packet, the target reads the identifier and checks the value against the appropriate initiator-specific counter on the target. When the value is not equal to the initiator-specific counter on the target, then it generates an error message. An additional memory write with specific data is posted from the initiator to the target. A memory read is posted of the additional memory write location from the initiator to the target. The operation of the initiator is continued when a good status and data matching the additional write data is returned from the target, and operation is halted when an error status is returned or data that does not match the additional write data.
摘要翻译：一种用于验证数据分组从PCIe数据总线上的发起者设备到数据总线上的目标设备的正确通信的方法。启动器上的目标特定计数器与目标上具有相同值的启动器专用计数器同步。启动器将目标特定计数器的值写入分组报头的标签字段，并将启动器的标识符写入报头。然后，启动器将数据包发送到PCIe数据总线上的目标。在接收到数据包后，目标读取标识符，并根据目标上适当的启动器特定计数器检查该值。当该值不等于目标上的启动器特定计数器时，它会生成错误消息。具有特定数据的附加存储器写入从发起者发布到目标。将附加存储器写入位置从启动器发布到目标的存储器读取。当从目标返回匹配附加写入数据的良好状态和数据时，持续启动器的操作，并且当返回错误状态或与附加写入数据不匹配的数据时停止操作。

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