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1. 发明申请

US20080209099A1 APPARATUS AND METHODS FOR CLUSTERING MULTIPLE INDEPENDENT PCI EXPRESS HIERARCHIES 有权
标题翻译：用于聚集多个独立PCI表达分层的装置和方法
公开(公告)号：US20080209099A1
公开(公告)日：2008-08-28
申请号：US11680366
申请日：2007-02-28
申请人： John R. Kloeppner , Dennis E. Gates , Robert E. Stubbs , Mohamad H. El-Batal , Russell J. Henry , Charles E. Nichols
发明人： John R. Kloeppner , Dennis E. Gates , Robert E. Stubbs , Mohamad H. El-Batal , Russell J. Henry , Charles E. Nichols
IPC分类号： G06F13/36
CPC分类号： G06F13/4022
摘要： Apparatus, systems and methods for clustering multiple PCI Express hierarchies to enable access of components in different hierarchies. Each PCI Express hierarchy includes a root device as well as a cluster port for coupling each hierarchy to each other hierarchy of a physical cluster through a PCI Express switched fabric. Memory addresses and transaction IDs are re-mapped by the cluster port of each hierarchy to partition the PCI Express space of the system of multiple hierarchies. A first portion of the partitioned space is reserved for access to local components within a hierarchy. A second portion of the space is used to access remote components of other hierarchies from within a different first hierarchy. The address and transaction ID values exchanged in such remote transactions are re-mapped and used by the cluster port of each hierarchy to route exchanges between hierarchies using standard PCIe root devices, endpoint devices, and switches.
摘要翻译：用于聚类多个PCI Express层次结构的装置，系统和方法，以使得能够访问不同层次的组件。每个PCI Express层次结构包括根设备以及通过PCI Express交换结构将每个层次结构耦合到物理集群的每个其他层次结构的集群端口。内存地址和事务ID由每个层次结构的群集端口重新映射，以分区多层次系统的PCI Express空间。保留分区空间的第一部分用于访问层次结构中的本地组件。空间的第二部分用于从不同的第一层次结构中访问其他层次结构的远程组件。在这种远程事务中交换的地址和事务ID值被每个层次结构的集群端口重新映射和使用，以使用标准PCIe根设备，端点设备和交换机在层次结构之间路由交换。

2. 发明授权

US06356969B1 Methods and apparatus for using interrupt score boarding with intelligent peripheral device 有权
标题翻译：使用智能外设的中断分数登机方法和装置
公开(公告)号：US06356969B1
公开(公告)日：2002-03-12
申请号：US09373864
申请日：1999-08-13
申请人： Rodney A DeKoning , Dennis E. Gates , Keith W. Holt , John R. Kloeppner
发明人： Rodney A DeKoning , Dennis E. Gates , Keith W. Holt , John R. Kloeppner
IPC分类号： G06F1324
CPC分类号： G06F3/0611 , G06F3/0613 , G06F3/0658 , G06F3/0689 , G06F13/24
摘要： In one embodiment, the present invention provides a storage system controller (10) having a main processor (12), a memory (14) and a device interface (18) adapted to interface with a peripheral component (28-32). The controller further includes an interrupt management scoreboard (24) adapted to receive a plurality of writes from the peripheral component(s) prior to interrupting the main processor. The main processor identifies a group of tasks to be executed, and sets up the scoreboard to await the completion of the tasks before interrupting the main processor.
摘要翻译：在一个实施例中，本发明提供一种具有主处理器（12），存储器（14）和适于与外围组件（28-32）接口的设备接口（18）的存储系统控制器（10）。所述控制器还包括适于在中断所述主处理器之前从所述外围组件接收多个写入的中断管理记分板（24）。主处理器识别要执行的一组任务，并设置记分板以等待完成任务，然后中断主处理器。

3. 发明授权

US09110796B2 Apparatus and circuitry for memory-based collection and verification of data integrity information 有权
标题翻译：用于基于存储器的收集和验证数据完整性信息的装置和电路
公开(公告)号：US09110796B2
公开(公告)日：2015-08-18
申请号：US12360193
申请日：2009-01-27
申请人： Dennis E. Gates , John R. Kloeppner
发明人： Dennis E. Gates , John R. Kloeppner
IPC分类号： G06F12/00 , G06F13/00 , G06F11/07 , G06F12/08
CPC分类号： G06F11/0727 , G06F11/0763 , G06F12/0802
摘要： Apparatus and circuitry are provided for supporting collection and/or verification of data integrity information. A circuitry in a storage controller is provided for creating and/or verifying a Data Integrity Block (“DIB”). The circuitry comprises a processor interface for coupling with the processor of the storage controller. The circuitry also comprises a memory interface for coupling with a cache memory of the storage controller. By reading a plurality of Data Integrity Fields (“DIFs”) from the cache memory through the memory interface based on information received from the processor, the DIB is created in that each DIF in the DIB corresponds to a respective data block.
摘要翻译：提供装置和电路用于支持数据完整性信息的收集和/或验证。提供存储控制器中用于创建和/或验证数据完整性块（“DIB”）的电路。电路包括用于与存储控制器的处理器耦合的处理器接口。电路还包括用于与存储控制器的高速缓冲存储器耦合的存储器接口。通过基于从处理器接收的信息通过存储器接口从高速缓冲存储器读取多个数据完整性字段（“DIF”），创建DIB，DIB中的每个DIF对应于相应的数据块。

4. 发明授权

US06385683B1 Methods and apparatus for raid hardware sequencing to achieve a higher performance raid architecture 有权
标题翻译：用于RAID硬件排序的方法和设备，以实现更高性能的RAID架构
公开(公告)号：US06385683B1
公开(公告)日：2002-05-07
申请号：US09374053
申请日：1999-08-13
申请人： Rodney A. DeKoning , Dennis E. Gates , Keith W. Holt , John R. Kloeppner
发明人： Rodney A. DeKoning , Dennis E. Gates , Keith W. Holt , John R. Kloeppner
IPC分类号： G06F1324
CPC分类号： G06F3/061 , G06F3/0659 , G06F3/0689
摘要： The present invention provides storage system controllers and methods of controlling storage systems therewith. The controller (10) includes a main processor (12), a memory (14), a device interface (18) adapted to interface a peripheral component (28-32), such as a RAID storage device, with the storage system controller, and an operations sequencer (24). The main processor sequences a plurality of tasks to be executed to complete an operation. The operations sequencer coordinates an execution of the plurality of tasks. Methods of the invention include receiving a task status for each of the plurality of tasks that is executed, and issuing an interrupt to the main processor after all of the plurality of tasks of the operation are finished executing. In this manner, the operations sequencer offloads at least some of the main processor overhead to improve processor efficiency.
摘要翻译：本发明提供了存储系统控制器及其控制存储系统的方法。控制器（10）包括主处理器（12），存储器（14），适于将诸如RAID存储设备的外围组件（28-32）与存储系统控制器接口的设备接口（18）和操作定序器（24）。主处理器排列要执行的多个任务以完成操作。操作定序器协调多个任务的执行。本发明的方法包括为所执行的多个任务中的每一个接收任务状态，并且在所有操作的所有任务完成执行之后向主处理器发出中断。以这种方式，操作定序器卸载至少一些主处理器开销以提高处理器效率。

5. 发明授权

US08756371B2 Methods and apparatus for improved raid parity computation in a storage controller 有权
标题翻译：用于在存储控制器中改进雷达奇偶校验计算的方法和装置
公开(公告)号：US08756371B2
公开(公告)日：2014-06-17
申请号：US13271397
申请日：2011-10-12
申请人： Randy K. Hall , Dennis E. Gates , Randolph W Sterns , John R. Kloeppner , Mohamad H. El-Batal
发明人： Randy K. Hall , Dennis E. Gates , Randolph W Sterns , John R. Kloeppner , Mohamad H. El-Batal
IPC分类号： G06F12/16 , G06F11/10 , G06F11/20 , G06F12/12 , G06F3/06
CPC分类号： G06F11/1076 , G06F3/061 , G06F3/0658 , G06F3/0689 , G06F11/1092 , G06F11/2094 , G06F12/123 , G06F2211/1057 , G06F2211/1059
摘要： Methods and apparatus for improved calculation of redundancy information in RAID storage controllers. Features and aspects hereof provide for a firmware/software element (FPE) for generating redundancy information in combination with a custom logic circuit (HPE) designed to generate redundancy information. A scheduler element operable on a processor of a storage controller along with the FPE determines which of the FPE and HPE is best suited to rapidly complete a new redundancy computation operation and activates or queues the new operation for performance by the selected component.
摘要翻译：改进RAID存储控制器中冗余信息计算的方法和设备。其特征和方面提供了用于产生冗余信息的固件/软件元件（FPE）以及用于生成冗余信息的定制逻辑电路（HPE）。可与FPE一起在存储控制器的处理器上操作的调度器元件确定FPE和HPE中的哪一个最适合于快速完成新的冗余计算操作，并激活或排队新的操作以供所选择的组件执行性能。

6. 发明授权

US07913027B2 Configurable storage array controller 有权
标题翻译：可配置存储阵列控制器
公开(公告)号：US07913027B2
公开(公告)日：2011-03-22
申请号：US12419840
申请日：2009-04-07
申请人： John R. Kloeppner , Jeremy D. Stover , Dennis E. Gates , Jason M. Stuhlsatz , Robert E. Stubbs , Mohamad El-Batal
发明人： John R. Kloeppner , Jeremy D. Stover , Dennis E. Gates , Jason M. Stuhlsatz , Robert E. Stubbs , Mohamad El-Batal
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F13/385
摘要： A configurable storage array controller can be configured to either a single-processor configuration or a multi-processor configuration by configuring a data bus switch system.
摘要翻译：可配置的存储阵列控制器可以通过配置数据总线交换机系统来配置为单处理器配置或多处理器配置。

7. 发明授权

US07562176B2 Apparatus and methods for clustering multiple independent PCI express hierarchies 有权
标题翻译：用于聚类多个独立PCI表现层次的装置和方法
公开(公告)号：US07562176B2
公开(公告)日：2009-07-14
申请号：US11680366
申请日：2007-02-28
申请人： John R. Kloeppner , Dennis E. Gates , Robert E. Stubbs , Mohamad H. El-Batal , Russell J. Henry , Charles E. Nichols
发明人： John R. Kloeppner , Dennis E. Gates , Robert E. Stubbs , Mohamad H. El-Batal , Russell J. Henry , Charles E. Nichols
IPC分类号： G06F13/36 , G06F13/20 , G06F13/00 , G06F15/16
CPC分类号： G06F13/4022
摘要： Apparatus, systems and methods for clustering multiple PCI Express hierarchies to enable access of components in different hierarchies. Each PCI Express hierarchy includes a root device as well as a cluster port for coupling each hierarchy to each other hierarchy of a physical cluster through a PCI Express switched fabric. Memory addresses and transaction IDs are re-mapped by the cluster port of each hierarchy to partition the PCI Express space of the system of multiple hierarchies. A first portion of the partitioned space is reserved for access to local components within a hierarchy. A second portion of the space is used to access remote components of other hierarchies from within a different first hierarchy. The address and transaction ID values exchanged in such remote transactions are re-mapped and used by the cluster port of each hierarchy to route exchanges between hierarchies using standard PCIe root devices, endpoint devices, and switches.
摘要翻译：用于聚类多个PCI Express层次结构的装置，系统和方法，以使得能够访问不同层次的组件。每个PCI Express层次结构包括根设备以及通过PCI Express交换结构将每个层次结构耦合到物理集群的每个其他层次结构的集群端口。内存地址和事务ID由每个层次结构的群集端口重新映射，以分区多层次系统的PCI Express空间。保留分区空间的第一部分用于访问层次结构中的本地组件。空间的第二部分用于从不同的第一层次结构中访问其他层次结构的远程组件。在这种远程事务中交换的地址和事务ID值被每个层次结构的集群端口重新映射和使用，以使用标准PCIe根设备，端点设备和交换机在层次结构之间路由交换。

8. 发明授权

US07043622B2 Method and apparatus for handling storage requests 有权
标题翻译：处理存储请求的方法和装置
公开(公告)号：US07043622B2
公开(公告)日：2006-05-09
申请号：US10329184
申请日：2002-12-23
申请人： Russell J. Henry , Bret S. Weber , Dennis E. Gates , John R. Kloeppner , Keith W. Holt
发明人： Russell J. Henry , Bret S. Weber , Dennis E. Gates , John R. Kloeppner , Keith W. Holt
IPC分类号： G06F12/00
CPC分类号： G06F3/0664 , G06F3/0607 , G06F3/0689
摘要： Systems and methods for handling I/O requests from a host system to a storage system. A system includes an I/O module for processing I/O requests from a host system, a virtualized storage element, and a communication medium coupling the I/O module to the virtualized storage elements. The virtualized storage element includes a mapping table for translating virtual storage locations into physical storage locations and a plurality of physical storage locations. The virtualized storage element generates base virtual addresses using the mapping table to communicate the base virtual addresses to the I/O module. The I/O module generates specific virtual addresses using the base virtual addresses and using information derived from the I/O requests. The I/O module uses the specific virtual addresses in communication with the virtualized storage element to identify the physical storage locations in the virtualized storage element.
摘要翻译：用于处理从主机系统到存储系统的I / O请求的系统和方法。系统包括用于处理来自主机系统的I / O请求的I / O模块，虚拟化存储元件以及将I / O模块耦合到虚拟存储元件的通信介质。虚拟化存储元件包括用于将虚拟存储位置转换为物理存储位置和多个物理存储位置的映射表。虚拟化存储元件使用映射表生成基本虚拟地址，以将基本虚拟地址传送到I / O模块。 I / O模块使用基本虚拟地址并使用从I / O请求导出的信息来生成特定的虚拟地址。 I / O模块使用与虚拟化存储元件通信的特定虚拟地址来识别虚拟化存储元件中的物理存储位置。

9. 发明申请

US20130097376A1 METHODS AND APPARATUS FOR IMPROVED RAID PARITY COMPUTATION IN A STORAGE CONTROLLER 有权
标题翻译：用于存储控制器中改进的RAID奇偶校验的方法和装置
公开(公告)号：US20130097376A1
公开(公告)日：2013-04-18
申请号：US13271397
申请日：2011-10-12
申请人： Randy K. Hall , Dennis E. Gates , Randolph W. Sterns , John R. Kloeppner , Mohamad H. El-Batal
发明人： Randy K. Hall , Dennis E. Gates , Randolph W. Sterns , John R. Kloeppner , Mohamad H. El-Batal
IPC分类号： G06F12/16
CPC分类号： G06F11/1076 , G06F3/061 , G06F3/0658 , G06F3/0689 , G06F11/1092 , G06F11/2094 , G06F12/123 , G06F2211/1057 , G06F2211/1059
摘要： Methods and apparatus for improved calculation of redundancy information in RAID storage controllers. Features and aspects hereof provide for a firmware/software element (FPE) for generating redundancy information in combination with a custom logic circuit (HPE) designed to generate redundancy information. A scheduler element operable on a processor of a storage controller along with the FPE determines which of the FPE and HPE is best suited to rapidly complete a new redundancy computation operation and activates or queues the new operation for performance by the selected component.
摘要翻译：改进RAID存储控制器中冗余信息计算的方法和设备。其特征和方面提供了用于产生冗余信息的固件/软件元件（FPE）以及用于生成冗余信息的定制逻辑电路（HPE）。可与FPE一起在存储控制器的处理器上操作的调度器元件确定FPE和HPE中的哪一个最适合于快速完成新的冗余计算操作，并激活或排队新的操作以供所选择的组件执行性能。

10. 发明申请

US20100257301A1 CONFIGURABLE STORAGE ARRAY CONTROLLER 有权
标题翻译：可配置存储阵列控制器
公开(公告)号：US20100257301A1
公开(公告)日：2010-10-07
申请号：US12419840
申请日：2009-04-07
申请人： John R. Kloeppner , Jeremy D. Stover , Dennis E. Gates , Jason M. Stuhlsatz , Robert E. Stubbs , Mohamad El-Batal
发明人： John R. Kloeppner , Jeremy D. Stover , Dennis E. Gates , Jason M. Stuhlsatz , Robert E. Stubbs , Mohamad El-Batal
IPC分类号： G06F13/20 , G06F13/36 , G06F12/14
CPC分类号： G06F13/4022 , G06F13/385
摘要： A configurable storage array controller can be configured to either a single-processor configuration or a multi-processor configuration by configuring a data bus switch system.
摘要翻译：可配置的存储阵列控制器可以通过配置数据总线交换机系统来配置为单处理器配置或多处理器配置。

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