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    • 1. 发明授权
    • Hard disk drive controller employing a plurality of microprocessors
    • 采用多个微处理器的硬盘驱动器控制器
    • US5610808A
    • 1997-03-11
    • US315129
    • 1994-09-29
    • John P. SquiresCharles M. SanderStanton M. KeelerDonald W. Clay
    • John P. SquiresCharles M. SanderStanton M. KeelerDonald W. Clay
    • G06F3/06G05B15/02
    • G06F3/0601G06F3/0613G06F3/0619G06F3/0658G06F3/0676G11B5/5578G06F2003/0692
    • A controller in a hard disk drive system for controlling the transfer of data and control signals between a plurality of host processors and the disk drive system. The disk drive system including storage media, at least one transducer for recording data on and retrieving data from the storage media and an actuator for moving the transducers with respect to the storage media. The controller includes a programmed first microprocessor operating under control of a first operating system stored in a first memory unit associated with the first microprocessor for controlling the recording of data on and the retrieval of data from the storage media, the controlling of the actuator to locate the transducer at and to maintain the transducer at a specified location with respect to the storage media. The controller includes a programmed second microprocessor operating under control of a second operating system stored in a second memory unit associated with the second microprocessor for controlling the transfer of data from a requesting host processor to the disk drive system and the transfer of data recovered from the storage media to a requesting host processor and for generating and communicating parameters to the first microprocessor for defining operations to be performed by the first microprocessor. The second microprocessor operates independently of and concurrently with the first microprocessor and the first microprocessor operates independently of and concurrently with the second microprocessor in exercising operations defined by the parameters received from the second microprocessor.
    • 硬盘驱动器系统中的控制器,用于控制多个主机处理器和磁盘驱动器系统之间的数据和控制信号的传送。 磁盘驱动器系统包括存储介质,用于在存储介质上记录数据和从存储介质检索数据的至少一个换能器和用于相对于存储介质移动换能器的致动器。 控制器包括在第一操作系统的控制下操作的编程的第一微处理器,该第一操作系统存储在与第一微处理器相关联的第一存储器单元中,用于控制数据的记录和从存储介质检索数据,执行器的控制定位 换能器处于和维持换能器相对于存储介质的指定位置。 控制器包括在第二操作系统的控制下操作的编程的第二微处理器,该第二操作系统存储在与第二微处理器相关联的第二存储器单元中,用于控制数据从请求主机处理器传输到磁盘驱动器系统,以及从 存储介质到请求主机处理器,并用于生成和传送参数给第一微处理器,以定义由第一微处理器执行的操作。 第二微处理器独立于第一微处理器工作并与第二微处理器并行运行,并且第一微处理器在由从第二微处理器接收的参数定义的运行中独立于并与第二微处理器一起操作。
    • 2. 发明授权
    • Flexible host interface controller architecture
    • 灵活的主机接口控制器架构
    • US5274773A
    • 1993-12-28
    • US997860
    • 1992-12-29
    • John P. SquiresCharles M. SanderStanton M. KeelerDonald W. Clay
    • John P. SquiresCharles M. SanderStanton M. KeelerDonald W. Clay
    • G06F3/06G06F13/14
    • G06F3/0601G06F2003/0692
    • A high level controller for maintaining communication with a host processor via a host processor interface for establishing communication paths between the host processor interface, an internal processor and a plurality of storage means. A first means receives indicia from the internal processor where the indicia specifies one of the communication paths and generates control signals for forming the specific communication path requested. A second means receives the control signals from the first means and forms the requested communication path. A third means is connected to the first and second means for controlling the communication of the system with the host processor interface in accordance with control signals generated by the first means. In this manner various data paths for communication between the host interface, internal processor and a plurality of storage means may be adaptably specified and formed to make optimum use of the system.
    • 一种用于通过主处理器接口维持与主机处理器的通信的高级控制器,用于建立主处理器接口,内部处理器和多个存储装置之间的通信路径。 第一装置从内部处理器接收标记,其中标记指定通信路径之一,并产生用于形成所请求的特定通信路径的控制信号。 第二装置从第一装置接收控制信号并形成请求的通信路径。 第三装置连接到第一和第二装置,用于根据由第一装置产生的控制信号来控制系统与主处理器接口的通信。 以这种方式,用于主机接口,内部处理器和多个存储装置之间的通信的各种数据路径可以被适应地指定和形成以便最佳地利用系统。
    • 3. 发明授权
    • Multiple microcontroller hard disk drive control architecture
    • 多单片机硬盘驱动器控制架构
    • US5261058A
    • 1993-11-09
    • US27614
    • 1993-03-05
    • John P. SquiresCharles M. SanderStanton M. KeelerDonald W. Clay
    • John P. SquiresCharles M. SanderStanton M. KeelerDonald W. Clay
    • G06F3/06G06F13/14
    • G06F3/0601G06F2003/0692
    • A disk drive architecture controls the transfer of data between a host processor interface and a recording media that includes one or more disk surfaces for storing data. A low-level data controller controls the transfer of data between the disk surfaces and a data buffer. An interface controller controls the transfer of data between the host interface and the data buffer. An arbiter and buffer controller, responsive to data transfer requests from the low-level and interface controllers, arbitrates data storage and retrieval accesses of the data buffer. The low-level and interface controllers operate substantially independent of one another in performing their respective control operations. Consequently, data is transferred bi-directionally through the data buffer at the optimum timing for both controllers.
    • 磁盘驱动器架构控制主机处理器接口和包括用于存储数据的一个或多个磁盘表面的记录介质之间的数据传输。 低级数据控制器控制磁盘表面和数据缓冲区之间的数据传输。 接口控制器控制主机接口和数据缓冲区之间的数据传输。 仲裁器和缓冲器控制器响应于来自低级和接口控制器的数据传输请求,仲裁数据缓冲器的数据存储和检索访问。 低电平和接口控制器在执行各自的控制操作时基本上彼此独立地进行操作。 因此,数据在两个控制器的最佳定时通过数据缓冲器双向传输。
    • 4. 发明授权
    • Disk drive data path integrity control architecture
    • 磁盘驱动器数据路径完整性控制架构
    • US5412666A
    • 1995-05-02
    • US997898
    • 1992-12-29
    • John P. SquiresCharles M. SanderStanton M. KeelerDonald W. Clay
    • John P. SquiresCharles M. SanderStanton M. KeelerDonald W. Clay
    • G06F3/06G06F11/10
    • G06F3/0601G06F3/0613G06F3/0619G06F3/0658G06F3/0676G11B5/5578G06F2003/0692
    • A multi-layer data integrity system for use in a disk drive controller for ensuring the data integrity as data is transferred through the controller and written and fetched from the disk media. The disk drive controller is partitioned into an interface controller and a low level controller where the interface controller controls the transfer of data to and from the host processor and the low level controller controls the recording and reading from the disk media. The interface controller employs a first error encoding and detecting means for encoding the data as originally received from the host processor. The low level controller employs an error encoding and detecting means for encoding both the received data and the encoding data which was appended to the data received by the interface controller. The low level controller's error encoding and detecting means corrects errors detected in recovered data. The interface controller during a fetch operation receives the data from the low level controller and determines if the data is valid and whether the data received from the low level controller was in fact the data being sought by the interface controller.
    • 一种用于磁盘驱动器控制器的多层数据完整性系统,用于确保数据完整性,因为数据通过控制器传输并从磁盘介质中读取和取出。 磁盘驱动器控制器被分为接口控制器和低级控制器,其中接口控制器控制到主处理器和从主处理器传送数据,而低级控制器控制从盘介质的记录和读取。 接口控制器采用第一错误编码和检测装置,用于对从主处理器原来接收到的数据进行编码。 低级别控制器采用错误编码和检测装置,用于对接收到的数据和编码数据进行编码,该编码数据附加到由接口控制器接收的数据。 低电平控制器的错误编码和检测装置纠正在恢复数据中检测到的错误。 提取操作期间的接口控制器从低级别控制器接收数据并确定数据是否有效,以及从低级别控制器接收到的数据是否实际上是由接口控制器寻求的数据。
    • 7. 发明授权
    • Structure and method for storing data on optical disks
    • 用于在光盘上存储数据的结构和方法
    • US06990058B1
    • 2006-01-24
    • US09542681
    • 2000-04-03
    • Curtis M. PleissStanton M. Keeler
    • Curtis M. PleissStanton M. Keeler
    • G11B7/24
    • G11B27/24G11B7/0053G11B7/00745G11B20/14G11B20/18G11B27/3027G11B2220/218G11B2220/2545G11B2220/2562
    • During manufacturing of optical disks, mastering equipment inserts marks (“high frequency wobble marks” or “HFWMs”) into the wobble of the groove on optical disks to store data. The presence of a HFWM at a zero crossing of the wobble indicates an active bit and the absence of the HFWM indicates an inactive bit. The zero crossing is, for example, a negative zero crossing. A matched filter is used to detect the shape of the HFWMs. If a HFWM is detected during a wobble cycle, an active bit is saved in a register or a memory. If a HFWM is not detected during a wobble cycle, an inactive bit is saved in a register or a memory. The active and inactive bits may be coded bits that must be decoded to data bits. The data bits include information such as a synchronization mark, a sector identification data, and an error detection code.
    • 在光盘制造过程中,母盘设备将标记(“高频摇摆标记”或“HFWM”)插入到光盘上凹槽的摆动中以存储数据。 HFWM在摆幅过零点处的存在表示有效位,并且HFWM的不存在表示无效位。 过零点例如是负零交叉。 匹配滤波器用于检测HFWM的形状。 如果在摆动周期期间检测到HFWM,则活动位将保存在寄存器或存储器中。 如果在摆动周期期间未检测到HFWM,则无效位将保存在寄存器或存储器中。 有源和无效位可以是必须被解码为数据位的编码位。 数据位包括诸如同步标记,扇区识别数据和错误检测码之类的信息。
    • 8. 发明授权
    • Skip list management for a write-once optical disk
    • 跳过一次写入光盘的列表管理
    • US06912189B2
    • 2005-06-28
    • US10299950
    • 2002-11-18
    • Michael B. ProppsLane W. LeeStanton M. Keeler
    • Michael B. ProppsLane W. LeeStanton M. Keeler
    • G11B20/18G11B5/09
    • G11B20/1883G11B2020/183G11B2020/1873G11B2020/1896G11B2220/20G11B2220/218
    • A method and system for managing a plurality of defects that may cause an error during a write operation in a write-once data storage disk is provided. A host system sends a write command to a disk drive that contains the storage disk. The process detects any errors that may occur during the write operation. When an error is detected, a “skip list” containing the addresses of physical sectors on the disk that are to be skipped during a read operation is updated, the write operation is suspended, and the process attempts to rewrite the data in another sector. If the rewrite is performed successfully, the write operation continues. Otherwise, the write operation is terminated and the host device is notified. While the disk drive is operative, the skip list is preferably maintained in a buffer memory, but periodically the entries in the skip list are copied to the disk for permanent storage. Before a read operation begins, the skip list is copied from the disk to the memory. When a file is read from the disk, any “skip sectors” that are encompassed within the file are skipped (i.e., the data in those sectors is not read). The method of this invention is particularly useful in supplementing an error correction code, which typically has difficulty dealing with errors of longer duration.
    • 提供了一种用于管理在一次写入数据存储盘中的写入操作期间可能引起错误的多个缺陷的方法和系统。 主机系统向包含存储磁盘的磁盘驱动器发送写入命令。 该过程检测在写入操作期间可能发生的任何错误。 当检测到错误时,更新包含在读取操作期间被跳过的盘上的物理扇区的地址的“跳过列表”,暂停写入操作,并且该过程尝试重写另一扇区中的数据。 如果重写成功执行,写操作将继续。 否则,写入操作被终止并且主机设备被通知。 当磁盘驱动器可操作时,跳过列表优选地保存在缓冲存储器中,但是周期性地将跳过列表中的条目复制到用于永久存储的磁盘。 在读操作开始之前,将跳过列表从磁盘复制到存储器。 当从磁盘读取文件时,跳过文件中包含的任何“跳过扇区”(即,这些扇区中的数据未被读取)。 本发明的方法在补充纠错码中特别有用,纠错码通常难以处理较长持续时间的错误。
    • 9. 发明授权
    • Format for recording data in a storage disk
    • 在存储磁盘中记录数据的格式
    • US06738333B1
    • 2004-05-18
    • US09583448
    • 2000-05-30
    • Daniel R. ZaharrisLane W. LeeStanton M. KeelerMichael B. Propps
    • Daniel R. ZaharrisLane W. LeeStanton M. KeelerMichael B. Propps
    • G11B2736
    • G11B20/00086G11B20/1217G11B20/18
    • A data storage disk includes a writeable area that allows a user to write data, wherein the data files are written from the outside diameter towards the inside diameter of the writeable area, while file system information is written from the inside diameter towards the outside diameter of the writeable area. This optimizes the use of the writeable area, whether a large number of small data files or a small number of large data files are being stored. To further optimize the use of the writeable area, information may be stored in two or more different error correction code (ECC) block sizes. Thus, information, such as the file system attributes and linking sectors, which contains few bytes may be stored in the smaller ECC block size, while the data may be stored in the larger ECC block size. The data storage disk, may also include a mastered content area.
    • 数据存储盘包括允许用户写入数据的可写入区域,其中数据文件从外径朝向可写入区域的内径写入,而文件系统信息从内径向外部直径写入 可写区。 这可以优化可写区域的使用,无论是大量的小数据文件还是少量的大数据文件都被存储。 为了进一步优化可写入区域的使用,可以将信息存储在两个或更多个不同的纠错码(ECC)块大小中。 因此,可以以更小的ECC块大小存储包含少量字节的诸如文件系统属性和链接扇区的信息,而数据可以以较大的ECC块大小存储。 数据存储盘还可以包括已掌握的内容区域。
    • 10. 发明授权
    • Integrated controller/processor for disc drive having direct memory
access
    • 具有直接存储器访问的磁盘驱动器的集成控制器/处理器
    • US06157984A
    • 2000-12-05
    • US856648
    • 1997-05-15
    • Daniel S. FisherStanton M. Keeler
    • Daniel S. FisherStanton M. Keeler
    • G06F3/06G06F12/60
    • G06F3/0614G06F3/0626G06F3/0658G06F3/0676
    • A single chip integrated disc/servo controller and processor (CPU) for a disc drive reduces timing overhead associated with processor/controller/memory communication paths, increases speed, reduces the number of ASIC components, and increases reliability. The processor has a core that can be customized and implemented with appropriate hard disc drive specific controller technology including code or algorithms. Timing overhead associated with the conventional multi-chip communication paths is reduced by the inventive structure as the single on-chip processor has direct access to a buffer memory through a buffer manager within the controller logic. This eliminates the pin and pad delays that are present in conventional implementations. This performance increase has a direct positive impact on disc drive performance generally, and more particularly on disc drive performance when running code from the buffer memory. The structure and method also reduce overhead when communicating with the controller logic, and reduces the delays and other timing overhead associated with accesses to individual storage registers, which are generally slower in the conventional multi-chip configuration than in the single-chip integrated device. Single-chip integration also advantageously reduces product cost by removing one of the ASICs that would otherwise be required for the disc drive electronics. The single chip integration provided by the invention also advantageously includes structural features implemented in sub-micron semiconductor manufacturing technology to provide the aforementioned integration.
    • 用于磁盘驱动器的单芯片集成光盘/伺服控制器和处理器(CPU)可减少与处理器/控制器/存储器通信路径相关的定时开销,提高速度,减少ASIC组件的数量,并提高可靠性。 处理器具有可以通过适当的硬盘驱动器特定控制器技术(包括代码或算法)来定制和实现的核心。 与传统的多芯片通信路径相关联的定时开销由于本发明的结构而减少,因为单个片上处理器通过控制器逻辑内的缓冲器管理器直接访问缓冲存储器。 这消除了传统实现中存在的引脚和焊盘延迟。 这种性能提高对于一般的磁盘驱动器性能具有直接的积极影响,特别是当从缓冲存储器运行代码时的磁盘驱动器性能。 结构和方法还减少了与控制器逻辑通信时的开销,并且减少了与单个存储寄存器的访问相关联的延迟和其他定时开销,这在常规多芯片配置中比在单芯片集成器件中通常较慢。 单芯片集成还有利地通过去除另外一种对于盘驱动电子装置所需的ASIC来降低产品成本。 本发明提供的单芯片集成还有利地包括以亚微米半导体制造技术实现的结构特征,以提供上述集成。