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1. 发明授权

US06229693B1 Articulated display for notebook computer 失效
标题翻译：笔记本电脑的铰接式显示器
公开(公告)号：US06229693B1
公开(公告)日：2001-05-08
申请号：US09282117
申请日：1999-03-31
申请人： John P. Karidis , David Wayne Hill
发明人： John P. Karidis , David Wayne Hill
IPC分类号： G06F116
CPC分类号： G06F1/1616
摘要： A notebook computer has a base, a lid and a display monitor located within the lid. The lid also contains a device which may be used to articulate and support the display in various positions away from the lid that improve viewing for the user under limited or cramped conditions. The device uses a linkage member to pivotally move the display out of the lid, closer to the user, and higher above the base. The linkage locks into place in a conventional lower position and an elevated upper position. After the linkage is locked in the upper position, the display may be tilted to a desired angle. Although the device allows the display angle to be increased well beyond vertical, the display does not obscure the user's view of the keyboard while in this position. In low light conditions, the device also incorporates a light source behind the display for illuminating the keyboard beneath the display.
摘要翻译：笔记本电脑具有底座，盖子和位于盖子内的显示器监视器。盖子还包含一种可用于在远离盖子的各种位置中铰接和支撑显示器的装置，其在有限或狭窄的条件下改善用户观看。该装置使用连杆构件将显示器从盖子枢转地移动到更靠近使用者的位置，并且在基座上方更高。连杆锁定在常规下部位置和升高的上部位置的适当位置。在将连杆锁定在上部位置之后，显示器可以倾斜到期望的角度。虽然该设备允许显示角度远远超过垂直度，但是在该位置时，显示器不会掩盖用户的键盘视图。在低光条件下，该装置还在显示器后面包含一个光源，用于照亮显示屏下面的键盘。

2. 发明授权

US08861266B2 Planar phase-change memory cell with parallel electrical paths 有权
标题翻译：具有并联电路径的平面相变存储单元
公开(公告)号：US08861266B2
公开(公告)日：2014-10-14
申请号：US13619473
申请日：2012-09-14
申请人： Michele M. Franceschini , John P. Karidis
发明人： Michele M. Franceschini , John P. Karidis
IPC分类号： G11C11/00 , H01L45/00 , G11C8/10 , G11C11/56 , G11C13/00
CPC分类号： G11C8/10 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0083 , H01L27/2463 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/1675
摘要： A method for operating a phase change memory that includes initializing a memory cell that includes: a first conductive electrode having a length greater than its width and an axis aligned with the length; a second conductive electrode having an edge oriented at an angle to the axis of the first conductive electrode; an insulator providing a separation distance between an end of the first conductive electrode and the edge of the second conductive electrode; and a phase change material covering a substantial portion of the first conductive electrode and at least a portion of the second conductive electrode. The initializing the memory cell includes creating a first amorphous material region in the phase change material. An active crystalline material region is created inside the first amorphous material region. Information is stored in the memory cell by creating a second amorphous material region inside the active crystalline material region.
摘要翻译：一种用于操作相变存储器的方法，包括初始化存储单元，所述存储单元包括：具有大于其宽度的长度的第一导电电极和与所述长度对准的轴线; 第二导电电极，其具有与第一导电电极的轴成一定角度的边缘; 绝缘体，其在所述第一导电电极的端部和所述第二导电电极的边缘之间提供间隔距离; 以及覆盖所述第一导电电极的主要部分和所述第二导电电极的至少一部分的相变材料。初始化存储单元包括在相变材料中形成第一非晶态材料区域。在第一无定形材料区域内形成活性结晶材料区域。通过在活性结晶材料区域内产生第二非晶态材料区域将信息存储在存储器单元中。

3. 发明授权

US08575008B2 Post-fabrication self-aligned initialization of integrated devices 有权
标题翻译：集成器件的后置自对准初始化
公开(公告)号：US08575008B2
公开(公告)日：2013-11-05
申请号：US12873058
申请日：2010-08-31
申请人： Michele M. Franceschini , John P. Karidis
发明人： Michele M. Franceschini , John P. Karidis
IPC分类号： H01L21/00
CPC分类号： H01L45/126 , H01L45/04 , H01L45/1226 , H01L45/144
摘要： Creating a localized region of material having a target chemical composition by defining an electrical circuit on a substrate, and depositing on the electrical circuit one or more layers of materials having one or more chemical compositions. An electrical current pulse is applied to the electrical circuit to create a self-aligned localized region having the target chemical composition. Applying the electrical current pulse causes a portion of the one or more layers of materials to be heated, resulting in the target chemical composition.
摘要翻译：通过在基板上限定电路来形成具有目标化学成分的材料的局部区域，以及在电路上沉积具有一种或多种化学成分的一层或多层材料。电流脉冲施加到电路以产生具有目标化学成分的自对准局部区域。施加电流脉冲导致一层或多层材料的一部分被加热，导致目标化学成分。

4. 发明授权

US08341501B2 Adaptive endurance coding of non-volatile memories 有权
标题翻译：非易失性存储器的适应性耐力编码
公开(公告)号：US08341501B2
公开(公告)日：2012-12-25
申请号：US12433669
申请日：2009-04-30
申请人： Michele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano
发明人： Michele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano
IPC分类号： H03M13/00 , G11C29/00
CPC分类号： G06F12/0246 , G06F11/1012 , G06F2212/1036 , G06F2212/401 , G06F2212/403 , G06F2212/7207 , G11C16/349
摘要： Adaptive endurance coding including a method for storing data that includes receiving write data and a write address. A compression algorithm is applied to the write data to generate compressed data. An endurance code is applied to the compressed data to generate a codeword. The endurance code is selected and applied in response to the amount of space saved by applying the compression to the write data. The codeword is written to the write address.
摘要翻译：自适应耐力编码包括用于存储包括接收写入数据和写入地址的数据的方法。将压缩算法应用于写入数据以生成压缩数据。将耐力码应用于压缩数据以产生码字。响应于通过将压缩应用于写数据而节省的空间量来选择和应用耐久代码。代码字被写入写入地址。

5. 发明申请

US20120311262A1 MEMORY CELL PRESETTING FOR IMPROVED MEMORY PERFORMANCE 审中-公开
标题翻译：用于改善记忆性能的存储单元预置
公开(公告)号：US20120311262A1
公开(公告)日：2012-12-06
申请号：US13151043
申请日：2011-06-01
申请人： Michele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano , Moinuddin K. Qureshi
发明人： Michele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano , Moinuddin K. Qureshi
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/00 , G06F12/08 , G06F12/0802 , G06F12/0891
摘要： Memory cell presetting for improved performance including a system that includes a memory, a cache, and a memory controller. The memory includes memory lines made up of memory cells. The cache includes cache lines that correspond to a subset of the memory lines. The memory controller is in communication with the memory and the cache. The memory controller is configured to perform a method that includes scheduling a request to set memory cells of a memory line to a common specified state in response to a cache line attaining a dirty state.
摘要翻译：用于改进性能的存储单元预置，包括包括存储器，高速缓存和存储器控制器的系统。存储器包括由存储单元组成的存储器线。缓存包括对应于存储器线的子集的高速缓存行。存储器控制器与存储器和缓存器通信。存储器控制器被配置为执行一种方法，该方法包括根据达到肮脏状态的高速缓存线来调度将存储器线的存储单元设置为公共指定状态的请求。

6. 发明授权

US08230276B2 Writing to memory using adaptive write techniques 有权
标题翻译：使用自适应写入技术写入内存
公开(公告)号：US08230276B2
公开(公告)日：2012-07-24
申请号：US12568035
申请日：2009-09-28
申请人： Stefanie Chiras , Michele Franceschini , John P. Karidis , Luis A. Lastras , Mayank Sharma
发明人： Stefanie Chiras , Michele Franceschini , John P. Karidis , Luis A. Lastras , Mayank Sharma
IPC分类号： G11C29/00
CPC分类号： G11C13/0004 , G11C13/0069 , G11C16/10 , G11C16/3459 , G11C2013/0076
摘要： Techniques for writing to memory using adaptive write techniques. An adaptive write technique includes receiving at a computer a message including a plurality of symbols. The message is written to a memory. The writing to memory includes performing for each symbol in the message: writing a data value to a memory location in the memory and reading contents of the memory location after the data value has been written. The data value is determined at the computer in response to the symbol and to the contents of any memory locations previously read as part of writing the message to the memory. It is determined at the computer if the contents of the memory locations reflect the message. The writing is restarted at the computer in response to determining that the contents of the memory locations do not reflect the message.
摘要翻译：使用自适应写入技术写入存储器的技术。一种自适应写入技术包括在计算机处接收包括多个符号的消息。消息被写入存储器。对存储器的写入包括对消息中的每个符号执行：将数据值写入存储器中的存储器位置，并且在写入数据值之后读取存储器位置的内容。数据值在计算机响应于符号以及先前读取的任何存储器位置的内容来确定，作为将消息写入存储器的一部分。在计算机中确定存储器位置的内容是否反映消息。响应于确定存储器位置的内容不反映消息，在计算机上重新开始写入。

7. 发明授权

US08144508B2 Memory reading method for resistance drift mitigation 有权
标题翻译：电阻漂移缓解的记忆读取方法
公开(公告)号：US08144508B2
公开(公告)日：2012-03-27
申请号：US12984682
申请日：2011-01-05
申请人： Michele M. Franceschini , John P. Karidis , Luis A. Lastras
发明人： Michele M. Franceschini , John P. Karidis , Luis A. Lastras
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0033 , G11C2013/0052
摘要： Techniques for reading phase change memory that mitigate resistance drift. One contemplated method includes apply a plurality of electrical input signals to the memory cell. The method includes measuring a plurality of electrical output signals from the memory cell resulting from the plurality of electrical input signals. The method includes calculating an invariant component of the plurality of electrical output signals dependent on the configuration of amorphous material in the memory cell. The method also includes determining a memory state of the memory cell based on the invariant component. In one embodiment of the invention, the method further includes mapping the plurality of electrical output signals to a measurements region of a plurality of measurements regions. The measurements regions correspond to memory states of the memory cell.
摘要翻译：读取相变存储器的技术，减轻电阻漂移。一种预期的方法包括将多个电输入信号应用于存储器单元。该方法包括从多个电输入信号测量来自存储器单元的多个电输出信号。该方法包括根据存储单元中非晶材料的配置来计算多个电输出信号的不变分量。该方法还包括基于不变分量来确定存储器单元的存储器状态。在本发明的一个实施例中，该方法还包括将多个电输出信号映射到多个测量区域的测量区域。测量区域对应于存储器单元的存储器状态。

8. 发明申请

US20110317481A1 PLANAR PHASE-CHANGE MEMORY CELL WITH PARALLEL ELECTRICAL PATHS 有权
标题翻译：平面相变存储器单元并联电路
公开(公告)号：US20110317481A1
公开(公告)日：2011-12-29
申请号：US12823924
申请日：2010-06-25
申请人： Michele M. Franceschini , John P. Karidis
发明人： Michele M. Franceschini , John P. Karidis
IPC分类号： G11C11/00 , G06F17/50 , H01L45/00
CPC分类号： G11C8/10 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0083 , H01L27/2463 , H01L45/06 , H01L45/1226 , H01L45/144 , H01L45/1675
摘要： A planar phase change memory cell with parallel electrical paths. The memory cell includes a first conductive electrode region having a length greater than its width and an axis aligned with the length. The memory cell also includes a second conductive electrode region having an edge oriented at an angle to the axis of the first conductive electrode region. The memory cell further includes an insulator region providing a lateral separation distance between an end of the first conductive electrode region and the edge of the second conductive electrode region, the insulator region including at least part of an insulator film and the lateral separation distance is responsive to the thickness of the insulator film.
摘要翻译：具有并联电路径的平面相变存储单元。存储单元包括具有大于其宽度的长度的第一导电电极区域和与该长度对准的轴线。存储单元还包括具有与第一导电电极区域的轴成一定角度的边缘的第二导电电极区域。存储单元还包括绝缘体区域，其在第一导电电极区域的端部和第二导电电极区域的边缘之间提供横向间隔距离，绝缘体区域包括绝缘膜的至少一部分，并且横向间隔距离是响应的到绝缘膜的厚度。

9. 发明授权

US08011563B2 Compliant mold fill head with integrated cavity venting and solder cooling 有权
标题翻译：具有集成腔体排气和焊锡冷却的合适的模具填充头
公开(公告)号：US08011563B2
公开(公告)日：2011-09-06
申请号：US11696753
申请日：2007-04-05
申请人： Russell A. Budd , Evan G. Colgan , Peter A. Gruber , Gareth G. Hougham , John P. Karidis
发明人： Russell A. Budd , Evan G. Colgan , Peter A. Gruber , Gareth G. Hougham , John P. Karidis
IPC分类号： B23K31/02 , B23K37/00
CPC分类号： B23K3/0607 , B23K2101/40
摘要： A mold fill head includes a solder delivery head and an interface portion having a compliant portion secured to the solder delivery head and a dispensing region associated with the compliant portion. The dispensing region is formed with at least one aperture configured to interface with cavities in a mold plate, the at least one aperture being in fluid communication with the solder delivery head. The compliant portion is configured and dimensioned to urge the dispensing region against the mold plate when held a predetermined distance therefrom and to substantially tolerate variations in flatness of the mold plate, variations in the predetermined distance, and/or variations in an angular orientation of the interface portion and the mold plate.
摘要翻译：模具填充头包括焊料输送头和具有固定到焊料输送头的顺应部分和与柔顺部分相关联的分配区域的界面部分。分配区域形成有至少一个孔，其被配置为与模板中的空腔相接触，所述至少一个孔与焊料输送头流体连通。顺应部分的构造和尺寸被设计成当从其延伸预定距离时将分配区域推靠在模板上，并且基本上容许模板的平坦度变化，预定距离的变化和/或角度取向的变化界面部分和模板。

10. 发明申请

US20110078392A1 WRITING TO MEMORY USING ADAPTIVE WRITE TECHNIQUES 有权
标题翻译：使用自适应写入技术写入记忆
公开(公告)号：US20110078392A1
公开(公告)日：2011-03-31
申请号：US12568035
申请日：2009-09-28
申请人： Stefanie Chiras , Michele Franceschini , John P. Karidis , Luis A. Lastras , Mayank Sharma
发明人： Stefanie Chiras , Michele Franceschini , John P. Karidis , Luis A. Lastras , Mayank Sharma
IPC分类号： G06F12/00
CPC分类号： G11C13/0004 , G11C13/0069 , G11C16/10 , G11C16/3459 , G11C2013/0076
摘要： Techniques for writing to memory using adaptive write techniques. An adaptive write technique includes receiving at a computer a message including a plurality of symbols. The message is written to a memory. The writing to memory includes performing for each symbol in the message: writing a data value to a memory location in the memory and reading contents of the memory location after the data value has been written. The data value is determined at the computer in response to the symbol and to the contents of any memory locations previously read as part of writing the message to the memory. It is determined at the computer if the contents of the memory locations reflect the message. The writing is restarted at the computer in response to determining that the contents of the memory locations do not reflect the message.
摘要翻译：使用自适应写入技术写入存储器的技术。自适应写入技术包括在计算机处接收包括多个符号的消息。消息被写入存储器。对存储器的写入包括对消息中的每个符号执行：将数据值写入存储器中的存储器位置，并且在写入数据值之后读取存储器位置的内容。数据值在计算机响应于符号以及先前读取的任何存储器位置的内容来确定，作为将消息写入存储器的一部分。在计算机中确定存储器位置的内容是否反映消息。响应于确定存储器位置的内容不反映消息，在计算机上重新开始写入。

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