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1. 发明申请

US20050038978A1 Reconfigurable processing system and method 审中-公开
公开(公告)号：US20050038978A1
公开(公告)日：2005-02-17
申请号：US10946924
申请日：2004-09-22
申请人： John Nickolls , Scott Johnson , Mark Williams , Ethan Mirsky , Kambdur Kirthiranjan , Amrit Pant , Lawrence Madar
发明人： John Nickolls , Scott Johnson , Mark Williams , Ethan Mirsky , Kambdur Kirthiranjan , Amrit Pant , Lawrence Madar
IPC分类号： G06F9/302 , G06F9/318 , G06F9/32 , G06F9/345 , G06F15/78 , G06F15/00
CPC分类号： G06F9/3001 , G06F9/30181 , G06F9/325 , G06F9/345 , G06F9/3455 , G06F15/8061
摘要： A reconfigurable processing system executes instructions and configurations in parallel. Initially, a first instruction loads configurations into configuration registers. The configuration field of a subsequently fetched instruction selects a configuration register. The instruction controls and controls of the configuration in the selected configuration register are decoded and modified as specified by the instruction. The controls provide data operands to the execution units which process the operands and generate results. Scalar data, vector data, or a combination of scalar and vector data can be processed. The processing is controlled by instructions executed in parallel with configurations invoked by configuration fields within the instructions. Vectors are processed using a vector register file which stores vectors. A vector address unit identifies addresses of vector elements in the vector register file to be processed. For each vector, vector address units provide addresses which stride through each element of each vector.

2. 发明授权

US06959378B2 Reconfigurable processing system and method 有权
标题翻译：可重构的处理系统和方法
公开(公告)号：US06959378B2
公开(公告)日：2005-10-25
申请号：US10004246
申请日：2001-11-02
申请人： John R. Nickolls , Scott D. Johnson , Mark Williams , Ethan Mirsky , Kambdur Kirthiranjan , Amrit Raj Pant , Lawrence J. Madar, III
发明人： John R. Nickolls , Scott D. Johnson , Mark Williams , Ethan Mirsky , Kambdur Kirthiranjan , Amrit Raj Pant , Lawrence J. Madar, III
IPC分类号： G06F9/302 , G06F9/318 , G06F9/32 , G06F9/345 , G06F15/78 , G06F9/30 , G06F19/00
CPC分类号： G06F9/3001 , G06F9/30181 , G06F9/325 , G06F9/345 , G06F9/3455 , G06F15/8061
摘要： A reconfigurable processing system executes instructions and configurations in parallel. Initially, a first instruction loads configurations into configuration registers. The configuration field of a subsequently fetched instruction selects a configuration register. The instruction controls and controls of the configuration in the selected configuration register are decoded and modified as specified by the instruction. The controls provide data operands to the execution units which process the operands and generate results. Scalar data, vector data, or a combination of scalar and vector data can be processed. The processing is controlled by instructions executed in parallel with configurations invoked by configuration fields within the instructions. Vectors are processed using a vector register file which stores vectors. A vector address unit identifies addresses of vector elements in the vector register file to be processed. For each vector, vector address units provide addresses which stride through each element of each vector.
摘要翻译：可重构处理系统并行执行指令和配置。最初，第一条指令将配置加载到配置寄存器中。随后取出的指令的配置字段选择配置寄存器。所选配置寄存器中的配置的指令控制和控制按照指令进行解码和修改。控件向处理操作数并生成结果的执行单元提供数据操作数。可以处理标量数据，向量数据或标量和向量数据的组合。处理由与指令中的配置字段调用的配置并行执行的指令控制。使用存储向量的向量寄存器文件处理向量。向量地址单元标识要处理的向量寄存器文件中的向量元素的地址。对于每个向量，向量地址单元提供跨越每个向量的每个元素的地址。

3. 发明申请

US20140329326A1 SYNTHETIC GENE CLUSTERS 有权
标题翻译：合成基因组
公开(公告)号：US20140329326A1
公开(公告)日：2014-11-06
申请号：US14126307
申请日：2012-06-14
申请人： Ethan Mirsky , Karsten Temme , Christopher A. Voigt , Dehua Zhao
发明人： Ethan Mirsky , Karsten Temme , Christopher A. Voigt , Dehua Zhao
IPC分类号： C12N15/63
CPC分类号： C12N15/635 , C07K14/255 , C07K14/26 , C12N9/0095 , C12N15/52 , C12N15/63 , C12N15/67 , C12N15/74 , C12Y118/06001 , G06F19/20 , G06F19/22
摘要： Methods for making synthetic gene clusters are described.
摘要翻译：描述制备合成基因簇的方法。

4. 发明授权

US07188192B2 Controlling multiple context processing elements based on transmitted message containing configuration data, address mask, and destination indentification 有权
标题翻译：基于包含配置数据，地址掩码和目的地识别的传输消息控制多个上下文处理元素
公开(公告)号：US07188192B2
公开(公告)日：2007-03-06
申请号：US10838071
申请日：2004-05-03
申请人： Ethan Mirsky , Robert French , Ian Eslick
发明人： Ethan Mirsky , Robert French , Ian Eslick
IPC分类号： G06F15/163
CPC分类号： G06F9/3885 , G06F15/7867 , G06F15/8007
摘要： A method and apparatus for providing local control of processing elements in a network of multiple context processing elements (MCPEs). A MCPE stores configuration memory contexts and maintains data of a current configuration. State information is received from at least one other MCPE. A configuration control signal is generated in response to the state information and current configuration data. A MCPE is selected in response to the configuration control signal to control the MCPE. Each MCPE in the networked array has an assigned physical and virtual identification. Data comprising control data, configuration data, an address mask, and a destination identification is transmitted to a MCPE. The transmitted address mask is applied to either a physical or a virtual identification, and to a destination identification. The masked physical or virtual identification is compared to the masked destination identification. When the masked physical or virtual identification matches the masked destination identification, a MCPE is manipulated in response to the transmitted data by selecting one of a number of configuration memory contexts to control the functioning of the MCPE.
摘要翻译：一种用于在多个上下文处理元件（MCPE）的网络中提供处理元件的本地控制的方法和装置。 MCPE存储配置存储器上下文并维护当前配置的数据。从至少一个其他MCPE接收状态信息。响应于状态信息和当前配置数据产生配置控制信号。选择MCPE以响应配置控制信号来控制MCPE。网络阵列中的每个MCPE都有一个分配的物理和虚拟标识。包含控制数据，配置数据，地址掩码和目的地标识的数据被发送到MCPE。发送的地址掩码被应用于物理或虚拟标识以及目的地标识。将屏蔽的物理或虚拟标识与掩蔽的目的地标识进行比较。当屏蔽的物理或虚拟标识与掩蔽的目的地标识匹配时，通过选择多个配置存储器上下文中的一个来控制MCPE的功能来响应于所发送的数据来操纵MCPE。

5. 发明授权

US07266672B2 Method and apparatus for retiming in a network of multiple context processing elements 失效
标题翻译：用于在多个上下文处理元件的网络中重定时的方法和装置
公开(公告)号：US07266672B2
公开(公告)日：2007-09-04
申请号：US10320018
申请日：2002-12-16
申请人： Ethan Mirsky , Robert French , Ian Eslick
发明人： Ethan Mirsky , Robert French , Ian Eslick
IPC分类号： G06F15/80 , G06F15/177
CPC分类号： G06F15/8007 , G06F15/8023
摘要： A method and an apparatus for retiming in a network of multiple context processing elements in a network of multiple context processing elements are provided. A programmable delay element is configured to programmably delay signals between a number of multiple context processing elements of an array without requiring a multiple context processing element to implement the delay. The output of a first multiple context processing element is coupled to a first multiplexer and to the input of a number of serially connected delay registers. The output of each of the serially connected registers is coupled to the input of a second multiplexer. The output of the second multiplexer is coupled to the input of the first multiplexer, and the output of the first multiplexer is coupled to a second multiple context processing element. The first and second multiplexers are provided with at least one set of data representative of at least one configuration memory context of a multiple context processing element. The first and second multiplexers are controlled to select one of a number of delay durations in response to the received set of data. A delay is programmed in the network structure in response to a data type being transferred between particular multiple context processing elements.
摘要翻译：提供了一种用于在多个上下文处理元件的网络中的多个上下文处理元件的网络中重定时的方法和装置。可编程延迟元件被配置为可编程地延迟阵列的多个上下文处理元件之间的信号，而不需要多个上下文处理元件来实现延迟。第一多重上下文处理元件的输出耦合到第一多路复用器和多个串行连接的延迟寄存器的输入。每个串行连接的寄存器的输出耦合到第二多路复用器的输入端。第二多路复用器的输出耦合到第一多路复用器的输入，第一多路复用器的输出耦合到第二多重上下文处理元件。第一和第二多路复用器被提供有表示多个上下文处理元件的至少一个配置存储器上下文的至少一组数据。控制第一和第二多路复用器以响应于所接收的数据集来选择多个延迟持续时间中的一个。响应于在特定多个上下文处理元件之间传送的数据类型，在网络结构中编程延迟。

6. 发明授权

US06976141B2 Pipelined multi-access memory apparatus and method 有权
标题翻译：流水线多路存储设备及方法
公开(公告)号：US06976141B2
公开(公告)日：2005-12-13
申请号：US10002449
申请日：2001-11-02
申请人： Lawrence J. Madar, III , John R. Nickolls , Ethan Mirsky
发明人： Lawrence J. Madar, III , John R. Nickolls , Ethan Mirsky
IPC分类号： G06F12/00 , G06F13/16
CPC分类号： G06F13/1615
摘要： A memory management system provides the ability for multiple requesters to access blocks of memory in a pipelined manner. During a first clock, requests for one or more of the memory blocks are received by the system. A determination is made of whether one of the memory blocks is requested by one or more requests. If the same memory block is requested by two or more requests, the system performs a further determination of which of the requests will be provided to the memory block. The determined request is provided to the memory block on the first clock. During a second clock, the data of the determined request is latched to the memory block and a memory access is initiated. If the request is a write request, the data is written to the memory block. If the request is a read request, then the requested data is retrieved and, on a third clock, the data is driven onto a bus, routed to the determined requester, and available to be latched into the requester on the fourth clock.
摘要翻译：存储器管理系统提供了多个请求者以流水线方式访问存储块的能力。在第一时钟期间，系统接收对一个或多个存储器块的请求。确定一个或多个请求是否请求一个存储器块。如果由两个或更多个请求请求相同的存储器块，则系统进一步确定哪个请求将被提供给存储器块。所确定的请求被提供给第一时钟上的存储器块。在第二时钟期间，确定的请求的数据被锁存到存储器块，并且启动存储器访问。如果请求是写请求，则将数据写入存储块。如果请求是读请求，则检索所请求的数据，并且在第三时钟将数据驱动到总线上，路由到确定的请求者，并且可以在第四时钟被锁存到请求者中。

7. 发明授权

US6108760A Method and apparatus for position independent reconfiguration in a network of multiple context processing elements 失效
标题翻译：用于在多个上下文处理元件的网络中用于位置无关重新配置的方法和装置
公开(公告)号：US6108760A
公开(公告)日：2000-08-22
申请号：US962187
申请日：1997-10-31
申请人： Ethan Mirsky , Robert French , Ian Eslick
发明人： Ethan Mirsky , Robert French , Ian Eslick
IPC分类号： G06F13/40 , G06F15/80 , G06F12/08
CPC分类号： G06F13/4022 , G06F15/8007
摘要： A method and an apparatus for position independent reconfiguration in a network of multiple context processing elements are provided. Wach multiple context processing element in a networked array of multiple context processing elements has an assigned physical identification. Virtual identifications may also be assigned to a number of the multiple context processing elements. Data is transmitted to at least one of the multiple context processing elements of the array, the data comprising control data, configuration data, an address mask, and a destination identification. The transmitted address mask is applied to either the physical or virtual identification and to a destination identification. The masked physical or virtual identification is compared to the masked destination identification. When the masked physical or virtual identification of a multiple context processing element matches the masked destination identification, at least one of the number of multiple context processing elements are manipulated in response to the transmitted data. Manipulation comprises programming a multiple context processing element with at least one configuration memory context and selecting a configuration memory context to control the functioning of the multiple context processing element.
摘要翻译：提供了一种在多个上下文处理元件的网络中用于位置无关重新配置的方法和装置。在多个上下文处理元件的网络阵列中的多个上下文处理元素具有分配的物理标识。虚拟标识也可以被分配给多个上下文处理元件的数量。数据被发送到阵列的多个上下文处理元件中的至少一个，数据包括控制数据，配置数据，地址掩码和目的地标识。发送的地址掩码应用于物理或虚拟标识和目标标识。将屏蔽的物理或虚拟标识与掩蔽的目的地标识进行比较。当多个上下文处理元件的掩蔽的物理或虚拟标识匹配掩蔽的目的地标识符时，多个上下文处理元件的数目中的至少一个被响应于发送的数据被操纵。操作包括使用至少一个配置存储器上下文编程多个上下文处理元件，并且选择配置存储器上下文来控制多个上下文处理元件的功能。

8. 发明授权

US06745317B1 Three level direct communication connections between neighboring multiple context processing elements 失效
标题翻译：相邻多个上下文处理元素之间的三级直接通信连接
公开(公告)号：US06745317B1
公开(公告)日：2004-06-01
申请号：US09364838
申请日：1999-07-30
申请人： Ethan Mirsky , Robert French , Ian Eslick
发明人： Ethan Mirsky , Robert French , Ian Eslick
IPC分类号： G06F1517
CPC分类号： G06F15/8023
摘要： A method and an apparatus for configuration of multiple context processing elements (MCPEs)are described. According to one aspect of the invention, the structure that joins the MCPE cores into a complete array in one embodiment is actually a set of several mesh-like interconnect structures. Each interconnect structure forms a network, and each network is independent in that it uses different paths, but the networks join at MCPE input switches. The network structure of one embodiment of the present invention is comprised of a local area broadcast network (level 1), a switched interconnect network (level 2), a shared bus network (level 3), and a broadcast network. In one embodiment, the level 3 network is used to carry configuration data for the MCPEs while the broadcast network is used to carry configuration data for the level 3 network drivers and switches. In one embodiment, the level 3 network is bidirectional and dynamically routable.
摘要翻译：描述了用于配置多个上下文处理元件（MCPE）的方法和装置。根据本发明的一个方面，在一个实施例中将MCPE核心连接成完整阵列的结构实际上是一组几个网状互连结构。每个互连结构形成网络，并且每个网络是独立的，因为它使用不同的路径，但是网络在MCPE输入交换机处连接。本发明的一个实施例的网络结构包括局域广播网络（1级），交换互连网络（2级），共享总线网络（3级）和广播网络。在一个实施例中，级别3网络用于承载MCPE的配置数据，而广播网络用于承载3级网络驱动器和交换机的配置数据。在一个实施例中，3级网络是双向的并且是可动态路由的。

9. 发明授权

US06266760B1 Intermediate-grain reconfigurable processing device 失效
标题翻译：中粒重配置处理装置
公开(公告)号：US06266760B1
公开(公告)日：2001-07-24
申请号：US09292497
申请日：1999-04-15
申请人： André DeHon , Ethan Mirsky , Thomas F. Knight, Jr.
发明人： André DeHon , Ethan Mirsky , Thomas F. Knight, Jr.
IPC分类号： G06F1516
CPC分类号： G06F15/8023
摘要： A programmable integrated circuit utilizes a large number of intermediate-grain processing elements which are multibit processing units arranged in a configurable mesh. The coarse-grain resources, such as memory and processing, are deployable in a way that takes advantage of the opportunities for optimization present in given problems. To accomplish this, the interconnect supports three different modes of operation: a static value in which a value set by the configuration data is provided to a functional unit, static source in which another functional unit serves as the value source, and a dynamic source mode in which the source is determined by the value from another functional unit.
摘要翻译：可编程集成电路利用大量的中间粒度处理元件，它们是以可配置的网格布置的多位处理单元。诸如内存和处理之类的粗粮资源可以利用在给定问题中存在的优化机会的方式进行部署。为了实现这一点，互连支持三种不同的操作模式：将由配置数据设置的值提供给功能单元的静态值，其他功能单元用作值源的静态源，以及动态源模式其中源由另一功能单元的值确定。

10. 发明授权

US5956518A Intermediate-grain reconfigurable processing device 失效
公开(公告)号：US5956518A
公开(公告)日：1999-09-21
申请号：US632371
申请日：1996-04-11
申请人： Andre DeHon , Ethan Mirsky , Thomas F. Knight, Jr.
发明人： Andre DeHon , Ethan Mirsky , Thomas F. Knight, Jr.
IPC分类号： G06F15/80
CPC分类号： G06F15/8023
摘要： A programmable integrated circuit utilizes a large number of intermediate-grain processing elements which are multibit processing units arranged in a configurable mesh. The coarse-grain resources, such as memory and processing, are deployable in a way that takes advantage of the opportunities for optimization present in given problems. To accomplish this, the interconnect supports three different modes of operation: a static value in which a value set by the configuration data is provided to a functional unit, static source in which another functional unit serves as the value source, and a dynamic source mode in which the source is determined by the value from another functional unit.

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