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1. 发明申请

US20050289440A1 System and method for controlling application of an error correction code (ECC) algorithm in a memory subsystem 有权
标题翻译：用于在存储器子系统中控制纠错码（ECC）算法的应用的系统和方法
公开(公告)号：US20050289440A1
公开(公告)日：2005-12-29
申请号：US10879262
申请日：2004-06-29
申请人： John Nerl , Ken Pomaranski , Gary Gostin , Andrew Walton , David Soper
发明人： John Nerl , Ken Pomaranski , Gary Gostin , Andrew Walton , David Soper
IPC分类号： G11C29/00
CPC分类号： G06F11/1012
摘要： In one embodiment of the invention, a computer readable medium, comprising executable instructions for controlling application of an error correction code (ECC) algorithm in a memory subsystem, comprises code for recording occurrences of data corruption in data retrieved from the memory subsystem, code for analyzing the occurrences of data corruption to detect a repeated bit pattern of data corruption across different addresses of the memory subsystem, and code for controlling application of the ECC algorithm to erase bits associated with a repeated bit pattern, detected by the code for analyzing, from data retrieved from the memory subsystem.
摘要翻译：在本发明的一个实施例中，包括用于控制存储器子系统中的纠错码（ECC）算法的应用的可执行指令的计算机可读介质包括用于记录从存储器子系统检索的数据中的数据损坏的发生的代码，分析数据损坏的发生以检测在存储器子系统的不同地址之间的数据损坏的重复位模式;以及用于控制ECC算法的应用以擦除与由用于分析的代码检测的重复位模式相关联的位的代码，从内存子系统检索的数据。

2. 发明申请

US20050289439A1 System and method for controlling application of an error correction code (ECC) algorithm in a memory subsystem 有权
标题翻译：用于在存储器子系统中控制纠错码（ECC）算法的应用的系统和方法
公开(公告)号：US20050289439A1
公开(公告)日：2005-12-29
申请号：US10879255
申请日：2004-06-29
申请人： John Nerl , Ken Pomaranski , Gary Gostin , Andrew Walton , David Soper
发明人： John Nerl , Ken Pomaranski , Gary Gostin , Andrew Walton , David Soper
IPC分类号： G11C29/00
CPC分类号： G06F11/1012
摘要： In one embodiment, a computer readable medium comprises code for recording occurrences of data corruption in data retrieved from a memory subsystem, code for determining whether bit locations within the memory subsystem are associated with multiple occurrences of data corruption, code for deallocating, in response to the code for determining, memory regions containing bit locations associated with multiple occurrences of data corruption, code for analyzing patterns of data corruption repeated across multiple addresses of the memory subsystem, and code for controlling application of an error correction code (ECC) algorithm by the memory subsystem to erase bits associated with a repeated bit pattern, detected by the code for analyzing, from data retrieved from the memory subsystem.
摘要翻译：在一个实施例中，计算机可读介质包括用于在从存储器子系统检索的数据中记录数据损坏的发生的代码，用于确定存储器子系统内的位位置是否与多次数据损坏相关联的代码，以及响应于用于确定的代码，包含与多次数据损坏相关联的位位置的存储器区域，用于分析在存储器子系统的多个地址上重复的数据损坏模式的代码，以及用于控制由所述存储器子系统的多个地址应用纠错码（ECC）算法的代码存储器子系统从从存储器子系统检索的数据中擦除与用于分析的代码检测的重复位模式相关联的位。

3. 发明申请

US20050289402A1 System and method for applying error correction code (ECC) erasure mode and clearing recorded information from a page deallocation table 有权
标题翻译：用于应用纠错码（ECC）擦除模式的系统和方法，并从页面解除分配表中清除记录的信息
公开(公告)号：US20050289402A1
公开(公告)日：2005-12-29
申请号：US10879643
申请日：2004-06-29
申请人： John Nerl , Ken Pomaranski , Gary Gostin , Andrew Walton , David Soper
发明人： John Nerl , Ken Pomaranski , Gary Gostin , Andrew Walton , David Soper
IPC分类号： G06F11/00 , G06F11/10
CPC分类号： G06F11/1064
摘要： In one embodiment, a system comprises non-volatile memory storing a page deallocation table (PDT), a memory controller for storing and retrieving data from a memory subsystem, the memory controller using an error correction code (ECC) algorithm to correct data corruption in retrieved data, a processor for executing an error analysis algorithm, the error analysis algorithm recording instances of data corruption in the PDT, deallocating memory regions associated with multiple occurrences of data corruption at single bit locations, the error analysis algorithm causing the memory controller to apply an erasure mode of the ECC algorithm upon detection of a repeated pattern of data corruption across different addresses of the memory subsystem, and removing entries in the PDT that correspond to data corruption addressed by application of the erasure mode.
摘要翻译：在一个实施例中，系统包括存储页面解除分配表（PDT）的非易失性存储器，用于从存储器子系统存储和检索数据的存储器控制器，存储器控制器使用纠错码（ECC）算法来校正数据损坏检索数据，用于执行错误分析算法的处理器，记录PDT中的数据损坏实例的错误分析算法，在单个位置释放与多次数据损坏相关联的存储器区域，使得存储器控制器应用的误差分析算法 ECC算法的擦除模式，当检测到在存储器子系统的不同地址上重复的数据损坏模式时，以及删除对应于通过应用擦除模式解决的数据损坏的PDT中的条目。

4. 发明授权

US07313749B2 System and method for applying error correction code (ECC) erasure mode and clearing recorded information from a page deallocation table 有权
标题翻译：用于应用纠错码（ECC）擦除模式的系统和方法，并从页面解除分配表中清除记录的信息
公开(公告)号：US07313749B2
公开(公告)日：2007-12-25
申请号：US10879643
申请日：2004-06-29
申请人： John A. Nerl , Ken Pomaranski , Gary Gostin , Andrew Walton , David Soper
发明人： John A. Nerl , Ken Pomaranski , Gary Gostin , Andrew Walton , David Soper
IPC分类号： G11C29/00
CPC分类号： G06F11/1064
摘要： A system utilizing an erasure mode in an error correction code algorithm is described that includes non-volatile memory storing a page deallocation table. A memory controller stores and retrieves data from a memory subsystem, and uses an error correction code algorithm to correct data corruption in retrieved data. An error analysis algorithm executed in a processor records instances of data corruption in the page deallocation tables and deallocates memory regions associated with multiple occurrences of data corruption at single bit locations. The error analysis algorithm further causes the memory controller to apply an erasure mode of the error correction code algorithm upon detection of a repeated pattern of data corruption across different addresses of the memory subsystem, and removes entries in the page deallocation table that correspond to data corruption addressed by application of the erasure mode.
摘要翻译：描述了在纠错码算法中利用擦除模式的系统，其包括存储页面解除分配表的非易失性存储器。存储器控制器从存储器子系统存储和检索数据，并使用纠错码算法来校正检索数据中的数据损坏。在处理器中执行的错误分析算法记录页面解除分配表中的数据损坏的实例，并释放与单个位位置上的多次数据损坏相关联的存储器区域。错误分析算法进一步导致存储器控制器在检测到存储器子系统的不同地址上的重复数据损坏模式时应用纠错码算法的擦除模式，并且去除页面分配表中对应于数据损坏的条目通过应用擦除模式来解决。

5. 发明授权

US07437651B2 System and method for controlling application of an error correction code (ECC) algorithm in a memory subsystem 有权
标题翻译：用于在存储器子系统中控制纠错码（ECC）算法的应用的系统和方法
公开(公告)号：US07437651B2
公开(公告)日：2008-10-14
申请号：US10879262
申请日：2004-06-29
申请人： John A. Nerl , Ken Pomaranski , Gary Gostin , Andrew Walton , David Soper
发明人： John A. Nerl , Ken Pomaranski , Gary Gostin , Andrew Walton , David Soper
IPC分类号： H03M13/00 , G11C29/00
CPC分类号： G06F11/1012
摘要： A method for controlling application of an erasure mode of an error correction code (ECC) algorithm in a memory subsystem includes detecting errors in cache lines retrieved from the memory subsystem using the ECC algorithm. The method also analyzes the errors to detect a repeated bit pattern of data corruption within the cache lines, correlates the detected repeated bit pattern of data corruption to one of a plurality of domains of the memory subsystem, and applies the ECC algorithm to erase bits associated with the detected repeated bit pattern from cache lines retrieved from the correlated domain of the memory subsystem.
摘要翻译：一种用于控制在存储器子系统中应用纠错码（ECC）算法的擦除模式的方法包括使用ECC算法检测从存储器子系统检索的高速缓存行中的错误。该方法还分析错误以检测高速缓存行内的数据损坏的重复比特模式，将检测到的数据损坏的重复比特模式与存储器子系统的多个域之一相关联，并将ECC算法应用于擦除与从存储器子系统的相关域检索的来自高速缓存行的检测到的重复位模式。

6. 发明授权

US07308638B2 System and method for controlling application of an error correction code (ECC) algorithm in a memory subsystem 有权
标题翻译：用于在存储器子系统中控制纠错码（ECC）算法的应用的系统和方法
公开(公告)号：US07308638B2
公开(公告)日：2007-12-11
申请号：US10879255
申请日：2004-06-29
申请人： John A. Nerl , Ken Pomaranski , Gary Gostin , Andrew Walton , David Soper
发明人： John A. Nerl , Ken Pomaranski , Gary Gostin , Andrew Walton , David Soper
IPC分类号： G11C29/00
CPC分类号： G06F11/1012
摘要： In one embodiment, a computer readable medium comprises code for recording occurrences of data corruption in data retrieved from a memory subsystem, code for determining whether bit locations within the memory subsystem are associated with multiple occurrences of data corruption, code for deallocating, in response to the code for determining, memory regions containing bit locations associated with multiple occurrences of data corruption, code for analyzing patterns of data corruption repeated across multiple addresses of the memory subsystem, and code for controlling application of an error correction code (ECC) algorithm by the memory subsystem to erase bits associated with a repeated bit pattern, detected by the code for analyzing, from data retrieved from the memory subsystem.
摘要翻译：在一个实施例中，计算机可读介质包括用于在从存储器子系统检索的数据中记录数据损坏的发生的代码，用于确定存储器子系统内的位位置是否与多次数据损坏相关联的代码，以及响应于用于确定的代码，包含与多次数据损坏相关联的位位置的存储器区域，用于分析在存储器子系统的多个地址上重复的数据损坏模式的代码，以及用于控制由所述存储器子系统的多个地址应用纠错码（ECC）算法的代码存储器子系统从从存储器子系统检索的数据中擦除与用于分析的代码检测的重复位模式相关联的位。

7. 发明授权

US09207416B2 Optical connector interconnection system and method 有权
标题翻译：光连接器互连系统及方法
公开(公告)号：US09207416B2
公开(公告)日：2015-12-08
申请号：US13126837
申请日：2008-10-31
申请人： Terrel Morris , Paul Kessler Rosenberg , Michael Renne Ty Tan , Gary Gostin , Eric Peterson
发明人： Terrel Morris , Paul Kessler Rosenberg , Michael Renne Ty Tan , Gary Gostin , Eric Peterson
IPC分类号： G02B6/43 , H04B10/80
CPC分类号： H04B10/801 , G02B6/12004 , G02B6/43 , G06F13/426 , H04B10/803 , Y10T29/49117
摘要： A method for connecting adjacent computing board devices. A source computing board may be provided. An optical engine attaches to the source computing board. A plurality of source optical connectors couples to the optical engine. A first optical connector may be positioned at a location on the source computing board for a first preset type of computing component on an adjacent computing board. A second optical connector may be positioned at a fixed coordinate related to the first optical connector on the source computing board.
摘要翻译：一种用于连接相邻计算板设备的方法。可以提供源计算板。光引擎连接到源计算板。多个源光学连接器耦合到光学引擎。第一光学连接器可以位于源计算板上的位置，用于相邻计算板上的第一预设类型的计算组件。第二光连接器可以位于与源计算板上的第一光连接器相关的固定坐标处。

8. 发明申请

US20120020663A1 BUS-BASED SCALABLE OPTICAL FABRICS 有权
标题翻译：基于总线的可扩展光学织物
公开(公告)号：US20120020663A1
公开(公告)日：2012-01-26
申请号：US13258425
申请日：2009-05-06
申请人： Moray McLaren , Michael Renne ,Ty Tan , Gary Gostin
发明人： Moray McLaren , Michael Renne ,Ty Tan , Gary Gostin
IPC分类号： H04B10/20 , H04J14/02
CPC分类号： G02B6/2852 , G02B6/28 , G02B6/2938 , G02B6/29382 , G02B6/29383 , H04B10/801
摘要： Various embodiments of the present invention are directed to arrangements of multiple optical buses to create scalable optical interconnect fabrics for computer systems. In one aspect, a multi-bus fabric (102) for transmitting optical signals between a plurality of nodes (108-111) comprises a plurality of optical buses (104-107). Each optical bus is optically coupled to each node of the plurality of nodes, and each optical bus is configured to so that one node broadcasts optical signals generated by the node to the other nodes of the plurality of nodes.
摘要翻译：本发明的各种实施例涉及多个光学总线的布置，以便为计算机系统创建可伸缩的光学互连结构。一方面，用于在多个节点（108-111）之间传输光信号的多总线结构（102）包括多条光总线（104-107）。每个光总线被光耦合到多个节点中的每个节点，并且每个光总线被配置为使得一个节点将节点生成的光信号广播到多个节点中的其他节点。

9. 发明申请

US20110280513A1 OPTICAL CONNECTOR INTERCONNECTION SYSTEM AND METHOD 有权
标题翻译：光连接器互连系统及方法
公开(公告)号：US20110280513A1
公开(公告)日：2011-11-17
申请号：US13126837
申请日：2008-10-31
申请人： Terrel Morris , Paul Kessler Rosenberg , Michael Renne Ty Tan , Gary Gostin , Eric Peterson
发明人： Terrel Morris , Paul Kessler Rosenberg , Michael Renne Ty Tan , Gary Gostin , Eric Peterson
IPC分类号： G02B6/125 , G02B6/38
CPC分类号： H04B10/801 , G02B6/12004 , G02B6/43 , G06F13/426 , H04B10/803 , Y10T29/49117
摘要： A method for connecting adjacent computing board devices. A source computing board may be provided. An optical engine attaches to the source computing board. A plurality of source optical connectors couples to the optical engine. A first optical connector may be positioned at a location on the source computing board for a first preset type of computing component on an adjacent computing board. A second optical connector may be positioned at a fixed coordinate related to the first optical connector on the source computing board.
摘要翻译：一种用于连接相邻计算板设备的方法。可以提供源计算板。光引擎连接到源计算板。多个源光学连接器耦合到光学引擎。第一光学连接器可以位于源计算板上的位置，用于相邻计算板上的第一预设类型的计算组件。第二光连接器可以位于与源计算板上的第一光连接器相关的固定坐标处。

10. 发明授权

US07818508B2 System and method for achieving enhanced memory access capabilities 有权
标题翻译：实现增强内存访问功能的系统和方法
公开(公告)号：US07818508B2
公开(公告)日：2010-10-19
申请号：US11741453
申请日：2007-04-27
申请人： Bryan Hornung , Erin A. Handgen , Gary Gostin , Craig Warner
发明人： Bryan Hornung , Erin A. Handgen , Gary Gostin , Craig Warner
IPC分类号： G06F13/00
CPC分类号： G06F12/0607 , G06F12/0817 , G06F13/1657
摘要： A computer system, related components such as a processor agent, and related method are disclosed. In at least one embodiment, the computer system includes a first core, at least one memory device including a first memory segment, and a first memory controller coupled to the first memory segment. Further, the computer system includes a fabric and at least one processor agent coupled at least indirectly to the first core and the first memory segment, and also coupled to the fabric. A first memory request of the first core in relation to a first memory location within the first memory segment proceeds to the first memory controller by way of the at least one processor agent and the fabric.
摘要翻译：公开了一种计算机系统，诸如处理器代理的相关组件和相关方法。在至少一个实施例中，计算机系统包括第一核心，包括第一存储器段的至少一个存储器设备和耦合到第一存储器段的第一存储器控制器。此外，计算机系统包括织物和至少一个处理器代理，至少间接耦合到第一核心和第一存储器段，并且还耦合到织物。相对于第一存储器段内的第一存储器位置的第一存储器的第一存储器请求通过至少一个处理器代理和结构进行到第一存储器控制器。

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