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1. 发明授权

US06600347B2 Dynamically producing an effective impedance of an output driver with a bounded variation during transitions thereby reducing jitter 失效
标题翻译：在转换期间动态地产生具有有界变化的输出驱动器的有效阻抗，从而减少抖动
公开(公告)号：US06600347B2
公开(公告)日：2003-07-29
申请号：US09974686
申请日：2001-10-10
申请人： John Michael Borkenhagen , Moises Cases , Daniel Mark Dreps , David LeRoy Guertin , Nam Huu Pham , Robert Russell Williams
发明人： John Michael Borkenhagen , Moises Cases , Daniel Mark Dreps , David LeRoy Guertin , Nam Huu Pham , Robert Russell Williams
IPC分类号： H03B100
CPC分类号： H03K17/164
摘要： A method and system for reducing a reflection coefficient below a predetermined value thereby reducing jitter by the variation of the effective impedance of a driver appearing to be bounded during state transitions. The driver may include a pull-up driver and a pull-down driver. In the pull-up driver, the transistors may be switched from a first state to a second state in a staggered fashion where the first state is complementary to the second state; In the pull-down driver, the transistors may be switched from a second state to a first state in a staggered fashion. By staggering the switching of the transistors in the pull-up driver and the pull-down driver, a portion of the current may flow from the pull-up driver to the pull-down driver thereby causing the variation of the effective impedance of the driver to appear to be bounded during state transitions.
摘要翻译：一种用于将反射系数降低到低于预定值的方法和系统，从而通过在状态转换期间看起来被界定的驱动器的有效阻抗的变化来减少抖动。驱动器可以包括上拉驱动器和下拉驱动器。在上拉驱动器中，晶体管可以以第一状态与第二状态互补的交错方式从第一状态切换到第二状态; 在下拉驱动器中，晶体管可以以交错的方式从第二状态切换到第一状态。通过交错上拉驱动器和下拉驱动器中的晶体管的切换，电流的一部分可以从上拉驱动器流向下拉驱动器，从而导致驱动器的有效阻抗的变化在状态转换期间看起来是有界的。

2. 发明授权

US07701222B2 Method for validating printed circuit board materials for high speed applications 失效
标题翻译：用于高速应用的印刷电路板材料的验证方法
公开(公告)号：US07701222B2
公开(公告)日：2010-04-20
申请号：US11875001
申请日：2007-10-19
申请人： Moises Cases , Bradley Donald Herrman , Kent Barclay Howieson , Erdem Matoglu , Bhyrav Murthy Mutnury , Pravin Patel , Nam Huu Pham , Caleb James Wesley
发明人： Moises Cases , Bradley Donald Herrman , Kent Barclay Howieson , Erdem Matoglu , Bhyrav Murthy Mutnury , Pravin Patel , Nam Huu Pham , Caleb James Wesley
IPC分类号： G01K3/00 , G01J5/00 , G01K17/00 , G01R27/32
CPC分类号： G01N25/72 , G01J5/0096 , G01R31/2818 , G01R31/2837 , G01R31/309
摘要： A method for testing a printed circuit board to determining the dielectric loss associated with the circuit board material relative to a standard. Dielectric losses in the material generate heat when a high frequency electronic signal, such as a microwave frequency signal, is communicated through a microstrip that is embedded within the printed circuit board. The temperature or spectrum at the surface of printed circuit board is measured and compared against the temperature or spectrum of the standard to determine whether the material under test is acceptable. While various temperature measurement devices may be used, the temperature is preferably measured without contacting the surface, such as using an infrared radiation probe.
摘要翻译：一种用于测试印刷电路板以确定与电路板材料相关的介电损耗相对于标准的方法。当诸如微波频率信号的高频电子信号通过嵌入在印刷电路板内的微带传输时，材料中的介电损耗产生热量。测量印刷电路板表面的温度或光谱，并与标准品的温度或光谱进行比较，以确定被测材料是否可接受。尽管可以使用各种温度测量装置，但是优选地在不接触表面的情况下测量温度，例如使用红外辐射探针。

3. 发明申请

US20090079456A1 APPARATUS, SYSTEM, AND METHOD FOR INTEGRATED COMPONENT TESTING 有权
标题翻译：用于集成组件测试的装置，系统和方法
公开(公告)号：US20090079456A1
公开(公告)日：2009-03-26
申请号：US11859540
申请日：2007-09-21
申请人： Moises Cases , Shiva R. Dasari , Erdem Matoglu , Bhyrav Murthy Mutnury , Nam Huu Pham
发明人： Moises Cases , Shiva R. Dasari , Erdem Matoglu , Bhyrav Murthy Mutnury , Nam Huu Pham
IPC分类号： G01R31/02
CPC分类号： G06F11/24 , G11C5/04 , G11C29/028 , G11C29/12005 , G11C29/50 , G11C2029/5004
摘要： An apparatus, system, and method are disclosed for integrating component testing. A voltage module modifies a reference voltage integral to an electronic device to a plurality of reference voltage values. A test module tests a component of the electronic device at each of the plurality of reference voltage values. In addition, the test module determines a voltage range for the component, wherein the voltage range comprises voltage values between a high voltage failure and a low voltage failure. An optimization module sets the reference voltage value to within the voltage range.
摘要翻译：公开了用于集成部件测试的装置，系统和方法。电压模块将对电子设备积分的参考电压修改为多个参考电压值。测试模块在多个参考电压值中的每一个测试电子设备的组件。此外，测试模块确定组件的电压范围，其中电压范围包括高电压故障和低电压故障之间的电压值。优化模块将参考电压值设置在电压范围内。

4. 发明授权

US07479597B1 Conductor cable having a high surface area 有权
标题翻译：导体电缆具有较高的表面积
公开(公告)号：US07479597B1
公开(公告)日：2009-01-20
申请号：US11946165
申请日：2007-11-28
申请人： Moises Cases , Daniel N. de Araujo , Bhyrav Murthy Mutnury , Nam Huu Pham , Bruce James Wilkie
发明人： Moises Cases , Daniel N. de Araujo , Bhyrav Murthy Mutnury , Nam Huu Pham , Bruce James Wilkie
IPC分类号： H01B7/00
CPC分类号： H01B7/30 , H01B7/0009
摘要： A cable having an electrically conducting wire with a cross sectional shape defined by a simple closed curve having from three to eight concave portions separated by an equal number of convex portions. The simple closed curve has no point where the radius of curvature is less than one-sixth (⅙) of an overall radius of the wire and no point where adjacent curves or lines intersect at an angle. The alternating concave and convex portions of the cable's cross-sectional shape may have substantially the same curvature. The cross-sectional shape of the cable avoids sharp angles and fight curves.
摘要翻译：一种具有导线的电缆，其横截面形状由简单的闭合曲线限定，具有由相等数量的凸部分开的三至八个凹部。简单的闭合曲线没有点曲率半径小于线的总半径的六分之一（1/6），而相邻的曲线或线不是以一定角度相交的点。电缆的横截面形状的交替的凹凸部分可以具有基本相同的曲率。电缆的横截面形状避免了锐角和抗弯曲。

5. 发明申请

US20090102487A1 Method for Validating Printed Circuit Board Materials for High Speed Applications 失效
标题翻译：用于验证高速应用的印刷电路板材料的方法
公开(公告)号：US20090102487A1
公开(公告)日：2009-04-23
申请号：US11875001
申请日：2007-10-19
申请人： Moises Cases , Bradley Donald Herrman , Kent Barclay Howieson , Erdem Matoglu , Bhyrav Murthy Mutnury , Pravin Patel , Nam Huu Pham , Celeb James Wesley
发明人： Moises Cases , Bradley Donald Herrman , Kent Barclay Howieson , Erdem Matoglu , Bhyrav Murthy Mutnury , Pravin Patel , Nam Huu Pham , Celeb James Wesley
IPC分类号： G01R31/02 , G01K3/00 , G01N25/72
CPC分类号： G01N25/72 , G01J5/0096 , G01R31/2818 , G01R31/2837 , G01R31/309
摘要： A method for testing a printed circuit board to determining the dielectric loss associated with the circuit board material relative to a standard. Dielectric losses in the material generate heat when a high frequency electronic signal, such as a microwave frequency signal, is communicated through a microstrip that is embedded within the printed circuit board. The temperature or spectrum at the surface of printed circuit board is measured and compared against the temperature or spectrum of the standard to determine whether the material under test is acceptable. While various temperature measurement devices may be used, the temperature is preferably measured without contacting the surface, such as using an infrared radiation probe.
摘要翻译：一种用于测试印刷电路板以确定与电路板材料相关的介电损耗相对于标准的方法。当诸如微波频率信号的高频电子信号通过嵌入在印刷电路板内的微带传输时，材料中的介电损耗产生热量。测量印刷电路板表面的温度或光谱，并与标准品的温度或光谱进行比较，以确定被测材料是否可接受。尽管可以使用各种温度测量装置，但是优选地在不接触表面的情况下测量温度，例如使用红外辐射探针。

6. 发明授权

US07444490B2 Apparatus, system, and method for modifying memory voltage and performance based on a measure of memory device stress 失效
标题翻译：用于根据存储器件应力测量修改存储器电压和性能的装置，系统和方法
公开(公告)号：US07444490B2
公开(公告)日：2008-10-28
申请号：US11148912
申请日：2005-06-09
申请人： Moises Cases , Daniel N. de Araujo , Nam Huu Pham , Menas Roumbakis
发明人： Moises Cases , Daniel N. de Araujo , Nam Huu Pham , Menas Roumbakis
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F11/00 , G11C29/00 , G11C7/04 , G11C11/34 , H01L35/00 , H01L37/00 , H03K3/42 , H03K17/78
CPC分类号： G06F13/4072
摘要： An apparatus, system, and method are disclosed for modifying memory device timing and voltage. A detection module detects a change of memory device stress. A timing modification module modifies the memory device timing in response to the change of the memory device stress. In addition, a voltage modification module modifies the memory device voltage in response to the change of the memory device stress. In one embodiment, a processor pause module pauses the operation of a processor module while the timing modification module modifies the memory device timing and the voltage modification module modifies the memory device voltage.
摘要翻译：公开了用于修改存储器件定时和电压的装置，系统和方法。检测模块检测存储器件应力的变化。定时修改模块响应于存储器件应力的变化来修改存储器件定时。此外，电压修改模块响应于存储器件应力的变化来修改存储器件电压。在一个实施例中，处理器暂停模块暂停处理器模块的操作，而定时修改模块修改存储器件定时，并且电压修改模块修改存储器件电压。

7. 发明申请

US20080148003A1 SPATIAL BASED DYNAMIC TRANSCEIVER ADJUSTMENT 审中-公开
标题翻译：基于空间的动态收敛机调整
公开(公告)号：US20080148003A1
公开(公告)日：2008-06-19
申请号：US11612658
申请日：2006-12-19
申请人： Mark A. Brandyberry , Daniel N. de Araujo , Nickolaus J. Gruendler , Nam Huu Pham
发明人： Mark A. Brandyberry , Daniel N. de Araujo , Nickolaus J. Gruendler , Nam Huu Pham
IPC分类号： G06F12/00
CPC分类号： G06F13/16
摘要： Embodiments of the invention address deficiencies of the art in respect to parameter value configuration for signaling in a multi-drop net, and provide a novel and non-obvious method, system and apparatus for spatial based transceiver adjustment. In one embodiment of the invention, a spatial based dynamic transceiver configuration method can be provided for a multi-drop net. The method can include locating a position for a target receiver for signaling in the multi-drop net, selecting a static transceiver configuration corresponding to the position, and signaling the target receiver utilizing the selected static transceiver configuration. The locating, selecting and signaling can be repeated for different target receivers in different positions in the multi-drop net each repetition utilizing a different selected transceiver configuration.
摘要翻译：本发明的实施例解决了在多滴网络中用于信令的参数值配置方面的技术缺陷，并且提供了一种用于基于空间的收发机调整的新颖且非显而易见的方法，系统和装置。在本发明的一个实施例中，可以为多点网络提供基于空间的动态收发机配置方法。该方法可以包括在多点网络中定位用于信令的目标接收机的位置，选择对应于该位置的静态收发器配置，以及使用所选择的静态收发机配置来发信号通知目标接收机。可以在多点网络中的不同位置的不同目标接收机重复定位，选择和信令，每次重复利用不同的选择的收发机配置。

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