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1. 发明申请

US20080148003A1 SPATIAL BASED DYNAMIC TRANSCEIVER ADJUSTMENT 审中-公开
标题翻译：基于空间的动态收敛机调整
公开(公告)号：US20080148003A1
公开(公告)日：2008-06-19
申请号：US11612658
申请日：2006-12-19
申请人： Mark A. Brandyberry , Daniel N. de Araujo , Nickolaus J. Gruendler , Nam Huu Pham
发明人： Mark A. Brandyberry , Daniel N. de Araujo , Nickolaus J. Gruendler , Nam Huu Pham
IPC分类号： G06F12/00
CPC分类号： G06F13/16
摘要： Embodiments of the invention address deficiencies of the art in respect to parameter value configuration for signaling in a multi-drop net, and provide a novel and non-obvious method, system and apparatus for spatial based transceiver adjustment. In one embodiment of the invention, a spatial based dynamic transceiver configuration method can be provided for a multi-drop net. The method can include locating a position for a target receiver for signaling in the multi-drop net, selecting a static transceiver configuration corresponding to the position, and signaling the target receiver utilizing the selected static transceiver configuration. The locating, selecting and signaling can be repeated for different target receivers in different positions in the multi-drop net each repetition utilizing a different selected transceiver configuration.
摘要翻译：本发明的实施例解决了在多滴网络中用于信令的参数值配置方面的技术缺陷，并且提供了一种用于基于空间的收发机调整的新颖且非显而易见的方法，系统和装置。在本发明的一个实施例中，可以为多点网络提供基于空间的动态收发机配置方法。该方法可以包括在多点网络中定位用于信令的目标接收机的位置，选择对应于该位置的静态收发器配置，以及使用所选择的静态收发机配置来发信号通知目标接收机。可以在多点网络中的不同位置的不同目标接收机重复定位，选择和信令，每次重复利用不同的选择的收发机配置。

2. 发明授权

US08492658B2 Laminate capacitor stack inside a printed circuit board for electromagnetic compatibility capacitance 失效
标题翻译：用于电磁兼容性电容的印刷电路板内层叠电容器堆叠
公开(公告)号：US08492658B2
公开(公告)日：2013-07-23
申请号：US12947562
申请日：2010-11-16
申请人： Nickolaus J. Gruendler , Bhyrav M. Mutnury , Terence Rodrigues
发明人： Nickolaus J. Gruendler , Bhyrav M. Mutnury , Terence Rodrigues
IPC分类号： H05K1/11 , H01K3/10
CPC分类号： H05K1/162 , H05K1/0231 , H05K2201/097 , Y10T29/49124 , Y10T29/49165
摘要： An apparatus comprises a multi-layer printed circuit board having at least three conductor layers, a dielectric material layer between each of the conductor layers, and a laminate capacitor stack arranged transversely through the printed circuit board. The laminate capacitor stack comprises: (a) a plurality of conducting patches including a patch in a plurality of the conductor layers, wherein the plurality of patches are aligned in a stack with the dielectric material filling the space between adjacent patches; (b) a first conducting via interconnecting each patch in a first subset of the plurality of patches, wherein the first subset of the plurality of patches are coupled to one of the conductor layers that is at ground potential; and (c) a second conducting via interconnecting each patch in a second subset of the plurality of patches, wherein the second subset of the plurality of patches are coupled to one of the conductor layers that is at power potential, wherein the patches in the first subset are disposed in an alternating pattern with the patches in the second subset.
摘要翻译：一种装置包括具有至少三个导体层的多层印刷电路板，每个导体层之间的介电材料层和横向布置在印刷电路板上的叠层电容器叠层。层压电容器堆叠包括：（a）多个导电贴片，包括多个导体层中的贴片，其中多个贴片以堆叠的方式与电介质材料填充相邻贴片之间的空间; （b）第一导电通孔，其互连多个贴片的第一子集中的每个贴片，其中所述多个贴片的第一子集耦合到处于地电位的导体层之一; 和（c）第二导电通孔，其互连多个贴片的第二子集中的每个贴片，其中多个贴片的第二子集耦合到处于功率电位的导体层中的一个，其中第一子集以与第二子集中的贴片交替模式布置。

3. 发明申请

US20120118622A1 LAMINATE CAPACITOR STACK INSIDE A PRINTED CIRCUIT BOARD FOR ELECTROMAGNETIC COMPATIBILITY CAPACITANCE 失效
标题翻译：印刷电路板内电容兼容性电容层叠电容器堆
公开(公告)号：US20120118622A1
公开(公告)日：2012-05-17
申请号：US12947562
申请日：2010-11-16
申请人： Nickolaus J. Gruendler , Bhyrav M. Mutnury , Terence Rodrigues
发明人： Nickolaus J. Gruendler , Bhyrav M. Mutnury , Terence Rodrigues
IPC分类号： H05K1/16 , H05K3/00
CPC分类号： H05K1/162 , H05K1/0231 , H05K2201/097 , Y10T29/49124 , Y10T29/49165
摘要： An apparatus comprises a multi-layer printed circuit board having at least three conductor layers, a dielectric material layer between each of the conductor layers, and a laminate capacitor stack arranged transversely through the printed circuit board. The laminate capacitor stack comprises: (a) a plurality of conducting patches including a patch in a plurality of the conductor layers, wherein the plurality of patches are aligned in a stack with the dielectric material filling the space between adjacent patches; (b) a first conducting via interconnecting each patch in a first subset of the plurality of patches, wherein the first subset of the plurality of patches are coupled to one of the conductor layers that is at ground potential; and (c) a second conducting via interconnecting each patch in a second subset of the plurality of patches, wherein the second subset of the plurality of patches are coupled to one of the conductor layers that is at power potential, wherein the patches in the first subset are disposed in an alternating pattern with the patches in the second subset.
摘要翻译：一种装置包括具有至少三个导体层的多层印刷电路板，每个导体层之间的介电材料层和横向布置在印刷电路板上的叠层电容器叠层。层压电容器堆叠包括：（a）多个导电贴片，包括多个导体层中的贴片，其中多个贴片以堆叠的方式与电介质材料填充相邻贴片之间的空间; （b）第一导电通孔，其互连多个贴片的第一子集中的每个贴片，其中所述多个贴片的第一子集耦合到处于地电位的导体层之一; 和（c）第二导电通孔，其互连多个贴片的第二子集中的每个贴片，其中多个贴片的第二子集耦合到处于功率电位的导体层中的一个，其中第一子集以与第二子集中的贴片交替模式布置。

4. 发明申请

US20120020042A1 NOISE SUPPRESSOR FOR SEMICONDUCTOR PACKAGES 有权
标题翻译：噪声抑制器用于半导体封装
公开(公告)号：US20120020042A1
公开(公告)日：2012-01-26
申请号：US12840861
申请日：2010-07-21
申请人： Nickolaus J. Gruendler , Paul M. Harvey , Tae Hong Kim , Sang Y. Lee , Michael J. Shapiro
发明人： Nickolaus J. Gruendler , Paul M. Harvey , Tae Hong Kim , Sang Y. Lee , Michael J. Shapiro
IPC分类号： H05K7/02 , H05K3/30 , H05K3/34 , H05K1/16
CPC分类号： G01L9/12 , H01L2224/16227 , H01L2224/16235 , H01L2924/1531 , H01L2924/3025 , H05K1/0228 , H05K1/0231 , H05K1/0251 , Y10T29/49139 , Y10T29/49142
摘要： One or more decoupling capacitors are coupled to a low inductance mount that is connected to the bottom layer of a printed circuit board (PCB) on which a semiconductor module is mounted. The low inductance mount includes a magnetic planar structure with vias that are coupled to the one or more decoupling capacitors and to like vias positioned on the PCB.
摘要翻译：一个或多个去耦电容器耦合到低电感安装座，该低电感安装件连接到其上安装有半导体模块的印刷电路板（PCB）的底层。低电感安装座包括磁性平面结构，其具有耦合到一个或多个去耦电容器的过孔以及位于PCB上的相似通孔。

5. 发明授权

US07827445B2 Fault injection in dynamic random access memory modules for performing built-in self-tests 有权
标题翻译：用于执行内置自检的动态随机存取存储器模块中的故障注入
公开(公告)号：US07827445B2
公开(公告)日：2010-11-02
申请号：US11960489
申请日：2007-12-19
申请人： Jimmy G. Foster, Sr. , Nickolaus J. Gruendler , Suzanne M. Michelich , Jacques B. Taylor
发明人： Jimmy G. Foster, Sr. , Nickolaus J. Gruendler , Suzanne M. Michelich , Jacques B. Taylor
IPC分类号： G06F11/00 , G06F11/273
CPC分类号： G11C29/02 , G11C5/04 , G11C11/401 , G11C29/022 , G11C29/024 , G11C29/025 , G11C29/16 , G11C29/44 , G11C29/56008
摘要： Fault injection in dynamic random access memory (‘DRAM’) modules for performing built-in self-tests (‘BISTs’) including establishing, in the mode registers of the DRAM modules by the memory controller through the shared address bus, an injection of a fault into one or more signal lines of a DRAM module, the fault characterized by a fault type; writing data by the memory controller through a data bus to the DRAM modules, the data identifying a particular DRAM module; and responsive to receiving the data, injecting, by the particular DRAM module, the fault characterized by the fault type into the one or more signal lines of the particular DRAM module.
摘要翻译：动态随机存取存储器（“DRAM”）模块中的故障注入用于执行内置的自检（“BIST”），包括通过共享地址总线在存储器控制器的DRAM模块的模式寄存器中建立注入故障成为DRAM模块的一条或多条信号线，故障特征为故障类型; 由存储器控制器通过数据总线向DRAM模块写入数据，识别特定DRAM模块的数据; 并且响应于接收到所述数据，由所述特定DRAM模块将由故障类型表征的故障注入到所述特定DRAM模块的所述一个或多个信号线中。

6. 发明授权

US08494038B2 Common mode noise reduction within differential signal 失效
标题翻译：差分信号内的共模降噪
公开(公告)号：US08494038B2
公开(公告)日：2013-07-23
申请号：US12972480
申请日：2010-12-19
申请人： Nickolaus J. Gruendler , Bhyrav Mutnury , Terence Rodrigues
发明人： Nickolaus J. Gruendler , Bhyrav Mutnury , Terence Rodrigues
IPC分类号： H04B3/46
CPC分类号： H04B3/30 , H04L25/0274
摘要： A receiver circuit detects an eye margin within a differential signal having a true component and a complement component. A transmitter circuit adjusts a phase between the true component and the complement component of the differential signal, based on the eye margin, to improve the eye margin. Improving the eye margin results from a reduction in common mode noise within the differential signal.
摘要翻译：接收机电路检测具有真实分量和补码分量的差分信号内的眼界。发射机电路基于眼睛边缘调整差分信号的真实分量和补码分量之间的相位，以改善眼睛边缘。差分信号中共模噪声的降低导致改善眼余量。

7. 发明申请

US20100102790A1 Optimizing delivery of regulated power from a voltage regulator to an electrical component 有权
标题翻译：优化调节功率从电压调节器到电气部件的传送
公开(公告)号：US20100102790A1
公开(公告)日：2010-04-29
申请号：US12258860
申请日：2008-10-27
申请人： Jerrod K. Buterbaugh , Nickolaus J. Gruendler , Bruce J. Wilkie
发明人： Jerrod K. Buterbaugh , Nickolaus J. Gruendler , Bruce J. Wilkie
IPC分类号： G05F1/618
CPC分类号： H02M3/285 , H02M3/1584 , H02M2001/0012
摘要： Methods, apparatus, and products for optimizing delivery of regulated power from a voltage regulator to an electrical component, operation of the voltage regulator controlled by a service processor, the voltage regulator including a number of phases, each phase rated to deliver a different maximum power to the electrical component, where optimizing delivery of regulated power includes determining, by the service processor, the present power requirements of the electrical component, and enabling, by the service processor, one or more phases of the voltage regulator in dependence upon the present power requirements of the electrical component.
摘要翻译：用于优化从稳压器到电气部件的调节功率传递的方法，装置和产品，由服务处理器控制的电压调节器的操作，所述电压调节器包括多个相位，每相被额定为递送不同的最大功率其中优化所述调节功率的传送包括由所述服务处理器确定所述电气部件的当前功率需求，以及由所述服务处理器根据所述当前功率使所述电压调节器的一个或多个相位要求电气部件。

8. 发明授权

US08898484B2 Optimizing delivery of regulated power from a voltage regulator to an electrical component 有权
标题翻译：优化调节功率从电压调节器到电气部件的传送
公开(公告)号：US08898484B2
公开(公告)日：2014-11-25
申请号：US12258860
申请日：2008-10-27
申请人： Jerrod K. Buterbaugh , Nickolaus J. Gruendler , Bruce J. Wilkie
发明人： Jerrod K. Buterbaugh , Nickolaus J. Gruendler , Bruce J. Wilkie
IPC分类号： G05F1/00 , H02M3/28 , H02M3/158 , G06F11/30 , H02M1/00
CPC分类号： H02M3/285 , H02M3/1584 , H02M2001/0012
摘要： Methods, apparatus, and products for optimizing delivery of regulated power from a voltage regulator to an electrical component, operation of the voltage regulator controlled by a service processor, the voltage regulator including a number of phases, each phase rated to deliver a different maximum power to the electrical component, where optimizing delivery of regulated power includes determining, by the service processor, the present power requirements of the electrical component, and enabling, by the service processor, one or more phases of the voltage regulator in dependence upon the present power requirements of the electrical component.
摘要翻译：用于优化从稳压器到电气部件的调节功率传递的方法，装置和产品，由服务处理器控制的电压调节器的操作，所述电压调节器包括多个相位，每相被额定为递送不同的最大功率其中优化所述调节功率的传送包括由所述服务处理器确定所述电气部件的当前功率需求，以及由所述服务处理器根据所述当前功率使所述电压调节器的一个或多个相位要求电气部件。

9. 发明授权

US08594955B2 Establishing a power profile for generating electrical ratings 有权
标题翻译：建立用于产生电气额定值的电源配置文件
公开(公告)号：US08594955B2
公开(公告)日：2013-11-26
申请号：US12327303
申请日：2008-12-03
申请人： Matthew R. Archibald , Nickolaus J. Gruendler
发明人： Matthew R. Archibald , Nickolaus J. Gruendler
IPC分类号： G01R21/00
CPC分类号： G01R21/133 , G06F1/26
摘要： Establishing a power profile of power consuming components of computer system configurations for generating electrical ratings, beginning with a default, limited configuration of a computer system and continuing for a number of configurations of the computer system, each configuration including additional power consuming components not included in a previous configuration, where establishing a power profile includes: measuring, for a present configuration, power consumption of the computer system; calculating, in dependence upon the measured power consumption for the present configuration, an estimated power rating for the one or more additional power consuming components; and recording, in a power profile, estimated power ratings for the additional power consuming components, where the number of configurations of the computer system for which power consumption is measured is less than the number of possible configurations of the computer system.
摘要翻译：建立用于产生电气额定值的计算机系统配置的功耗组件的功率曲线，从默认的计算机系统的有限配置开始并且继续计算机系统的多个配置，每个配置包括不包括在其中的附加功耗部件其中建立功率分布的先前配置包括：针对当前配置，测量计算机系统的功耗; 根据本配置的测量功率消耗计算一个或多个附加功耗组件的估计功率额定值; 并且在功率分布图中记录附加功耗组件的估计功率额定值，其中测量功耗的计算机系统的配置数量小于计算机系统的可能配置的数量。

10. 发明申请

US20120155527A1 Common mode noise reduction within differential signal 失效
标题翻译：差分信号内的共模降噪
公开(公告)号：US20120155527A1
公开(公告)日：2012-06-21
申请号：US12972480
申请日：2010-12-19
申请人： Nickolaus J. Gruendler , Bhyrav Mutnury , Terence Rodrigues
发明人： Nickolaus J. Gruendler , Bhyrav Mutnury , Terence Rodrigues
IPC分类号： H04B3/46
CPC分类号： H04B3/30 , H04L25/0274
摘要： A receiver circuit detects an eye margin within a differential signal having a true component and a complement component. A transmitter circuit adjusts a phase between the true component and the complement component of the differential signal, based on the eye margin, to improve the eye margin. Improving the eye margin results from a reduction in common mode noise within the differential signal
摘要翻译：接收机电路检测具有真实分量和补码分量的差分信号内的眼界。发射机电路基于眼睛边缘调整差分信号的真实分量和补码分量之间的相位，以改善眼睛边缘。差分信号中共模噪声的降低导致改善眼余量

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