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1. 发明授权

US06486527B1 Vertical fuse structure for integrated circuits containing an exposure window in the layer over the fuse structure to facilitate programming thereafter 失效
标题翻译：用于集成电路的垂直熔丝结构，其在熔丝结构的层中包含曝光窗口，以便于之后进行编程
公开(公告)号：US06486527B1
公开(公告)日：2002-11-26
申请号：US09344613
申请日：1999-06-25
申请人： John MacPherson , Jayaraman Iyer , Alan H. Huggins , John S. Starzynski , Keith R. Erb , Dennis L. Lantz, Jr.
发明人： John MacPherson , Jayaraman Iyer , Alan H. Huggins , John S. Starzynski , Keith R. Erb , Dennis L. Lantz, Jr.
IPC分类号： H01L2900
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： According to the present invention, after manufacture of a disconnect fuse circuit, windows are opened in the insulating film overlying the second interconnect layer at all possible disconnection points, the disconnection points preferably being an exposure window that is aligned over a disconnect fuse circuit that includes a via that electrically connects electrical conductors disposed on different respective layers. This insulating film may consist of one or more layers of one or more materials, but preferentially consists of a single layer of silicon oxide. The wafer is then stored for later configuration. When the wafer is to be configured, a non-precision mask is manufactured. The wafer is coated with photoresist and patterned using the mask to produce disconnection holes in the photoresist at the desired disconnection points. Since the area over the desired disconnection points are free of the insulating film overlying the second patterned interconnect layer, the etching process can be limited to etch techniques which are optimized to etch metal with selectivity to the insulating film. The areas at the disconnection sites that are covered by the insulating film are further protected during the etch process, since the insulating film acts as an etch barrier to inhibit the etching of active circuit elements in proximity to the desired disconnect points.
摘要翻译：根据本发明，在断开保险丝电路的制造之后，在所有可能的断开点处在覆盖第二互连层的绝缘膜中打开窗口，断开点优选地是在断开熔丝电路上对准的曝光窗口，通孔，其电连接设置在不同的各层上的电导体。该绝缘膜可由一层或多层一层或多层材料组成，但优选由单层氧化硅组成。然后将晶片存储以供稍后配置。当要构造晶片时，制造非精密掩模。晶片用光刻胶涂覆，并使用掩模进行图案化，以在期望的断开点处在光致抗蚀剂中产生断开孔。由于期望的断开点上的区域没有覆盖第二图案化互连层的绝缘膜，所以蚀刻工艺可以限于蚀刻技术，其被优化以蚀刻具有对绝缘膜的选择性的金属。在绝缘膜被覆盖的断开位置处的区域在蚀刻工艺期间被进一步保护，因为绝缘膜用作蚀刻阻挡层，以阻止在期望的断开点附近蚀刻有源电路元件。

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