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1. 发明授权

US06486527B1 Vertical fuse structure for integrated circuits containing an exposure window in the layer over the fuse structure to facilitate programming thereafter 失效
标题翻译：用于集成电路的垂直熔丝结构，其在熔丝结构的层中包含曝光窗口，以便于之后进行编程
公开(公告)号：US06486527B1
公开(公告)日：2002-11-26
申请号：US09344613
申请日：1999-06-25
申请人： John MacPherson , Jayaraman Iyer , Alan H. Huggins , John S. Starzynski , Keith R. Erb , Dennis L. Lantz, Jr.
发明人： John MacPherson , Jayaraman Iyer , Alan H. Huggins , John S. Starzynski , Keith R. Erb , Dennis L. Lantz, Jr.
IPC分类号： H01L2900
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： According to the present invention, after manufacture of a disconnect fuse circuit, windows are opened in the insulating film overlying the second interconnect layer at all possible disconnection points, the disconnection points preferably being an exposure window that is aligned over a disconnect fuse circuit that includes a via that electrically connects electrical conductors disposed on different respective layers. This insulating film may consist of one or more layers of one or more materials, but preferentially consists of a single layer of silicon oxide. The wafer is then stored for later configuration. When the wafer is to be configured, a non-precision mask is manufactured. The wafer is coated with photoresist and patterned using the mask to produce disconnection holes in the photoresist at the desired disconnection points. Since the area over the desired disconnection points are free of the insulating film overlying the second patterned interconnect layer, the etching process can be limited to etch techniques which are optimized to etch metal with selectivity to the insulating film. The areas at the disconnection sites that are covered by the insulating film are further protected during the etch process, since the insulating film acts as an etch barrier to inhibit the etching of active circuit elements in proximity to the desired disconnect points.
摘要翻译：根据本发明，在断开保险丝电路的制造之后，在所有可能的断开点处在覆盖第二互连层的绝缘膜中打开窗口，断开点优选地是在断开熔丝电路上对准的曝光窗口，通孔，其电连接设置在不同的各层上的电导体。该绝缘膜可由一层或多层一层或多层材料组成，但优选由单层氧化硅组成。然后将晶片存储以供稍后配置。当要构造晶片时，制造非精密掩模。晶片用光刻胶涂覆，并使用掩模进行图案化，以在期望的断开点处在光致抗蚀剂中产生断开孔。由于期望的断开点上的区域没有覆盖第二图案化互连层的绝缘膜，所以蚀刻工艺可以限于蚀刻技术，其被优化以蚀刻具有对绝缘膜的选择性的金属。在绝缘膜被覆盖的断开位置处的区域在蚀刻工艺期间被进一步保护，因为绝缘膜用作蚀刻阻挡层，以阻止在期望的断开点附近蚀刻有源电路元件。

2. 发明授权

US06228564B1 Method of patterning photoresist using precision and non-precision techniques 失效
标题翻译：使用精密和非精密技术构图光刻胶的方法
公开(公告)号：US06228564B1
公开(公告)日：2001-05-08
申请号：US09376613
申请日：1999-08-18
申请人： Alan H. Huggins
发明人： Alan H. Huggins
IPC分类号： G03C500
CPC分类号： G03F7/70425 , G03F7/2002 , Y10S430/146
摘要： A method for patterning a layer of photoresist includes the steps of 1) exposing the photoresist through a standard precision mask to define all possible patterns and features, and 2) selecting desired patterns and features with a non-precision targeting energy beam or mask. Consequently, no custom precision masks are required to pattern the various layers of photoresist during the fabrication of application specific integrated circuits (ASICs), thereby reducing both the lead-time and costs for manufacturing ASICs.
摘要翻译：用于图案化光致抗蚀剂层的方法包括以下步骤：1）通过标准精密掩模曝光光致抗蚀剂以限定所有可能的图案和特征，以及2）用非精确的瞄准能量束或掩模选择期望的图案和特征。因此，在制造专用集成电路（ASIC）期间，不需要定制精密掩模来对各种光致抗蚀剂层进行图案化，从而减少制造ASIC的交货时间和成本。

3. 发明授权

US6080533A Method of patterning photoresist using precision and non-precision techniques 失效
标题翻译：使用精密和非精密技术构图光刻胶的方法
公开(公告)号：US6080533A
公开(公告)日：2000-06-27
申请号：US38216
申请日：1998-03-10
申请人： Alan H. Huggins
发明人： Alan H. Huggins
IPC分类号： G03F7/20
CPC分类号： G03F7/70425 , G03F7/2002 , Y10S430/146
摘要： A method for patterning a layer of photoresist includes the steps of 1) exposing the photoresist through a standard precision mask to define all possible patterns and features, and 2) selecting desired patterns and features with a non-precision targeting energy beam or mask. Consequently, no custom precision masks are required to pattern the various layers of photoresist during the fabrication of application specific integrated circuits (ASICs), thereby reducing both the lead-time and costs for manufacturing ASICs.
摘要翻译：用于图案化光致抗蚀剂层的方法包括以下步骤：1）通过标准精密掩模曝光光致抗蚀剂以限定所有可能的图案和特征，以及2）用非精确的瞄准能量束或掩模选择期望的图案和特征。因此，在制造专用集成电路（ASIC）期间，不需要定制精密掩模来对各种光致抗蚀剂层进行图案化，从而减少制造ASIC的交货时间和成本。

4. 发明授权

US5514613A Parallel manufacturing of semiconductor devices and the resulting structure 失效
标题翻译：并联制造半导体器件及其结构
公开(公告)号：US5514613A
公开(公告)日：1996-05-07
申请号：US189024
申请日：1994-01-27
申请人： Joseph F. Santadrea , Ji-Min Lee , Chuen-Der Lien , Alan H. Huggins
发明人： Joseph F. Santadrea , Ji-Min Lee , Chuen-Der Lien , Alan H. Huggins
IPC分类号： H01L21/66 , H01L21/68 , H01L21/768
CPC分类号： H01L21/6835 , H01L22/20 , H01L2221/68359 , H01L2221/68363 , H01L2924/014 , H01L2924/10253 , H01L2924/19041 , H01L2924/30105
摘要： In accordance with this invention, integrated circuits are manufactured using parallel processing to manufacture separately selected parts of finished integrated circuits. Upon completion of the parts, the parts are joined together to form the completed integrated circuit. For example, a semiconductor wafer containing active and passive semiconductor regions is fabricated through the first layer of insulation and first conductive contacts. Separately, an interconnect structure is fabricated on a separate fabrication line to include all the layers of interconnects required to form a completed integrated circuit when joined to the wafer. The interconnect structure is joined to the wafer to form the complete integrated device. The interconnect structure can be fabricated to exclude from the integrated circuit those portions of the wafer which have been determined by test to be defective.
摘要翻译：根据本发明，使用并行处理制造集成电路，以制造成品集成电路的分开选择的部分。零件完成后，零件连接在一起形成完整的集成电路。例如，通过第一绝缘层和第一导电触点制造包含有源和无源半导体区域的半导体晶片。另外，在单独的制造线上制造互连结构，以包括当连接到晶片时形成完整的集成电路所需的所有互连层。互连结构连接到晶片以形成完整的集成器件。可以制造互连结构以从集成电路排除已经通过测试确定为缺陷的晶片的那些部分。

5. 发明授权

US5986319A Laser fuse and antifuse structures formed over the active circuitry of an integrated circuit 失效
公开(公告)号：US5986319A
公开(公告)日：1999-11-16
申请号：US822551
申请日：1997-03-19
申请人： Alan H. Huggins
发明人： Alan H. Huggins
IPC分类号： H01L23/525 , H01L23/62 , H01L23/52
CPC分类号： H01L23/5258 , H01L23/525 , H01L23/62 , H01L2924/0002
摘要： In an integrated circuit where one desires the most compact arrangement of fuses and active circuitry, an insulating layer is deposited over active circuitry which includes the associated interconnect layers. A protective layer made with a reflective material may be used as a conductive layer above the lower layers of the integrated circuit containing active circuitry which includes interconnect layers of any desired number. This protective layer is patterned below the areas that will later contain fuses (or antifuses or both). Above this protective layer another insulating layer is deposited. A fuse layer which may be metal or another conductive film is then deposited. This conductive layer is patterned to provide the desired fuses (and/or antifuses) as required, with some or all of the fuses aligned with the protective layer deposited underneath. The protective layer is patterned such that the area of the protective layer underneath the fuses will absorb and/or deflect much of the radiant energy that does not directly impinge upon the fuses.

6. 发明授权

US5949323A Non-uniform width configurable fuse structure 失效
标题翻译：不均匀宽度可配置保险丝结构
公开(公告)号：US5949323A
公开(公告)日：1999-09-07
申请号：US107841
申请日：1998-06-30
申请人： Alan H. Huggins , Ron Thomas , David E. Schmulian
发明人： Alan H. Huggins , Ron Thomas , David E. Schmulian
IPC分类号： H01H37/76 , H01L21/82 , H01L23/525 , H01H37/36 , H01L27/10 , H01L27/115
CPC分类号： H01L23/5258 , H01L2924/0002
摘要： A radiant-energy configurable fuse structure and array are provided in which the fuse body of the fuse is wider than the fuse connection terminals. The fuse body can be circular or polygonal to capture more of the radiant energy from a targeting beam, which reduces the energy required to blow the fuse. As a result, unrelated circuit elements and patterned lines can be placed closer together in a laser fuse array, thereby increasing the packing density of such arrays.
摘要翻译：提供了一种可辐射能量可配置的熔丝结构和阵列，其中熔丝的保险丝体比熔丝连接端子更宽。保险丝体可以是圆形或多边形，以从瞄准光束捕获更多的辐射能，这降低了熔断器所需的能量。结果，不相关的电路元件和图案化线可以放置在激光熔丝阵列中更靠近在一起，从而增加这种阵列的封装密度。

7. 发明授权

US5885749A Method of customizing integrated circuits by selective secondary deposition of layer interconnect material 失效
标题翻译：通过层互连材料的选择性二次沉积定制集成电路的方法
公开(公告)号：US5885749A
公开(公告)日：1999-03-23
申请号：US879542
申请日：1997-06-20
申请人： Alan H. Huggins , John MacPherson
发明人： Alan H. Huggins , John MacPherson
IPC分类号： G03F7/20 , H01L21/768 , H01L23/525
CPC分类号： G03F7/70466 , G03F7/2022 , H01L21/76894 , H01L23/5258 , H01L2924/0002
摘要： A method for fabricating custom integrated circuits includes the steps of 1) patterning a photoresist layer on an insulative layer with a standard via precision mask to define all possible vias, and 2) using a targeting energy beam to select the desired via locations, which are then etched and interconnections made, for customization or repair of the integrated circuit. Consequently, the present invention requires no custom mask so that application specific integrated circuits (ASICs) can be produced with lower lead-time and costs when compared to prior methods.
摘要翻译：一种用于制造定制集成电路的方法包括以下步骤：1）使用标准通孔精密掩模在绝缘层上图案化光致抗蚀剂层以限定所有可能的通孔，以及2）使用瞄准能量束来选择所需的通孔位置，然后进行蚀刻和互连，用于定制或修复集成电路。因此，本发明不需要定制掩模，使得与现有方法相比，可以以较低的提前期和成本制造专用集成电路（ASIC）。

8. 发明授权

US5840627A Method of customizing integrated circuits using standard masks and targeting energy beams for single resist development 失效
标题翻译：使用标准掩模定制集成电路的方法，并针对单个抗蚀剂开发的能量束
公开(公告)号：US5840627A
公开(公告)日：1998-11-24
申请号：US823777
申请日：1997-03-24
申请人： Alan H. Huggins
发明人： Alan H. Huggins
IPC分类号： H01L21/768 , H01L23/525 , H05K3/22 , H01L21/44
CPC分类号： H01L21/76894 , H01L23/5254 , H01L23/5258 , H05K3/225 , H01L2924/0002 , Y10S438/94
摘要： A method for fabricating custom integrated circuits includes the steps of 1) patterning the layer to be customized with standard precision masking techniques to define all possible connections, vias or cut-points, and 2) using a non-precision targeting energy beam to select the desired connections, vias or cut-points for customization. Consequently, the present invention requires no custom mask so that application specific integrated circuits (ASICs) can be produced with lower lead-time and costs when compared to prior methods. In other embodiments, a non-precision configuration mask may replace the targeting energy beam, where the configuration mask can be made by conventional mask-making techniques or by applying an opaque layer to a mask blank and using a targeting energy beam to selectively remove the desired portions of the opaque areas.
摘要翻译：一种用于制造定制集成电路的方法包括以下步骤：1）使用标准精密掩模技术对要定制的层进行图案化以定义所有可能的连接，通孔或切割点，以及2）使用非精确的瞄准能量束来选择所需的连接，通孔或切割点进行定制。因此，本发明不需要定制掩模，使得与现有方法相比，可以以较低的提前期和成本制造专用集成电路（ASIC）。在其他实施例中，非精密配置掩模可以替代瞄准能量束，其中配置掩模可以通过常规掩模制造技术制造，或者通过将不透明层施加到掩模坯料并且使用瞄准能量束来选择性地去除不透明区域的所需部分。

9. 发明授权

US5989783A Method of customizing integrated circuits by depositing two resist layers to selectively pattern layer interconnect material 失效
标题翻译：通过沉积两个抗蚀剂层来选择性地图案化层互连材料来定制集成电路的方法
公开(公告)号：US5989783A
公开(公告)日：1999-11-23
申请号：US39280
申请日：1998-03-12
申请人： Alan H. Huggins , John MacPherson
发明人： Alan H. Huggins , John MacPherson
IPC分类号： B65H37/00 , H01L21/00 , H01L21/683 , H01L21/768 , H01L23/525 , H05K3/22 , G03F7/00
CPC分类号： H01L21/67132 , B65H37/002 , H01L21/6838 , H01L21/76892 , H01L23/5254 , H05K3/225 , H01L21/76807 , H01L2924/0002 , Y10S156/943 , Y10T156/1179 , Y10T156/1983
摘要： A method for fabricating custom integrated circuits includes the steps of 1) patterning a photoresist layer on an insulative layer with a standard via precision mask to define all possible vias, and 2) using a targeting energy beam to select the desired via locations on a second photoresist layer, which are then etched and interconnections made, for customization or repair of the integrated circuit. Consequently, the present invention requires no custom mask so that application specific integrated circuits (ASICs) can be produced with lower lead-time and costs when compared to prior methods.
摘要翻译：一种用于制造定制集成电路的方法包括以下步骤：1）使用标准通孔精密掩模在绝缘层上图案化光致抗蚀剂层以限定所有可能的通孔，以及2）使用瞄准能量束来选择第二个所需的通孔位置光致抗蚀剂层，然后蚀刻并制成互连，用于定制或修复集成电路。因此，本发明不需要定制掩模，使得与现有方法相比，可以以较低的提前期和成本制造专用集成电路（ASIC）。

10. 发明授权

US5985518A Method of customizing integrated circuits using standard masks and targeting energy beams 失效
标题翻译：使用标准掩模定制集成电路并瞄准能量束的方法
公开(公告)号：US5985518A
公开(公告)日：1999-11-16
申请号：US823778
申请日：1997-03-24
申请人： Alan H. Huggins , John MacPherson
发明人： Alan H. Huggins , John MacPherson
IPC分类号： H01L21/768 , G03F7/00
CPC分类号： H01L21/76894
摘要： A method for fabricating custom integrated circuits includes the steps of 1) patterning the layer to be customized with standard precision masking techniques to define all possible connections, vias or cut-points, and 2) using a non-precision targeting energy beam to select the desired connections, vias or cut-points for customization. Consequently, the present invention requires no custom mask so that application specific integrated circuits (ASICs) can be produced with lower lead-time and costs when compared to prior methods. In other embodiments, a non-precision configuration mask may replace the targeting energy beam, where the configuration mask can be made by conventional mask-making techniques or by applying an opaque layer to a mask blank and using a targeting energy beam to selectively remove the desired portions of the opaque areas.
摘要翻译：一种用于制造定制集成电路的方法包括以下步骤：1）使用标准精密掩模技术对要定制的层进行图案化以定义所有可能的连接，通孔或切割点，以及2）使用非精确的瞄准能量束来选择所需的连接，通孔或切割点进行定制。因此，本发明不需要定制掩模，使得与现有方法相比，可以以较低的提前期和成本制造专用集成电路（ASIC）。在其他实施例中，非精密配置掩模可以替代瞄准能量束，其中配置掩模可以通过常规掩模制造技术制造，或者通过将不透明层施加到掩模坯料并且使用瞄准能量束来选择性地去除不透明区域的所需部分。

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