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1. 发明申请

US20110227603A1 Secure Anti-Tamper Integrated Layer Security Device Comprising Nano-Structures 审中-公开
标题翻译：包含纳米结构的安全防篡改集成层安全设备
公开(公告)号：US20110227603A1
公开(公告)日：2011-09-22
申请号：US13045880
申请日：2011-03-11
申请人： John Leon , James Yamaguchi , W. Eric Boyd , Volkan Ozguz
发明人： John Leon , James Yamaguchi , W. Eric Boyd , Volkan Ozguz
IPC分类号： H03K19/00 , H02H3/08 , G01R27/26 , G01R27/08
CPC分类号： H01L23/576 , H01L24/24 , H01L25/0657 , H01L25/16 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/3011 , H01L2924/00
摘要： A device and method using one or more electrically conductive nano-structures defined on one or more surfaces of a microelectronic circuit such as an integrated circuit die, microelectronic circuit package a stacked microelectronic circuit package, or on the surface of one or more layers in a stack of layers containing one or more ICs. The nano-structure is in connection with a monitoring circuit and acts as a “trip wire” to detect unauthorized tampering with the device or module. Such a monitoring circuit may include a power source such as an in-circuit or in-module battery and a “zeroization” circuit within the chip or package to erase the contents of a memory when the nano-structure is breached or altered. One or more electrically conductive nano-structures interconnect and reroute one or more electrical connections between one or more ICs to create an “invisible” set of electrical connections on the chip or stack to obfuscate an attempt to reverse engineer the device. microscope.
摘要翻译：限定在微电子电路的一个或多个表面上的一个或多个导电纳米结构的装置和方法，所述微电子电路例如集成电路管芯，微电子电路封装堆叠的微电子电路封装，或者在一个或多个层的表面上一堆包含一个或多个IC的层。纳米结构与监控电路相连，并用作“跳闸线”，以检测未经授权篡改设备或模块。这种监视电路可以包括芯片或封装内的诸如电路内或模块内电池的电源和“归零”电路，以在纳米结构被破坏或改变时擦除存储器的内容物。一个或多个导电纳米结构互连并重新路由一个或多个IC之间的一个或多个电连接，以在芯片或堆栈上产生“不可见”的电连接集合，以模糊设备的反向工程尝试。显微镜。

2. 发明申请

US20110031982A1 Tamper-resistant electronic circuit and module incorporating electrically conductive nano-structures 审中-公开
标题翻译：具有防篡改电子电路和包含导电纳米结构的模块
公开(公告)号：US20110031982A1
公开(公告)日：2011-02-10
申请号：US12806127
申请日：2010-08-04
申请人： John Leon , James Yamaguchi , Volkan Ozguz , W. Eric Boyd
发明人： John Leon , James Yamaguchi , Volkan Ozguz , W. Eric Boyd
IPC分类号： G01R27/28 , H02H3/08 , H05K7/00
CPC分类号： H01L23/576 , H01L25/0657 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A device and method are disclosed comprising one or more electrically conductive nano-structures defined on one or more surfaces of a microelectronic circuit such as an integrated circuit die, microelectronic circuit package (such as a TSOP, BGA or other prepackaged IC) a stacked microelectronic circuit package, or on the surface of one or more layers in a stack of layers containing one or more ICs.In one embodiment, the electrically conductive nano-structure is in electrical connection with a monitoring circuit and acts as a “trip wire” to detect unauthorized tampering with the device or module. Such a monitoring circuit may include a power source such as an in-circuit or in-module battery and a “zeroization” circuit within the chip or package to erase the contents of a memory when the electrically conductive nano-structure is breached or altered. The device may be configured to blow one or more fuses or overcurrent protection devices when the electrically conductive nano-structure is breached or altered.In a further embodiment, one or more electrically conductive nano-structures are used to interconnect and reroute one or more electrical connections between one or more ICs (or dummy leads and vias) to create an “invisible” set of electrical connections on the chip or stack to obfuscate an attempt to reverse engineer the device, i.e., a set of connections that cannot be observed by standard test means such as by X-ray or conventional microscope.
摘要翻译：公开了一种器件和方法，其包括限定在微电子电路的一个或多个表面上的一个或多个导电纳米结构，例如集成电路管芯，微电子电路封装（例如TSOP，BGA或其它预封装IC）堆叠微电子或者在包含一个或多个IC的层叠层中的一个或多个层的表面上。在一个实施例中，导电纳米结构与监控电路电连接，并用作“跳闸线”，以检测未经授权的篡改设备或模块。这样的监视电路可以包括诸如电路内或模块内电池的电源和芯片或封装内的“零化”电路，以在导电纳米结构被破坏或改变时擦除存储器的内容物。该装置可以被配置为当导电纳米结构被破坏或改变时吹送一个或多个保险丝或过电流保护装置。在另一个实施例中，使用一个或多个导电纳米结构来互连和重新路由一个或多个IC（或虚拟引线和通孔）之间的一个或多个电连接，以在芯片上产生“不可见”的电连接集合，或堆叠以模糊化设备的反向工程，即通过X射线或常规显微镜的标准测试手段无法观察到的一组连接。

3. 发明申请

US20100291735A1 STACKABLE SEMICONDUCTOR CHIP LAYER COMPRISING PREFABRICATED TRENCH INTERCONNECT VIAS 审中-公开
标题翻译：包含预制TRENCH INTERCONNECT VIAS的可堆叠半导体芯片层
公开(公告)号：US20100291735A1
公开(公告)日：2010-11-18
申请号：US12844555
申请日：2010-07-27
申请人： Volkan Ozguz , Angel Pepe , James Yamaguchi , W. Eric Boyd , Douglas Albert , Andrew Camien
发明人： Volkan Ozguz , Angel Pepe , James Yamaguchi , W. Eric Boyd , Douglas Albert , Andrew Camien
IPC分类号： H01L21/70 , H01L21/60
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/02 , H01L25/0657 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/00
摘要： A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.
摘要翻译：公开了一种可堆叠层和堆叠多层模块。单个集成电路裸片在晶片级进行测试和处理，以创建用于将电信号从芯片的有源表面路由到非活动表面的垂直区域互连通孔。使用一系列半导体处理步骤，在掩模版级上在晶片上的每个管芯上的预定位置处形成通孔。晶片被钝化，并且通孔填充有导电材料。裸片上的接合焊盘被暴露，并且应用来自用户选择的接合焊盘和通孔的金属化重新路由。然后将晶片分段以形成薄的可堆叠层，其可以使用导电通孔堆叠并垂直电互连，形成高密度电子模块，其可以进一步堆叠并互连以形成更大的更复杂的堆叠。

4. 发明授权

US07786562B2 Stackable semiconductor chip layer comprising prefabricated trench interconnect vias 有权
标题翻译：可堆叠半导体芯片层，包括预制沟槽互连通孔
公开(公告)号：US07786562B2
公开(公告)日：2010-08-31
申请号：US11150712
申请日：2005-06-10
申请人： Volkan Ozguz , Angel Pepe , James Yamaguchi , W. Eric Boyd , Douglas Albert , Andrew Camien
发明人： Volkan Ozguz , Angel Pepe , James Yamaguchi , W. Eric Boyd , Douglas Albert , Andrew Camien
IPC分类号： H01L23/02
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/02 , H01L25/0657 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/00
摘要： A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.
摘要翻译：公开了一种可堆叠层和堆叠多层模块。单个集成电路裸片在晶片级进行测试和处理，以创建用于将电信号从芯片的有源表面路由到非活动表面的垂直区域互连通孔。使用一系列半导体处理步骤，在掩模版级上在晶片上的每个管芯上的预定位置处形成通孔。晶片被钝化，并且通孔填充有导电材料。裸片上的接合焊盘被暴露，并且应用来自用户选择的接合焊盘和通孔的金属化重新路由。然后将晶片分段以形成薄的可堆叠层，其可以使用导电通孔堆叠并垂直电互连，形成高密度电子模块，其可以进一步堆叠并互连以形成更大的更复杂的堆叠。

5. 发明申请

US20080074144A1 Field programmable gate array utilizing dedicated memory stacks in a vertical layer format 有权
标题翻译：利用垂直层格式的专用存储器堆栈的现场可编程门阵列
公开(公告)号：US20080074144A1
公开(公告)日：2008-03-27
申请号：US11897938
申请日：2007-08-31
申请人： Volkan Ozguz , Randolph Carlson , Keith Gann , John Leon , W. Boyd
发明人： Volkan Ozguz , Randolph Carlson , Keith Gann , John Leon , W. Boyd
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , G01R31/318519 , G06F9/3802 , H03K19/177 , H03K19/17792
摘要： A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m.times.N where m is the number of word width bits per memory chip and N is the number of memory chips.
摘要翻译：现场可编程门阵列，耦合到FPGA的接入引线网络和电耦合到接入引线网络的多个存储器。 FPGA，接入引线网络和多个存储器被布置和配置为以可变字宽度操作，即具有在1和最大位数之间的字宽度。绝对最大字宽度可以与m.times.N一样大m其中m是每个存储器芯片的字宽度位数，N是存储器芯片的数量。

6. 发明申请

US20050122758A1 Field programmable gate array incorporating dedicated memory stacks 有权
标题翻译：集成专用存储器堆栈的现场可编程门阵列
公开(公告)号：US20050122758A1
公开(公告)日：2005-06-09
申请号：US11037490
申请日：2005-01-18
申请人： Randolph Carlson , Volkan Ozguz , Keith Gann , John Leon
发明人： Randolph Carlson , Volkan Ozguz , Keith Gann , John Leon
IPC分类号： G01R31/3185 , G06F9/38 , H03K19/177 , G11C5/06
CPC分类号： G01R31/318519 , G06F9/3802 , H01L2224/16227 , H01L2924/15311 , H03K19/17736 , H03K19/1776 , H03K19/1778 , H03K19/17796
摘要： A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m.times.N where m is the number of word width bits per memory chip and N is the number of memory chips.
摘要翻译：现场可编程门阵列，耦合到FPGA的接入引线网络和电耦合到接入引线网络的多个存储器。 FPGA，接入引线网络和多个存储器被布置和配置为以可变字宽度操作，即具有在1和最大位数之间的字宽度。绝对最大字宽度可以与m.times.N一样大m其中m是每个存储器芯片的字宽度位数，N是存储器芯片的数量。

7. 发明申请

US20050277288A1 Stackable semiconductor chip layer comprising prefabricated trench interconnect vias 有权
标题翻译：可堆叠半导体芯片层，包括预制沟槽互连通孔
公开(公告)号：US20050277288A1
公开(公告)日：2005-12-15
申请号：US11150712
申请日：2005-06-10
申请人： Volkan Ozguz , Angel Pepe , James Yamaguchi , W. Boyd , Douglas Albert , Andrew Camien
发明人： Volkan Ozguz , Angel Pepe , James Yamaguchi , W. Boyd , Douglas Albert , Andrew Camien
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/48 , H01L21/50 , H01L21/768 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/02 , H01L25/0657 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/00
摘要： A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.
摘要翻译：公开了一种可堆叠层和堆叠多层模块。单个集成电路裸片在晶片级进行测试和处理，以创建用于将电信号从芯片的有源表面路由到非活动表面的垂直区域互连通孔。使用一系列半导体处理步骤，在掩模版级上在晶片上的每个管芯上的预定位置处形成通孔。晶片被钝化，并且通孔填充有导电材料。裸片上的接合焊盘被暴露，并且应用来自用户选择的接合焊盘和通孔的金属化重新路由。然后将晶片分段以形成薄的可堆叠层，其可以使用导电通孔堆叠并垂直电互连，形成高密度电子模块，其可以进一步堆叠并互连以形成更大的更复杂的堆叠。

8. 发明申请

US20060087883A1 Anti-tamper module 有权
标题翻译：防篡改模块
公开(公告)号：US20060087883A1
公开(公告)日：2006-04-27
申请号：US11248659
申请日：2005-10-11
申请人： Volkan Ozguz , John Leon
发明人： Volkan Ozguz , John Leon
IPC分类号： G11C16/04 , H01L23/02 , H01L21/50 , H01L21/82 , G08B13/14 , G08B21/00
CPC分类号： H01L23/576 , G06F21/87 , H01L23/48 , H01L23/49816 , H01L25/0657 , H01L27/02 , H01L2223/6677 , H01L2224/16 , H01L2225/06548 , H01L2225/06551 , H01L2225/06565 , H01L2924/00011 , H01L2924/00014 , H01L2924/15311 , H01L2224/0401
摘要： An anti-tamper module is provided for protecting the contents and functionality of an integrated circuit incorporated in the module. The anti-tamper module is arranged in a stacked configuration having multiple layers. A connection layer is provided for connecting the module to an external system. A configurable logic device is provided for routing connections between the integrated circuit and the connection layer. Specifically, the configurable logic device is programmable to create logical circuits connecting at least one of the input/output connectors of the integrated circuit to at least one of the input/output connectors of the connection layer. Configuration information for programming the reconfigurable logic device is stored in a memory within the module.
摘要翻译：提供防篡改模块，用于保护组合在模块中的集成电路的内容和功能。防篡改模块被布置成具有多层的堆叠构造。提供连接层将模块连接到外部系统。提供了一种用于在集成电路和连接层之间路由连接的可配置逻辑器件。具体地，可配置逻辑器件是可编程的，以创建将集成电路的至少一个输入/输出连接器连接到连接层的至少一个输入/输出连接器的逻辑电路。用于编程可重构逻辑器件的配置信息存储在模块内的存储器中。

9. 发明申请

US20100271588A1 ELECTRONIC EYEGLASS FRAME 有权
标题翻译：电子眼镜架
公开(公告)号：US20100271588A1
公开(公告)日：2010-10-28
申请号：US12834526
申请日：2010-07-12
申请人： William Kokonaski , Ronald D. Blum , Tiziano Tabacchi , Martin Boch , Massimo Pinazza , Scott N. Richman , Volkan Ozguz , Joshua N. Haddock
发明人： William Kokonaski , Ronald D. Blum , Tiziano Tabacchi , Martin Boch , Massimo Pinazza , Scott N. Richman , Volkan Ozguz , Joshua N. Haddock
IPC分类号： G02C7/10
CPC分类号： G02C7/101 , G02C7/08 , G02C7/083 , G02C11/00 , G02C11/10
摘要： The present invention generally relates to integrating electronic components into an electro-active frame for driving electro-active focusing lenses. This is accomplished in a cosmetically pleasing manner that allows a platform of frame systems to be built from a single electronic module. Specifically, the present invention discloses controlling an electro-active lens in a deliberate, hands free manner that gives the user control of the electro-active lens.
摘要翻译：本发明一般涉及将电子部件集成到用于驱动电动聚焦透镜的电动式框架中。这是以令人愉快的方式完成的，允许从单个电子模块构建框架系统的平台。具体而言，本发明公开了以有意的，无手的方式控制电动透镜，使得用户能够控制电动透镜。

10. 发明申请

US20070035033A1 Stackable tier structure comprising high density feedthrough 有权
标题翻译：可堆叠层结构包括高密度馈通
公开(公告)号：US20070035033A1
公开(公告)日：2007-02-15
申请号：US11524090
申请日：2006-09-20
申请人： Volkan Ozguz , Jonathan Stern
发明人： Volkan Ozguz , Jonathan Stern
IPC分类号： H01L23/52
CPC分类号： H01L23/52 , H01L21/4803 , H01L21/4846 , H01L23/13 , H01L23/147 , H01L23/3672 , H01L23/49811 , H01L23/49827 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L25/50 , H01L2224/05001 , H01L2224/16 , H01L2224/24227 , H01L2224/32188 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2225/06589 , H01L2225/1035 , H01L2225/1058 , H01L2225/1094 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07811 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/15312 , H01L2924/1627 , H01L2924/3011 , H01L2924/00
摘要： A stackable tier structure comprising one or more integrated circuit die and one or more feedthrough structures is disclosed. The 1/0 pads of the integrated circuit die are electrically rerouted using conductive traces from the first side of the tier structure to a feedthrough structure comprising one ore more conductive structures. The conductive structures electrically route the integrated die pads to predetermined locations on the second side of the tier structure. The predetermined locations, such as exposed conductive pads or conductive posts, in turn, may be interconnected to a second tier structure or other circuitry to permit the fabrication of a three-dimensional microelectronic module comprising one or more stacked tiers.
摘要翻译：公开了一种包括一个或多个集成电路管芯和一个或多个馈通结构的可堆叠层结构。集成电路管芯的1/0焊盘使用从层结构的第一侧到包括一个或多个导电结构的馈通结构的导电迹线进行电气重新布线。导电结构将集成管芯焊盘电连接到层结构的第二侧上的预定位置。反过来，诸如暴露的导电焊盘或导电柱的预定位置可以互连到第二层结构或其他电路，以允许制造包括一个或多个堆叠层的三维微电子模块。

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