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1. 发明授权

US5517662A Multiprocessor system with distributed memory 失效
标题翻译：具有分布式存储器的多处理器系统
公开(公告)号：US5517662A
公开(公告)日：1996-05-14
申请号：US335926
申请日：1994-11-08
申请人： John J. Coleman , Ronald G. Coleman , Owen K. Monroe , Robert F. Stucke , Elizabeth A. Vanderbeck , Stephen E. Bello , John R. Hattersley , Kien A. Hua , David R. Pruett , Gerald F. Rollo
发明人： John J. Coleman , Ronald G. Coleman , Owen K. Monroe , Robert F. Stucke , Elizabeth A. Vanderbeck , Stephen E. Bello , John R. Hattersley , Kien A. Hua , David R. Pruett , Gerald F. Rollo
IPC分类号： G06F15/16 , G06F15/173 , G06F13/14
CPC分类号： G06F15/17375
摘要： A parallel computer system is disclosed comprising a plurality of high level processors joined together using a cross-point or cross-bar switch. The system includes an adapter between each processor and the switch. Protocol processing to drive the switch, transfer pages and schedule transmissions between the processors is performed by the adapter. The protocol use the notion of typed or tagged buffer management that allows a client to bind the semantics of a message being sent or received. These semantics specify behaviors in the protocol when message packets depart or when they arrive.
摘要翻译：公开了一种并行计算机系统，其包括使用交叉点或横杆开关连接在一起的多个高级处理器。该系统包括每个处理器和交换机之间的适配器。用于驱动交换机的协议处理，传送页面和调度处理器之间的传输由适配器执行。该协议使用类型化或标记的缓冲区管理的概念，允许客户端绑定正在发送或接收的消息的语义。这些语义在消息包离开或到达时指定协议中的行为。

2. 发明授权

US5287494A Sorting/merging tree for determining a next tournament champion in each cycle by simultaneously comparing records in a path of the previous tournament champion 失效
标题翻译：排序/合并树，以确定每个周期中的下一届锦标赛冠军，同时比较之前比赛冠军的路径中的记录
公开(公告)号：US5287494A
公开(公告)日：1994-02-15
申请号：US599609
申请日：1990-10-18
申请人： Leslie C. Garcia , David B. Lindquist , Gerald F. Rollo
发明人： Leslie C. Garcia , David B. Lindquist , Gerald F. Rollo
IPC分类号： G06F7/24 , G06F7/36 , G06F15/78 , G06F17/30 , G06F7/22
CPC分类号： G06F15/8053 , G06F7/24 , G06F7/36 , G06F2207/222 , Y10S707/99937
摘要： A tree sorter having hardware logic node registers and output selectors plus comparators enables a vector processor to perform sort and merge operations. A system and method of providing one output record each cycle provides performance enhancement over similar scalar operation. Storage to storage traffic is drastically reduced because the hardware tree and update logic is implemented in the Vector Processor. Vector registers provide input data to the hardware tree structure. Output records sorted by key together with address ID are placed in storage. Multiple Vector count and multiple Vector Interruption Index (VIX) operation, string length and merge masks are used in conjunction with a vector merge instruction. The data input record key field has both long and short formats. Actual key data or codewords may be used. The vector merge forms a new codeword when compare equal codewords are encountered. By storing sorted keys (codewords) plus the address ID, reuse of codewords (in formation of longer strings, etc.) is made possible.
摘要翻译：具有硬件逻辑节点寄存器和输出选择器加比较器的树分类器使矢量处理器能够执行排序和合并操作。每个周期提供一个输出记录的系统和方法提供了超过类似标量运算的性能增强。由于在向量处理器中实现了硬件树和更新逻辑，因此存储流量的存储大大减少。向量寄存器向硬件树结构提供输入数据。通过密钥和地址ID排序的输出记录放在存储器中。多向量计数和多个向量中断索引（VIX）操作，字符串长度和合并掩码与向量合并指令结合使用。数据输入记录键字段具有长格式和短格式。可以使用实际密钥数据或码字。当遇到比较相等的码字时，向量合并形成新的码字。通过存储排序的密钥（码字）加上地址ID，可以重用码字（形成较长的字符串等）。

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