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1. 发明授权

US08861864B2 Image feature detection based on application of multiple feature detectors 有权
标题翻译：基于多个特征检测器的图像特征检测
公开(公告)号：US08861864B2
公开(公告)日：2014-10-14
申请号：US12855502
申请日：2010-08-12
申请人： John Hong , Onur C. Hamsici , Jose R. dos Santos , Joseph Huang , Chong U. Lee , Yuriy Reznik , Mark K. Murphy , Devender A. Yamakawa
发明人： John Hong , Onur C. Hamsici , Jose R. dos Santos , Joseph Huang , Chong U. Lee , Yuriy Reznik , Mark K. Murphy , Devender A. Yamakawa
IPC分类号： G06K9/46
CPC分类号： G06K9/4671
摘要： In a particular embodiment, a method includes applying a first feature detector to a portion of an image to detect a first set of features. The first set of features is used to locate a region of interest, and a boundary corresponding to the region of interest is determined. The method also includes displaying the boundary at a display. In response to receiving user input to accept the displayed boundary, a second feature detector is applied to an area of the image encapsulated by the boundary.
摘要翻译：在特定实施例中，一种方法包括将第一特征检测器应用于图像的一部分以检测第一组特征。第一组特征用于定位感兴趣区域，并且确定与感兴趣区域相对应的边界。该方法还包括在显示器上显示边界。响应于接收用户输入以接受所显示的边界，第二特征检测器被应用于由边界封装的图像的区域。

2. 发明授权

US09099999B1 Adjustable drive strength input-output buffer circuitry 有权
标题翻译：可调驱动强度输入输出缓冲电路
公开(公告)号：US09099999B1
公开(公告)日：2015-08-04
申请号：US13485768
申请日：2012-05-31
申请人： Bonnie I. Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Tony Ngai , Zhe Li , Hong Shi
发明人： Bonnie I. Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Tony Ngai , Zhe Li , Hong Shi
IPC分类号： H01L29/73 , H01L29/40 , H03K17/00 , H05K1/18 , H01L25/065 , H01L27/06
CPC分类号： H03K17/00 , H01L25/0652 , H01L25/0657 , H01L27/0688 , H01L2224/16145 , H01L2224/16225 , H01L2924/0002 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H05K1/144 , H05K1/181 , H05K2201/045 , H05K2201/10378 , H05K2201/10674 , H05K2201/10734 , H01L2924/00
摘要： An integrated circuit in a multi-chip package is provided. The integrated circuit may include adjustable interface circuitry configured to interface with other off-chip components. In particular, the adjustable interface circuitry may include a microbump input-output buffer operable to drive signals off of the integrated circuit and operable to receive signals from other integrated circuits in the multi-chip package via a microbump. The microbump input-output buffer may include output buffers and input buffers. The output buffers may have programmable drive strengths and may each be selectively switched in and out of use depending on the desired application. Each output buffer may include a level shifter, a buffer circuit, and multiple inverter-like circuits each of which can be turned on or off to adjust the drive strength of that output buffer.
摘要翻译：提供了一种多芯片封装中的集成电路。该集成电路可以包括被配置为与其它片外部件接口的可调节接口电路。特别地，可调接口电路可以包括微控制输入 - 输出缓冲器，其可操作用于驱动离开集成电路的信号，并且可操作以经由微型小型接收器从多芯片封装中的其他集成电路接收信号。微控制输入 - 输出缓冲器可以包括输出缓冲器和输入缓冲器。输出缓冲器可以具有可编程驱动强度，并且可以根据期望的应用选择性地切换和使用。每个输出缓冲器可以包括电平移位器，缓冲电路和多个类似逆变器的电路，每个可以导通或关断以调整该输出缓冲器的驱动强度。

3. 发明授权

US08624647B2 Duty cycle correction circuit for memory interfaces in integrated circuits 有权
标题翻译：集成电路中存储器接口的占空比校正电路
公开(公告)号：US08624647B2
公开(公告)日：2014-01-07
申请号：US12690064
申请日：2010-01-19
申请人： Yan Chong , Joseph Huang , Pradeep Nagarajan , Chiakang Sung
发明人： Yan Chong , Joseph Huang , Pradeep Nagarajan , Chiakang Sung
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03K5/151 , H03K5/1534 , H03K2005/00019
摘要： Circuits and a method for correcting duty cycle distortions in an integrated circuit (IC) are disclosed. The IC includes a splitter circuit that is coupled to receive a clock signal. The clock signal is split into two different clock signals. One of the clock signals is an inverted version of the other. A delay circuit is coupled to each of the clock signals. Each of the delay circuits generates a delayed version of the corresponding clock signal. A corrector circuit is coupled to receive both the delayed versions of the clock signals. The corrector circuit generates a clock output signal with a corrected duty cycle.
摘要翻译：公开了用于校正集成电路（IC）中的占空比失真的电路和方法。 IC包括被耦合以接收时钟信号的分离器电路。时钟信号分为两个不同的时钟信号。其中一个时钟信号是另一个的反转版本。延迟电路耦合到每个时钟信号。每个延迟电路产生相应时钟信号的延迟版本。耦合校正器电路以接收时钟信号的延迟版本。校正器电路产生具有校正占空比的时钟输出信号。

4. 外观设计

USD672361S1 USB flash drive 有权
标题翻译： USB闪存盘
公开(公告)号：USD672361S1
公开(公告)日：2012-12-11
申请号：US29415773
申请日：2012-03-14
申请人： Joseph Huang
设计人： Joseph Huang

5. 发明授权

US08273268B2 Electrically conductive polyolefin blends 有权
标题翻译：导电聚烯烃共混物
公开(公告)号：US08273268B2
公开(公告)日：2012-09-25
申请号：US12673055
申请日：2008-08-01
申请人： Joseph Huang , George P. Kipouras
发明人： Joseph Huang , George P. Kipouras
IPC分类号： H01B1/24 , H01B1/02 , C09B67/00
CPC分类号： H01B1/24 , C08K3/04 , C08L23/14 , C08L2205/02 , H05K9/0083 , C08L2666/06
摘要： An electrically conductive polymer compound is disclosed. The compound comprises a matrix comprising two polyolefin copolymers having different melt mass flow rates and electrically conductive functional additive particles dispersed in the matrix. The compound is useful for making extruded and molded plastic articles that need electrical conductivity.
摘要翻译：公开了一种导电高分子化合物。该化合物包含一种包含两种具有不同熔体质量流动速率的聚烯烃共聚物和分散在基质中的导电功能添加剂颗粒的基体。该化合物可用于制备需要导电性的挤出和模制的塑料制品。

6. 发明申请

US20120146700A1 MULTIPLE DATA RATE INTERFACE ARCHITECTURE 有权
标题翻译：多种数据速率接口架构
公开(公告)号：US20120146700A1
公开(公告)日：2012-06-14
申请号：US13324354
申请日：2011-12-13
申请人： Philip Pan , Chiakang Sung , Joseph Huang , Yan Chong , Bonnie I. Wang
发明人： Philip Pan , Chiakang Sung , Joseph Huang , Yan Chong , Bonnie I. Wang
IPC分类号： H03K5/06
CPC分类号： H03K19/017581 , H03K19/17744
摘要： Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.
摘要翻译：用于实现可编程逻辑器件的高速多数据速率接口架构的方法和电路。本发明将I / O引脚及其对应的寄存器分为独立的多数据速率I / O模块，每个I / O引脚具有至少一个专用于选通信号DQS的引脚和其他引脚用于DQ数据信号。模块化架构便于引脚从一代PLD迁移到下一代。

7. 发明申请

US20110297890A1 ELECTRICALLY CONDUCTIVE POLYOLEFIN BLENDS 有权
标题翻译：电导电聚苯乙烯
公开(公告)号：US20110297890A1
公开(公告)日：2011-12-08
申请号：US12673055
申请日：2008-08-01
申请人： Joseph Huang , George P. Kipouras
发明人： Joseph Huang , George P. Kipouras
IPC分类号： H01B1/24 , H01B1/22 , H01B1/20
CPC分类号： H01B1/24 , C08K3/04 , C08L23/14 , C08L2205/02 , H05K9/0083 , C08L2666/06
摘要： An electrically conductive polymer compound is disclosed. The compound comprises a matrix comprising two polyolefin copolymers having different melt mass flow rates and electrically conductive functional additive particles dispersed in the matrix. The compound is useful for making extruded and molded plastic articles that need electrical conductivity.
摘要翻译：公开了一种导电高分子化合物。该化合物包含一种包含两种具有不同熔体质量流动速率的聚烯烃共聚物和分散在基质中的导电功能添加剂颗粒的基体。该化合物可用于制备需要导电性的挤出和模制的塑料制品。

8. 发明授权

US08029299B1 Cover unit 失效
标题翻译：封面单元
公开(公告)号：US08029299B1
公开(公告)日：2011-10-04
申请号：US12913853
申请日：2010-10-28
申请人： Joseph Huang
发明人： Joseph Huang
IPC分类号： H01R13/44
CPC分类号： H01R13/5213
摘要： A cover unit for a USB flash disk, wherein a seat hole is provided at the middle position of a seat, an engaging structure with an elastic element is pivotally provided in the cover unit to provide restoring force, an engaging plate of the engaging structure can be extended into the opening of the USB connector, and by using protruding blocks provided on the engaging plate in matching with directional holes on the USB connector, the holes are covered by the blocks to seal the USB connector; meantime when a stopping plate on the engaging plate is pressed, engaging of the protruding blocks with the directional holes can be relieved, thereby the whole cover unit can be removed.
摘要翻译：一种用于USB闪存盘的盖单元，其中在座的中间位置设置有座孔，具有弹性元件的接合结构可枢转地设置在盖单元中以提供恢复力，接合结构的接合板可以延伸到USB连接器的开口，并且通过使用设置在接合板上的突出块来匹配USB连接器上的定向孔，孔被块覆盖以密封USB连接器; 同时当按压接合板上的止动板时，可以释放突出块与定向孔的接合，从而可以去除整个盖单元。

9. 发明申请

US20110227606A1 PROGRAMMABLE HIGH-SPEED INTERFACE 有权
标题翻译：可编程高速接口
公开(公告)号：US20110227606A1
公开(公告)日：2011-09-22
申请号：US13149168
申请日：2011-05-31
申请人： Bonnie I. Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
发明人： Bonnie I. Wang , Chiakang Sung , Joseph Huang , Khai Nguyen , Philip Pan
IPC分类号： H03K19/0175 , H03K3/00
CPC分类号： H03K19/17744 , H03K19/0175 , H03K19/017509 , H03K19/017581 , H03K19/1774 , H03K19/17788
摘要： Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.
摘要翻译：提供高速或低速灵活的输入和输出的方法和设备。提供具有高速输入，高速输出，低速或中速输入以及低速或中速输出的输入和输出结构。选择其中一个输入和输出电路，并取消选择其他电路。高速输入和输出电路相对简单，在一个示例中，仅具有用于控制线输入的清除信号，并且能够与集成电路的核心内的低速电路接口。低速或中速输入和输出电路比较灵活，例如具有预置，使能和清除作为控制线路输入，并且能够支持JTAG边界测试。这些并行高速和低速电路是用户可选择的，使得输入输出结构根据应用的要求在速度和功能之间进行优化。

10. 发明授权

US07990786B2 Read-leveling implementations for DDR3 applications on an FPGA 有权
标题翻译： FPGA上DDR3应用程序的读取级别实现
公开(公告)号：US07990786B2
公开(公告)日：2011-08-02
申请号：US12539582
申请日：2009-08-11
申请人： Michael H. M. Chu , Joseph Huang , Chiakang Sung , Yan Chong , Andrew Bellis , Philip Clarke , Manoj B. Roge
发明人： Michael H. M. Chu , Joseph Huang , Chiakang Sung , Yan Chong , Andrew Bellis , Philip Clarke , Manoj B. Roge
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , H03L7/06 , H03L7/0812
摘要： Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting.
摘要翻译：用于将数据从设备的输入时钟域传送到核心时钟域的电路，方法和装置。一个例子是通过在输入和电路之间使用重新定时元件实现这一点。重新定时元素通过逐渐扫描延迟并在每个增量处接收数据进行校准。平均接收无差错数据的最小和最大延迟。然后可以使用该平均值来调整插入由输入选通信号计时的输入寄存器和由核心时钟信号计时的输出寄存器之间的输入路径中的电路元件的定时。在一个示例中，输入信号可以被延迟与延迟设置相对应的量。在其他示例中，使用输入寄存器和输出寄存器之间的中间寄存器来注册每个输入信号，其中时钟信号被延迟与延迟设置相对应的量。

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