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1. 发明授权

US06787472B2 Utilization of disappearing silicon hard mask for fabrication of semiconductor structures 失效
标题翻译：消耗硅硬掩模的利用用于制造半导体结构
公开(公告)号：US06787472B2
公开(公告)日：2004-09-07
申请号：US10352464
申请日：2003-01-27
申请人： John H. Givens , Mark E. Jost
发明人： John H. Givens , Mark E. Jost
IPC分类号： H01L21302
CPC分类号： H01L27/10882 , H01L21/28518 , H01L21/31144 , H01L21/76802 , H01L21/7684 , H01L21/76843 , H01L21/76855 , H01L21/76897 , H01L27/10814 , H01L27/10855 , H01L27/10888
摘要： A method of forming structures in semiconductor devices through a buffer or insulator layer comprises the use of a silicon hard mask between a patterned resist layer for etching the structures and an underlying barrier layer. The silicon hard mask acts as a backup to the resist layer, preventing the potential etching of the barrier layer which is protected by the resist layer by acting as an etch stop if the first resist layer is ablated away during the etching of the openings for the structures. This allows for a thinner layer of resist material to be used. After etching, a layer of silicidable material is deposited over the silicon hard mask and the resulting structure is annealed to turn the silicon hard mask into a silicide material. The silicide material is removed by an abrasive method, such as by chemical mechanical planarization.
摘要翻译：通过缓冲层或绝缘体层在半导体器件中形成结构的方法包括在蚀刻结构的图案化抗蚀剂层和下面的阻挡层之间使用硅硬掩模。硅硬掩模用作对抗蚀剂层的支撑，防止如果第一抗蚀剂层在用于蚀刻的开口的蚀刻期间被消除，则通过作为蚀刻停止来防止被抗蚀剂层保护的势垒层的潜在蚀刻结构。这允许使用更薄的抗蚀剂材料层。在蚀刻之后，在硅硬掩模上沉积一层可硅化材料，并将所得结构退火以将硅硬掩模转变为硅化物材料。通过研磨方法例如通过化学机械平面化除去硅化物材料。

2. 发明授权

US06689693B2 Methods for utilization of disappearing silicon hard mask for fabrication of semiconductor structures 有权
标题翻译：利用消失的硅硬掩模制造半导体结构的方法
公开(公告)号：US06689693B2
公开(公告)日：2004-02-10
申请号：US10267063
申请日：2002-10-07
申请人： John H. Givens , Mark E. Jost
发明人： John H. Givens , Mark E. Jost
IPC分类号： H01L21302
CPC分类号： H01L27/10882 , H01L21/28518 , H01L21/31144 , H01L21/76802 , H01L21/7684 , H01L21/76843 , H01L21/76855 , H01L21/76897 , H01L27/10814 , H01L27/10855 , H01L27/10888
摘要： A method of forming structures in semiconductor devices through a buffer or insulator layer comprises the use of a silicon hard mask between a patterned resist layer for etching the structures and an underlying barrier layer. The silicon hard mask acts as a backup to the resist layer, preventing the potential etching of the barrier layer which is protected by the resist layer by acting as an etch stop if the first resist layer is ablated away during the etching of the openings for the structures. After etching, a layer of silicidable material is deposited over the silicon hard mask and the resulting structure is annealed to turn the silicon hard mask into a silicide material. The silicide material is removed by an abrasive method, such as by CMP.
摘要翻译：通过缓冲层或绝缘体层在半导体器件中形成结构的方法包括在蚀刻结构的图案化抗蚀剂层和下面的阻挡层之间使用硅硬掩模。硅硬掩模用作对抗蚀剂层的支撑，防止如果第一抗蚀剂层在用于蚀刻的开口的蚀刻期间被消除，则通过作为蚀刻停止来防止被抗蚀剂层保护的势垒层的潜在蚀刻结构。在蚀刻之后，在硅硬掩模上沉积一层可硅化材料，并将所得结构退火以将硅硬掩模转变为硅化物材料。通过研磨方法，例如通过CMP去除硅化物材料。

3. 发明授权

US06534408B2 Utilization of disappearing silicon hard mask for fabrication of semiconductor structures 有权
公开(公告)号：US06534408B2
公开(公告)日：2003-03-18
申请号：US10107764
申请日：2002-03-27
申请人： John H. Givens , Mark E. Jost
发明人： John H. Givens , Mark E. Jost
IPC分类号： H01L21302
CPC分类号： H01L27/10882 , H01L21/28518 , H01L21/31144 , H01L21/76802 , H01L21/7684 , H01L21/76843 , H01L21/76855 , H01L21/76897 , H01L27/10814 , H01L27/10855 , H01L27/10888
摘要： A method of forming structures in semiconductor devices through a buffer or insulator layer comprising the use of a silicon hard mask between a patterned resist layer for etching the structures and an underlying barrier layer. The silicon hard mask acts as a backup to the resist layer, preventing the potential etching of the barrier layer which is protected by the resist layer by acting as an etch stop if the first resist layer is ablated away during the etching of the openings for the structures. This allows for a thinner layer of resist material to be used. After etching, a layer of silicidable material is deposited over the silicon hard mask and the resulting structure is annealed to turn the silicon hard mask into a silicide material. The silicide material is removed by an abrasive method, such as by chemical mechanical planarization.

4. 发明授权

US06461963B1 Utilization of disappearing silicon hard mask for fabrication of semiconductor structures 有权
标题翻译：消耗硅硬掩模的利用用于制造半导体结构
公开(公告)号：US06461963B1
公开(公告)日：2002-10-08
申请号：US09651462
申请日：2000-08-30
申请人： John H. Givens , Mark E. Jost
发明人： John H. Givens , Mark E. Jost
IPC分类号： H01L21302
CPC分类号： H01L27/10882 , H01L21/28518 , H01L21/31144 , H01L21/76802 , H01L21/7684 , H01L21/76843 , H01L21/76855 , H01L21/76897 , H01L27/10814 , H01L27/10855 , H01L27/10888
摘要： A method of forming structures in semiconductor devices through a buffer or insulator layer comprising the use of a silicon hard mask between a patterned resist layer for etching the structures and an underlying barrier layer. The silicon hard mask acts as a backup to the resist layer, preventing the potential etching of the barrier layer which is protected by the resist layer by acting as an etch stop if the first resist layer is ablated away during the etching of the openings for the structures. This allows for a thinner layer of resist material to be used because no additional resist is required to provide a “margin of error” during the etching to assure the integrity of the barrier layer. After etching, a layer of silicidable material is deposited over the silicon hard mask and the resulting structure is annealed to turn the silicon hard mask into a silicide material. The silicide material is removed by an abrasive method, such as by CMP. A silicon hard mask is difficult to remove by such an abrasive method. However, a silicide material is conducive to abrasive removal. The deposition and annealing of the silicidable material can be a part of the formation of a contact silicide layer at the bottom of a contact opening during the formation of a bitline contact or a capacitor contact.
摘要翻译：一种通过缓冲层或绝缘体层在半导体器件中形成结构的方法，包括在用于蚀刻结构的图案化抗蚀剂层和下面的阻挡层之间使用硅硬掩模。硅硬掩模用作对抗蚀剂层的支撑，防止如果第一抗蚀剂层在用于蚀刻的开口的蚀刻期间被消除，则通过作为蚀刻停止来防止被抗蚀剂层保护的势垒层的潜在蚀刻结构。这允许使用更薄的抗蚀剂材料层，因为在蚀刻期间不需要额外的抗蚀剂来提供“误差范围”，以确保阻挡层的完整性。在蚀刻之后，在硅硬掩模上沉积一层可硅化材料，并将所得结构退火以将硅硬掩模转变为硅化物材料。通过研磨方法，例如通过CMP去除硅化物材料。通过这种研磨方法难以除去硅硬掩模。然而，硅化物材料有利于研磨去除。可硅化材料的沉积和退火可以是在形成位线接触或电容器接触期间在接触开口底部形成接触硅化物层的一部分。

5. 发明授权

US06828252B2 Method of etching a contact opening 失效
标题翻译：刻蚀接触孔的方法
公开(公告)号：US06828252B2
公开(公告)日：2004-12-07
申请号：US10830274
申请日：2004-04-21
申请人： Mark E. Jost , Chris W. Hill
发明人： Mark E. Jost , Chris W. Hill
IPC分类号： H03L21302
CPC分类号： H01L21/02129 , H01L21/022 , H01L21/02271 , H01L21/31116 , H01L21/31625 , H01L21/76802
摘要： A chemical vapor deposition method includes providing a semiconductor substrate within a chemical vapor deposition chamber. At least one liquid deposition precursor is vaporized with a vaporizer to form a flowing vaporized precursor stream. The flowing vaporized precursor stream is initially bypassed from entering the chamber for a first period of time while the substrate is in the deposition chamber. After the first period of time, the flowing vaporized precursor stream is directed to flow into the chamber with the substrate therein under conditions effective to chemical vapor deposit a layer over the substrate. A method of etching a contact opening over a node location on a semiconductor substrate is disclosed.
摘要翻译：化学气相沉积方法包括在化学气相沉积室内提供半导体衬底。至少一个液体沉积前体用蒸发器蒸发以形成流动的蒸发的前体物流。当衬底处于沉积室中时，首先将流动的汽化的前体物流绕过第一时间段进入该室。在第一时间段之后，在有效使化学气相沉积衬底上的层的条件下，使流动的蒸发的前体物流被引导到其中具有衬底的腔室中。公开了一种在半导体衬底上的节点位置上蚀刻接触开口的方法。

6. 发明授权

US6153527A Semiconductor processing method of making electrical contact to a node received within a mass of insulating dielectric material 有权
标题翻译：与接收在绝缘介电材料块内的节点进行电接触的半导体加工方法
公开(公告)号：US6153527A
公开(公告)日：2000-11-28
申请号：US441718
申请日：1999-11-16
申请人： Mark E. Jost , Phillip G. Wald
发明人： Mark E. Jost , Phillip G. Wald
IPC分类号： H01L21/02 , H01L21/768 , H01L21/8242 , H01L23/485 , H01L27/105 , H01L27/108 , H01L21/311
CPC分类号： H01L27/10844 , H01L21/768 , H01L21/76802 , H01L21/76804 , H01L21/76885 , H01L23/485 , H01L27/105 , H01L27/10808 , H01L27/10852 , H01L28/40 , H01L28/82 , H01L28/84 , H01L28/86 , H01L28/90 , H01L2924/0002
摘要： A semiconductor processing method of making electrical contact to a node received within a mass of insulating dielectric material includes, a) providing a node within a mass of insulating dielectric material; b) first stage etching into the insulating dielectric material over the node in a manner substantially selective relative to the node; c) after the first stage etching, second stage etching the dielectric material in a manner which increases a degree of sidewall polymerization over that occurring in the first stage etching and in a manner substantially selective relative to the node; and d) after the second stage etching, third stage etching the dielectric material with a degree of sidewall polymerization which is less than that of the second stage etching and in a manner substantially selective relative to the first node. An alternate method provides an etch stop annulus cap 70 overlying an electrically conductive ring 62 which projects from a primary insulating layer 54. A secondary insulating 74 is then provided outwardly of the etch stop annulus cap. A second contact opening 76 is patterned and etched through the second insulating layer relative to the first contact opening and to the etch stop annulus cap, with the second contact opening having a wider target area 80 than would otherwise be provided if the annulus cap were not present. Aspects of the invention have significant utility in the fabrication of bit line over capacitor arrays of memory cells.
摘要翻译：对接收在绝缘介电材料块内的节点进行电接触的半导体处理方法包括：a）在绝缘介电材料块内提供节点; b）以相对于节点基本上选择性的方式在节点上第一级蚀刻到绝缘介电材料中; c）在第一阶段蚀刻之后，第二阶段以相对于该节点基本上选择性的方式，以增加与第一阶段蚀刻中发生的侧壁聚合程度相似的方式来蚀刻电介质材料; 以及d）在第二阶段蚀刻之后，第三阶段以比第二阶段蚀刻小的侧壁聚合程度以相对于第一节点基本选择的方式蚀刻电介质材料。替代方法提供了覆盖从主绝缘层54突出的导电环62的蚀刻阻挡环盖70.然后在蚀刻停止环形盖的外侧设置次级绝缘体74。第二接触开口76相对于第一接触开口和蚀刻停止环形盖被图案化和蚀刻通过第二绝缘层，其中第二接触开口具有比否则将提供的更宽的目标区域80 当下。本发明的方面在存储器单元的电容器阵列上的位线的制造中具有显着的用途。

7. 发明授权

US6046094A Method of forming wafer alignment patterns 失效
标题翻译：形成晶圆对准图案的方法
公开(公告)号：US6046094A
公开(公告)日：2000-04-04
申请号：US124933
申请日：1998-07-29
申请人： Mark E. Jost , David J. Hansen , Steven M. McDonald
发明人： Mark E. Jost , David J. Hansen , Steven M. McDonald
IPC分类号： G03F7/20 , G03F9/00 , H01L21/00 , H01L23/544 , H01L21/76
CPC分类号： H01L21/67282 , G03F7/70 , G03F9/70 , H01L23/544 , H01L2223/5442 , H01L2223/54453 , H01L2924/0002 , Y10S148/102 , Y10S438/975
摘要： A semiconductor processing method of forming integrated circuitry on a semiconductor wafer includes, a) forming at least two discrete wafer alignment patterns on the wafer, the two discrete alignment patterns having respective series of elevation steps provided therein; and b) while fabricating integrated circuitry elsewhere on the wafer, processing a first portion of at least one of the alignment patterns differently from a second portion of the one alignment pattern to render the first portion to be different from the second portion in the one alignment pattern. Such preferably superimposes a secondary step, most preferably of the same degree, over only a portion of the elevation steps in at least one of the wafer alignment patterns. Further, a semiconductor processing method of forming integrated circuitry on a semiconductor wafer includes, i) forming at least two discrete wafer alignment patterns on the wafer, the two discrete alignment patterns having respective series of elevation steps provided therein; and ii) while fabricating integrated circuitry elsewhere on the wafer, processing one of the alignment patterns differently from the other to render the one alignment pattern to be different from the other alignment pattern.
摘要翻译：在半导体晶片上形成集成电路的半导体处理方法包括：a）在晶片上形成至少两个离散晶片对准图案，所述两个离散对准图案具有在其中提供的相应的一系列升高台阶; 以及b）当在所述晶片上的其它地方制造集成电路时，处理所述对准图案中的至少一个的第一部分与所述一个对准图案的第二部分不同，以使所述第一部分在所述一个对准中与所述第二部分不同模式。这样优选地，在至少一个晶片对准图案中，仅在升高台阶的一部分上叠加最优选相同程度的次级台阶。此外，在半导体晶片上形成集成电路的半导体处理方法包括：i）在晶片上形成至少两个离散的晶片对准图案，所述两个离散对准图案具有在其中提供的相应的一系列升高台阶; 以及ii）当在晶片上的其他地方制造集成电路时，将对准图案之一与另一个不同地进行处理，以使得一个对准图案与另一个对准图案不同。

8. 发明授权

US6037261A Semiconductor processing method of making electrical contact to a node received within a mass of insulating dielectric material 失效
标题翻译：与接收在绝缘介电材料块内的节点进行电接触的半导体加工方法
公开(公告)号：US6037261A
公开(公告)日：2000-03-14
申请号：US28045
申请日：1998-02-23
申请人： Mark E. Jost , Phillip G. Wald
发明人： Mark E. Jost , Phillip G. Wald
IPC分类号： H01L21/02 , H01L21/768 , H01L21/8242 , H01L23/485 , H01L27/105 , H01L27/108 , H01L21/3065
CPC分类号： H01L27/10844 , H01L21/768 , H01L21/76802 , H01L21/76804 , H01L21/76885 , H01L23/485 , H01L27/105 , H01L27/10808 , H01L27/10852 , H01L28/40 , H01L28/82 , H01L28/84 , H01L28/86 , H01L28/90 , H01L2924/0002
摘要： A semiconductor processing method of making electrical contact to a node received within a mass of insulating dielectric material includes, a) providing a node within a mass of insulating dielectric material; b) first stage etching into the insulating dielectric material over the node in a manner substantially selective relative to the node; c) after the first stage etching, second stage etching the dielectric material in a manner which increases a degree of sidewall polymerization over that occurring in the first stage etching and in a manner substantially selective relative to the node; and d) after the second stage etching, third stage etching the dielectric material with a degree of sidewall polymerization which is less than that of the second stage etching and in a manner substantially selective relative to the first node. An alternate method provides an etch stop annulus cap overlying an electrically conductive ring which projects from a primary insulating layer. A secondary insulating layer is then provided outwardly of the etch stop annulus cap. A second contact opening is patterned and etched through the second insulating layer relative to the first contact opening and to the etch stop annulus cap, with the second contact opening having a wider target area than would otherwise be provided if the annulus cap were not present. Aspects of the invention have significant utility in the fabrication of bit line over capacitor arrays of memory cells.
摘要翻译：对接收在绝缘介电材料块内的节点进行电接触的半导体处理方法包括：a）在绝缘介电材料块内提供节点; b）以相对于节点基本上选择性的方式在节点上第一级蚀刻到绝缘介电材料中; c）在第一阶段蚀刻之后，第二阶段以相对于该节点基本上选择性的方式，以增加与第一阶段蚀刻中发生的侧壁聚合程度相似的方式来蚀刻电介质材料; 以及d）在第二阶段蚀刻之后，第三阶段以比第二阶段蚀刻小的侧壁聚合程度以相对于第一节点基本选择的方式蚀刻电介质材料。替代方法提供覆盖从主绝缘层突出的导电环的蚀刻停止环形覆盖层。然后在蚀刻停止环形盖的外侧设置次级绝缘层。第二接触开口相对于第一接触开口和蚀刻停止环形盖通过第二绝缘层图案化并蚀刻，其中第二接触开口具有比否则将提供的环面帽不存在时更宽的目标面积。本发明的方面在存储器单元的电容器阵列上的位线的制造中具有显着的用途。

9. 发明授权

US5307357A Protection means for ridge waveguide laser structures using thick organic films 失效
标题翻译：使用厚的有机膜的脊波导激光器结构的保护手段
公开(公告)号：US5307357A
公开(公告)日：1994-04-26
申请号：US972041
申请日：1992-11-05
申请人： Mark E. Jost , Ranee W. Kwong , Abbas Behfar-Rad , Peter P. Kwan
发明人： Mark E. Jost , Ranee W. Kwong , Abbas Behfar-Rad , Peter P. Kwan
IPC分类号： H01S5/02 , H01S5/22 , H01S3/30
CPC分类号： H01S5/02 , H01S5/0282 , H01S5/22
摘要： What is disclosed is a semiconductor ridge waveguide laser structure having mechanical protection of ridge element by means of a thick, multi-layer organic material. The organic material, which may be a polyimide film, is deposited over the ridge element. The present invention also provides a fabrication process for depositing the protective means on the ridge element including deposition and photolithographic steps.
摘要翻译：公开的是具有通过厚的多层有机材料对脊元件进行机械保护的半导体脊形波导激光器结构。可以是聚酰亚胺膜的有机材料沉积在脊元件上。本发明还提供了一种用于在脊元件上沉积保护装置的制造方法，包括沉积和光刻步骤。

10. 发明授权

US06653241B2 Methods of forming protective segments of material, and etch stops 有权
公开(公告)号：US06653241B2
公开(公告)日：2003-11-25
申请号：US10098680
申请日：2002-03-12
申请人： Mark E. Jost , Keith Cook , Erik Byers
发明人： Mark E. Jost , Keith Cook , Erik Byers
IPC分类号： H01L21302
CPC分类号： H01L27/10855 , H01L21/31116 , H01L21/76895 , H01L21/76897 , H01L27/10888 , H01L28/90
摘要： The invention encompasses a method of forming a protective segment of material. A plurality of at least three conductive lines are provided over a semiconductor substrate. A material is formed over the conductive lines, and a patterned masking layer is formed to cover a segment of the material extending between a pair of the conductive lines while leaving another segment of the material uncovered. The uncovered segment of the material is anisotropically etched to form separated spacers from the uncovered segment. The separated spacers are along sidewalls of at least two of the conductive lines. The covered segment of the material remains after the anisotropic etching, and is a protective segment of the material over the semiconductor substrate.

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