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1. 发明授权

US06812139B2 Method for metal fill by treatment of mobility layers 失效
标题翻译：通过处理迁移率层的金属填充方法
公开(公告)号：US06812139B2
公开(公告)日：2004-11-02
申请号：US10280427
申请日：2002-10-25
申请人： John H. Givens , Russell C. Zahorik , Brenda D. Kraus
发明人： John H. Givens , Russell C. Zahorik , Brenda D. Kraus
IPC分类号： H01L214763
CPC分类号： H01L23/485 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A recess having a height-to-width aspect ratio from about 6:1 to about 10:1 in a semiconductor structure is taught with a method of forming the same. In a first embodiment, a refractory metal layer is formed in the recess, which can be a trench, a contact hole, or a combination thereof. A refractory metal nitride layer is then formed on the refractory metal layer. A heat treatment is used to form a metal silicide contact at the bottom of the contact hole upon a semiconductor material. In a first alternative method, an ammonia high-temperature treatment is conducted to remove undesirable impurities within the refractory metal nitride layer lining the contact hole and to replace the impurities with more nitrogen. In a second alternative method, a second refractory metal nitride layer is formed by PVD upon the first refractory metal nitride layer. In either alternative, a metallization layer is deposited within the recess. High pressure and temperature are used to substantially fill the recess with the metallization layer. Following the substantially filling of the recess, residual surface metallization may at least be partially removed by techniques such as etch back or CMP.
摘要翻译：通过形成半导体结构的方法，教导了半导体结构中的高度 - 宽度纵横比为约6:1至约10:1的凹槽。在第一实施例中，难熔金属层形成在凹槽中，其可以是沟槽，接触孔或其组合。然后在难熔金属层上形成难熔金属氮化物层。使用热处理在半导体材料上的接触孔的底部形成金属硅化物接触。在第一替代方法中，进行氨高温处理以除去在接触孔内衬的难熔金属氮化物层内的不期望的杂质，并用更多的氮替代杂质。在第二替代方法中，通过PVD在第一难熔金属氮化物层上形成第二难熔金属氮化物层。在任一替代方案中，在凹陷内沉积金属化层。高压和高温用于基本上用金属化层填充凹槽。在基本上填充凹部之后，残余表面金属化可以至少通过诸如回蚀刻或CMP之类的技术部分地去除。

2. 发明授权

US06482735B1 Method for improved metal fill by treatment of mobility layers 有权
标题翻译：通过处理迁移率层改善金属填充的方法
公开(公告)号：US06482735B1
公开(公告)日：2002-11-19
申请号：US09428159
申请日：1999-10-27
申请人： John H. Givens , Russell C. Zahorik , Brenda D. Kraus
发明人： John H. Givens , Russell C. Zahorik , Brenda D. Kraus
IPC分类号： H01L214763
CPC分类号： H01L23/485 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： A recess having a height-to-width aspect ratio from about 6:1 to about 10:1 in a semiconductor structure is taught with a method of forming the same. In a first embodiment, a refractory metal layer is formed in the recess, which can be a trench, a contact hole, or a combination thereof. A refractory metal nitride layer is then formed on the refractory metal layer. A heat treatment, preferably RTP, is used to form a metal silicide contact at the bottom of the contact hole upon semiconductor material. In a first alternative method, an ammonia high-temperature treatment is conducted to remove undesirable impurities within the refractory metal nitride layer lining the contact hole and to replace the impurities with more nitrogen. In a second alternative method, a second refractory metal nitride layer is formed by PVD upon the first refractory metal nitride layer. In either alternative, metallization layer is deposited with the recess. High pressure and temperature are used to substantially fill the recess with the metallization layer. In a preferred embodiment, deposition of the first refractory metal nitride layer is accomplished using trimethylethylenediamine tris (dimethylamino) titanium (TMEDT). The aspect ratio of a recess that can be substantially filled can exceed 8:1 when using a TMEDT-deposited refractory metal nitride layer and a subsequent deposition of a second refractory metal nitride layer by PVD. Following the substantially filling of the recess, residual surface metallization may be at least partially removed by such techniques as etch back or CMP.
摘要翻译：通过形成半导体结构的方法，教导了半导体结构中的高度 - 宽度纵横比为约6:1至约10:1的凹槽。在第一实施例中，难熔金属层形成在凹槽中，其可以是沟槽，接触孔或其组合。然后在难熔金属层上形成难熔金属氮化物层。在半导体材料上的接触孔的底部使用热处理（优选RTP）来形成金属硅化物接触。在第一替代方法中，进行氨高温处理以除去在接触孔内衬的难熔金属氮化物层内的不期望的杂质，并用更多的氮替代杂质。在第二替代方法中，通过PVD在第一难熔金属氮化物层上形成第二难熔金属氮化物层。在任一替代方案中，金属化层沉积有凹槽。高压和高温用于基本上用金属化层填充凹槽。在优选的实施方案中，使用三甲基乙二胺三（二甲基氨基）钛（TMEDT）完成第一难熔金属氮化物层的沉积。当使用TMEDT沉积的难熔金属氮化物层和随后通过PVD沉积第二难熔金属氮化物层时，可以基本上填充的凹槽的纵横比可以超过8:1。在基本上填充凹部之后，残余表面金属化可以通过诸如回蚀刻或CMP之类的技术至少部分地去除。

3. 发明授权

US06320261B1 High aspect ratio metallization structures for shallow junction devices, and methods of forming the same 失效
公开(公告)号：US06320261B1
公开(公告)日：2001-11-20
申请号：US09063516
申请日：1998-04-21
申请人： Randle D. Burton , John H. Givens
发明人： Randle D. Burton , John H. Givens
IPC分类号： H01L2348
CPC分类号： H01L27/10855 , H01L21/28518 , H01L21/2855 , H01L23/485 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： A contact interface having a substantially annular silicide ring along sides of a depression formed in an active surface of the semiconductor substrate, wherein the depression is formed by an etching process to form a contact opening through a dielectric layer. The contact interface is formed by depositing a layer of conductive material, such as titanium, with a high bias power IMP deposition. The conductive material is turned to a silicide by an annealing process, thereby forming the contact interface.

4. 发明授权

US06319813B1 Semiconductor processing methods of forming integrated circuitry and integrated circuitry constructions 失效
标题翻译：形成集成电路的半导体处理方法
公开(公告)号：US06319813B1
公开(公告)日：2001-11-20
申请号：US09111359
申请日：1998-07-06
申请人： John H. Givens
发明人： John H. Givens
IPC分类号： H01L214763
CPC分类号： H01L21/76807 , H01L23/485 , H01L2221/1036
摘要： Semiconductor processing methods of forming integrated circuitry, and in particular, methods of forming such circuitry utilizing dual damascene technology, and resultant integrated circuitry constructions are described. In one embodiment, a substrate is provided having a circuit device. At least three layers are formed over the substrate and through which electrical connection is to be made with the circuit device. The three layers comprise first and second layers having an etch stop layer interposed therebetween. A contact opening is formed through the three layers and a patterned masking layer is formed over the three layers to define a conductive line pattern. Material of an uppermost of the first and second layers is selectively removed relative to the etch stop layer and defines a trough joined with the contact opening. Conductive material is subsequently formed within the trough and contact opening. In another embodiment, a contact opening is formed through a plurality of layers and has an aspect ratio of no less than about 10:1. A trench is defined in an uppermost layer of the plurality of layers proximate the contact opening. Conductive material is formed within the contact opening and at least a portion of the trench, with the conductive material being in electrical communication.
摘要翻译：描述了形成集成电路的半导体处理方法，特别是利用双镶嵌技术形成这种电路的方法以及所得到的集成电路结构。在一个实施例中，提供具有电路装置的基板。在衬底上形成至少三个层，并且通过该层与电路器件进行电连接。三层包括其间插入有蚀刻停止层的第一层和第二层。通过三层形成接触开口，并且在三层上形成图案化掩模层以限定导电线图案。相对于蚀刻停止层选择性地去除第一和第二层的最上层的材料，并且限定与接触开口接合的槽。随后在槽和接触开口内形成导电材料。在另一个实施例中，接触开口形成为穿过多个层并具有不小于约10:1的纵横比。在靠近接触开口的多个层的最上层中限定沟槽。导电材料形成在接触开口内以及沟槽的至少一部分，其中导电材料是电连通的。

5. 发明授权

US06316360B1 High aspect ratio metallization structures for shallow junction devices, and methods of forming the same 失效
标题翻译：浅接头器件的高纵横比金属化结构及其形成方法
公开(公告)号：US06316360B1
公开(公告)日：2001-11-13
申请号：US09150445
申请日：1998-09-09
申请人： Randle D. Burton , John H. Givens
发明人： Randle D. Burton , John H. Givens
IPC分类号： H01L2144
CPC分类号： H01L27/10855 , H01L21/28518 , H01L21/2855 , H01L23/485 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： A contact interface having a substantially annular silicide ring along sides of a depression formed in an active surface of the semiconductor substrate, wherein the depression is formed by an etching process to form a contact opening through a dielectric layer. The contact interface is formed by depositing a layer of conductive material, such as titanium, with a high bias power IMP deposition. The conductive material is turned to a silicide by an annealing process, thereby forming the contact interface.
摘要翻译：一种接触界面，其具有沿着形成在所述半导体衬底的有源表面中的凹部的侧面的基本环形的硅化物环，其中所述凹陷通过蚀刻工艺形成以形成通过介电层的接触开口。接触界面通过以高偏压功率IMP沉积沉积诸如钛的导电材料层而形成。导电材料通过退火工艺转变成硅化物，从而形成接触界面。

6. 发明授权

US06271593B1 Method for fabricating conductive components in microelectronic devices and substrate structures therefor 有权
标题翻译：在微电子器件及其衬底结构中制造导电元件的方法
公开(公告)号：US06271593B1
公开(公告)日：2001-08-07
申请号：US09385130
申请日：1999-08-27
申请人： John H. Givens , Richard H. Lane
发明人： John H. Givens , Richard H. Lane
IPC分类号： H01L23485
CPC分类号： H01L21/76807 , H01L21/76838
摘要： A method and substrate structure for fabricating highly conductive components on microelectronic devices. In one embodiment in accordance with the principles of the present invention, a first dielectric layer is formed over a base layer of a substrate, a second dielectric layer is deposited onto the first dielectric layer, and a third dielectric layer is deposited onto the second dielectric layer. The first, second and third dielectric layers define a dielectric stratum in which the first and second dielectric layers may be selectively etchable from one another so that the second dielectric layer etches at a faster rate than the first layer in the presence of a selective etchant. After the dielectric layers are deposited onto the substrate, a void is etched through the second and third dielectric layers. The void may be etched in a two part process in which a non-selective etchant etches through the third dielectric layer to an intermediate level in the second dielectric layer, and then a selective etchant etches through the remaining portion of the second dielectric layer to the first dielectric layer. The third dielectric layer is subsequently covered with a conductive material, and the void is filled with a portion of the conductive layer. The substrate is then planarized to the third layer to form a conductive component in the void. The third dielectric layer generally has a lower polishing rate than the conductive layer so that the third dielectric layer acts as a polish-stop layer for the planarizing process. Although the method is applicable to forming virtually any type of conductive component on a substrate, it is particularly useful for forming gold components in contact holes and/or trenches.
摘要翻译：一种用于在微电子器件上制造高导电元件的方法和衬底结构。在根据本发明的原理的一个实施例中，在衬底的基底层上形成第一电介质层，第二电介质层沉积到第一电介质层上，并且第三电介质层沉积到第二电介质上层。第一，第二和第三电介质层限定电介质层，其中第一和第二电介质层可以彼此可选择性地蚀刻，使得第二电介质层在存在选择性蚀刻剂的情况下以比第一层更快的速率蚀刻。在将电介质层沉积到衬底上之后，通过第二和第三电介质层蚀刻空隙。可以在两部分工艺中蚀刻空隙，其中非选择性蚀刻剂通过第三介电层蚀刻到第二介电层中的中间水平，然后选择性蚀刻剂通过第二介电层的剩余部分蚀刻到第一电介质层。随后用导电材料覆盖第三电介质层，并且该空隙用导电层的一部分填充。然后将衬底平坦化到第三层，以在空隙中形成导电组分。第三电介质层通常具有比导电层更低的抛光速率，使得第三介电层用作平坦化工艺的抛光停止层。尽管该方法适用于在基片上形成几乎任何类型的导电组分，但其特别可用于在接触孔和/或沟槽中形成金成分。

7. 发明授权

US06267852B1 Method of forming a sputtering apparatus 有权
标题翻译：形成溅射装置的方法
公开(公告)号：US06267852B1
公开(公告)日：2001-07-31
申请号：US09535764
申请日：2000-03-28
申请人： John H. Givens , Shane B. Leiphart
发明人： John H. Givens , Shane B. Leiphart
IPC分类号： C23C1434
CPC分类号： C23C14/345 , C23C14/34 , C23C14/564 , H01J37/32862 , H01J37/34 , H01J37/3447
摘要： Disclosed is a method of forming a PVD deposition chamber which is modified with an electrical circuit that allows a voltage bias to be applied to any one or more of a target, an in-process integrated circuit wafer, and collimator. The collimator can also be isolated from the electrical circuit. This configuration allows a preclean of the in-process integrated circuit wafer in situ in the PVD deposition chamber by ion sputtering and a subsequent sputter deposition through the collimator. A method is also disclosed wherein an in-process integrated circuit wafer is first precleaned in the PVD deposition chamber by applying a negative voltage bias to the in-process integrated circuit wafer. A film of conducting material is then sputter deposited on the surface of the in-process integrated circuit wafer by applying a negative voltage bias to the target. The collimator is electrically isolated during this process or is set at a higher potential than the in-process integrated circuit wafer. A voltage bias can also be applied to the in-process integrated circuit wafer during the deposition, and its magnitude proportioned to modify the morphology of the film being deposited. Once the deposition is conducted, a negative voltage bias can be applied to the collimator to sputter clean the collimator.
摘要翻译：公开了一种形成PVD沉积室的方法，其被电路修改，该电路允许将电压偏压施加到靶，过程中集成电路晶片和准直器中的任何一个或多个。准直器也可以与电路隔离。该配置允许通过离子溅射在PVD沉积室中原位处理过程中集成电路晶片，并通过准直器进行随后的溅射沉积。还公开了一种在工艺中集成电路晶片首先在 PVD沉积室，通过对过程中集成电路晶片施加负电压偏压。然后通过向目标施加负电压偏压将导电材料膜溅射沉积在过程集成电路晶片的表面上。在该过程期间，准直器被电隔离或被设置在比过程中集成电路晶片更高的电位。在沉积期间也可以将电压偏压施加到过程中集成电路晶片，并且其大小成比例以改变被沉积的膜的形态。一旦进行沉积，可以对准直器施加负电压偏压以溅射清洁准直器。

8. 发明授权

US6114232A Method for making an electrical contact to a node location and process for forming a conductive line or other circuit component 失效
标题翻译：用于与节点位置进行电接触的方法以及用于形成导线或其它电路部件的工艺
公开(公告)号：US6114232A
公开(公告)日：2000-09-05
申请号：US187294
申请日：1998-11-05
申请人： John H. Givens
发明人： John H. Givens
IPC分类号： H01L21/027 , H01L21/285 , H01L21/311 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/31111 , H01L21/0274 , H01L21/28512 , H01L21/76807 , H01L2221/1026 , H01L2221/1036
摘要： An electrical contact and method for making an electrical contact to a node location is disclosed and which includes forming a substrate having a node location to which electrical connection is to be made; forming a first patterned layer of a photosensitive material over the node location; forming a first dielectric layer over the first patterned layer of photosensitive material; planarizing the first dielectric layer to expose at least a portion of the first patterned layer of photosensitive material; forming a second patterned layer of a photosensitive material over the exposed first patterned layer of photosensitive material and the first dielectric layer; forming a second dielectric layer over the second patterned layer of photosensitive material; planarizing the second dielectric layer to expose at least a portion of the second patterned layer of photosensitive material; after planarizing the second dielectric layer, removing the first and second patterned layers of photosensitive material, the removal of the first and second layers of photosensitive material forming a void to the underlying node locations; and filling the void with electrically conductive material to make electrical contact to the node location.
摘要翻译：公开了一种用于与节点位置进行电接触的电触点和方法，其包括形成具有要与其进行电连接的节点位置的基板; 在所述节点位置上形成感光材料的第一图案化层; 在感光材料的第一图案化层上形成第一介电层; 平面化第一介电层以暴露感光材料的第一图案化层的至少一部分; 在感光材料的暴露的第一图案化层和第一介电层上形成感光材料的第二图案化层; 在感光材料的第二图案化层上形成第二电介质层; 平面化第二介电层以暴露感光材料的第二图案化层的至少一部分; 在平坦化第二介电层之后，去除感光材料的第一和第二图案化层，去除形成空隙的第一和第二层感光材料到下面的节点位置; 并用导电材料填充空隙以使电接触到节点位置。

9. 发明授权

US6080653A Method for making an electrical contact to a node location and process for forming a conductive line or other circuit component 失效
公开(公告)号：US6080653A
公开(公告)日：2000-06-27
申请号：US257880
申请日：1999-02-25
申请人： John H. Givens
发明人： John H. Givens
IPC分类号： H01L21/027 , H01L21/285 , H01L21/311 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/31111 , H01L21/0274 , H01L21/28512 , H01L21/76807 , H01L2221/1026 , H01L2221/1036
摘要： An electrical contact and method for making an electrical contact to a node location is disclosed and which includes forming a substrate having a node location to which electrical connection is to be made; forming a first patterned layer of a photosensitive material over the node location; forming a first dielectric layer over the first patterned layer of photosensitive material; planarizing the first dielectric layer to expose at least a portion of the first patterned layer of photosensitive material; forming a second patterned layer of a photosensitive material over the exposed first patterned layer of photosensitive material and the first dielectric layer; forming a second dielectric layer over the second patterned layer of photosensitive material; planarizing the second dielectric layer to expose at least a portion of the second patterned layer of photosensitive material; after planarizing the second dielectric layer, removing the first and second patterned layers of photosensitive material, the removal of the first and second layers of photosensitive material forming a void to the underlying node locations; and filling the void with electrically conductive material to make electrical contact to the node location.

10. 发明授权

US5980657A Alloy for enhanced filling of high aspect ratio dual damascene structures 失效
标题翻译：用于增强高纵横比双镶嵌结构的填充材料
公开(公告)号：US5980657A
公开(公告)日：1999-11-09
申请号：US37935
申请日：1998-03-10
申请人： Paul A. Farrar , John H. Givens
发明人： Paul A. Farrar , John H. Givens
IPC分类号： C22C21/14 , H01L23/532 , H01L23/535 , C22C21/12
CPC分类号： H01L23/53219 , C22C21/14 , H01L23/535 , H01L2924/0002
摘要： An integrated circuit alloy is described which reduces the alloy melting temperature for improved coverage of high aspect ratio features with a reduced deposition pressure. The alloy is used to fabricate metal contacts and interconnects in integrated circuits, such as memory devices. The contacts and interconnects can be high aspect ratio features formed using a dual damascene process. An aluminum interconnect alloy is described for use in an integrated circuit which includes Al, Cu, Si. Ge and Mg can also be provided in the alloy. The composition of Si+Ge+Mg provides a melting temperature of the aluminum interconnect alloy which is between 500 and 550.degree. C.
摘要翻译：描述了一种集成电路合金，其降低了合金熔化温度，以便降低沉积压力来改善高纵横比特征的覆盖。该合金用于在诸如存储器件的集成电路中制造金属触点和互连。触点和互连可以是使用双镶嵌工艺形成的高纵横比特征。描述了用于包括Al，Cu，Si的集成电路中的铝互连合金。也可以在合金中提供Ge和Mg。 Si + Ge + Mg的组成提供了在500和550℃之间的铝互连合金的熔化温度。

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