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1. 发明授权

US08126045B2 System and method for latency reduction in speculative decision feedback equalizers 有权
标题翻译：投机决策反馈均衡器延迟降低的系统和方法
公开(公告)号：US08126045B2
公开(公告)日：2012-02-28
申请号：US12201487
申请日：2008-08-29
申请人： John Francis Bulzacchelli , Gautam Gangasani , Mounir Meghelli , Sergey V. Rylov , Michael A. Sorna , Steven J. Zier
发明人： John Francis Bulzacchelli , Gautam Gangasani , Mounir Meghelli , Sergey V. Rylov , Michael A. Sorna , Steven J. Zier
IPC分类号： H03H7/40
CPC分类号： H04L25/03057 , H04L2025/0349 , H04L2025/03617
摘要： A decision feedback equalizer (DFE) and method include summer circuits configured to add a dynamic feedback tap to a received input to provide a sum and to add a speculative static tap to the sum. Sense amplifiers are configured to receive outputs of the summer circuits and evaluate the outputs of the summer circuits in accordance with a clock signal. A passgate multiplexer is configured to receive outputs from sense amplifiers wherein the multiplexers is clock-gated for isolation of subsequent ciruitry from the outputs of the sense amplifiers during a precharged period. A gating circuit is configured to perform gating of a selected signal output from a second circuit portion with a clock signal and to enable the isolation of the subsequent circuitry by the multiplexer during the precharge period. A regenerative buffer is coupled to the multiplexer to maintain an output of the multiplexer during the precharge period, to provide the select signal for a passgate multiplexer in the second circuit portion of the DFE and to drive the dynamic feedback tap on the first circuit portion of the DFE.
摘要翻译：决策反馈均衡器（DFE）和方法包括配置为向所接收的输入添加动态反馈抽头以提供和并且为该和添加推测静态抽头的加法电路。检测放大器被配置为接收加法电路的输出并根据时钟信号来估计加法电路的输出。通道门复用器被配置为接收来自读出放大器的输出，其中多路复用器是时钟门控的，用于在预充电时段期间从读出放大器的输出隔离后续电路。选通电路被配置为利用时钟信号来执行从第二电路部分输出的选定信号的门控，并且能够在预充电期间使多路复用器能够隔离后续电路。再生缓冲器耦合到多路复用器以在预充电周期期间保持多路复用器的输出，以便为DFE的第二电路部分中的通道门多路复用器提供选择信号，并且在DFE的第一电路部分上驱动动态反馈抽头 DFE。

2. 发明申请

US20100054324A1 SYSTEM AND METHOD FOR LATENCY REDUCTION IN SPECULATIVE DECISION FEEDBACK EQUALIZERS 有权
标题翻译：在决策反馈均衡器中减少衰减的系统和方法
公开(公告)号：US20100054324A1
公开(公告)日：2010-03-04
申请号：US12201487
申请日：2008-08-29
申请人： John Francis Bulzacchelli , Gautam Gangasani , Mounir Meghelli , Sergey V. Rylov , Michael A. Sorna , Steven J. Zier
发明人： John Francis Bulzacchelli , Gautam Gangasani , Mounir Meghelli , Sergey V. Rylov , Michael A. Sorna , Steven J. Zier
IPC分类号： H03H7/40
CPC分类号： H04L25/03057 , H04L2025/0349 , H04L2025/03617
摘要： A decision feedback equalizer (DFE) and method include summer circuits configured to add a dynamic feedback tap to a received input to provide a sum and to add a speculative static tap to the sum. Sense amplifiers are configured to receive outputs of the summer circuits and evaluate the outputs of the summer circuits in accordance with a clock signal. A passgate multiplexer is configured to receive outputs from sense amplifiers wherein the multiplexer is clock-gated for isolation of subsequent circuitry from the outputs of the sense amplifiers during a precharge period. A gating circuit is configured to perform gating of a select signal output from a second circuit portion with a clock signal and to enable the isolation of the subsequent circuitry by the multiplexer during the precharge period. A regenerative buffer is coupled to the multiplexer to maintain an output of the multiplexer during the precharge period, to provide the select signal for a passgate multiplexer in the second circuit portion of the DFE and to drive the dynamic feedback tap on the first circuit portion of the DFE.
摘要翻译：决策反馈均衡器（DFE）和方法包括配置为向所接收的输入添加动态反馈抽头以提供和并且为该和添加推测静态抽头的加法电路。检测放大器被配置为接收加法电路的输出并根据时钟信号来估计加法电路的输出。门控多路复用器被配置为接收来自读出放大器的输出，其中多路复用器是时钟选通的，用于在预充电期间将后续电路与读出放大器的输出隔离。选通电路被配置为利用时钟信号来执行从第二电路部分输出的选择信号的门控，并且能够在预充电期间使多路复用器能够隔离后续电路。再生缓冲器耦合到多路复用器以在预充电周期期间保持多路复用器的输出，以便为DFE的第二电路部分中的通道门多路复用器提供选择信号，并且在DFE的第一电路部分上驱动动态反馈抽头 DFE。

3. 发明申请

US20080061825A1 CML TO CMOS SIGNAL CONVERTER 失效
标题翻译： CML TO CMOS信号转换器
公开(公告)号：US20080061825A1
公开(公告)日：2008-03-13
申请号：US11467349
申请日：2006-08-25
申请人： Louis L. Hsu , Gautam Gangasani , Michael A. Sorna , Steven J. Zier
发明人： Louis L. Hsu , Gautam Gangasani , Michael A. Sorna , Steven J. Zier
IPC分类号： H03K19/094
CPC分类号： H03K19/018528
摘要： A signal regenerator is provided which includes a common mode reference generator and a signal converter circuit. A common mode reference voltage level is generated which is variable in relation to at least one of a process used to fabricate the common mode reference generator, a level of a power supply voltage provided to the common mode reference generator or a temperature at which the common mode reference generator is operated. A signal converter circuit receives a differentially transmitted signal pair including a first input signal and a second input signal and outputs a single-ended output signal representing information carried by the differentially transmitted signal pair. Using a feedback signal from the common mode reference generator, a feedback control block controls a common mode level of the single-ended output signal in accordance with the common mode reference voltage level.
摘要翻译：提供信号再生器，其包括共模参考发生器和信号转换器电路。产生共模参考电压电平，其相对于用于制造共模参考发生器的工艺中的至少一个，提供给共模参考发生器的电源电压的电平或共模参考电压的温度可变模式参考发生器运行。信号转换器电路接收包括第一输入信号和第二输入信号的差分发送信号对，并输出表示由差分发送信号对承载的信息的单端输出信号。使用来自共模参考发生器的反馈信号，反馈控制块根据共模参考电压电平控制单端输出信号的共模电平。

4. 发明授权

US07394283B2 CML to CMOS signal converter 失效
标题翻译： CML到CMOS信号转换器
公开(公告)号：US07394283B2
公开(公告)日：2008-07-01
申请号：US11467349
申请日：2006-08-25
申请人： Louis L. Hsu , Gautam Gangasani , Michael A. Sorna , Steven J. Zier
发明人： Louis L. Hsu , Gautam Gangasani , Michael A. Sorna , Steven J. Zier
IPC分类号： H03K17/16
CPC分类号： H03K19/018528
摘要： A signal regenerator is provided which includes a common mode reference generator and a signal converter circuit. A common mode reference voltage level is generated which is variable in relation to at least one of a process used to fabricate the common mode reference generator, a level of a power supply voltage provided to the common mode reference generator or a temperature at which the common mode reference generator is operated. A signal converter circuit receives a differentially transmitted signal pair including a first input signal and a second input signal and outputs a single-ended output signal representing information carried by the differentially transmitted signal pair. Using a feedback signal from the common mode reference generator, a feedback control block controls a common mode level of the single-ended output signal in accordance with the common mode reference voltage level.
摘要翻译：提供信号再生器，其包括共模参考发生器和信号转换器电路。产生共模参考电压电平，其相对于用于制造共模参考发生器的工艺中的至少一个，提供给共模参考发生器的电源电压的电平或共模参考电压的温度可变模式参考发生器运行。信号转换器电路接收包括第一输入信号和第二输入信号的差分发送信号对，并输出表示由差分发送信号对承载的信息的单端输出信号。使用来自共模参考发生器的反馈信号，反馈控制块根据共模参考电压电平控制单端输出信号的共模电平。

5. 发明授权

US07409019B2 High Speed Multi-Mode Receiver with adaptive receiver equalization and controllable transmitter pre-distortion 有权
标题翻译：具有自适应接收机均衡和可控发射机预失真的高速多模式接收机
公开(公告)号：US07409019B2
公开(公告)日：2008-08-05
申请号：US10711713
申请日：2004-09-30
申请人： Louis C. Hsu , Brian L. Ji , James S. Mason , Karl D. Selander , Michael A. Sorna , Steven J. Zier
发明人： Louis C. Hsu , Brian L. Ji , James S. Mason , Karl D. Selander , Michael A. Sorna , Steven J. Zier
IPC分类号： H04L27/08
CPC分类号： H04L25/085 , H03F1/3241 , H04L25/0278 , H04L25/0292 , H04L25/03343 , H04L25/061 , H04L2025/0349 , H04L2025/03566 , H04L2025/03617 , H04L2025/03808
摘要： A data receiver is provided which is operable to receive a signal controllably pre-distorted and transmitted by a transmitter, to generate information for adjusting the pre-distortion applied to the signal transmitted by the transmitter, and to transmit the information to the transmitter. The receiver is further operable to perform adaptive equalization to receive the signal transmitted by the transmitter.
摘要翻译：提供了一种数据接收器，其可操作以接收由发射机可控地预失真和发送的信号，以产生用于调整应用于由发射机发送的信号的预失真的信息，并将该信息发送到发射机。接收机还可操作以执行自适应均衡以接收由发射机发送的信号。

6. 发明授权

US07486114B2 Signal detector with calibration circuit arrangement 有权
标题翻译：具有校准电路布置的信号检测器
公开(公告)号：US07486114B2
公开(公告)日：2009-02-03
申请号：US11383821
申请日：2006-05-17
申请人： Minhan Chen , Louis Hsu , Joseph Natonio , Karl D. Selander , Michael A. Sorna , Steven J. Zier
发明人： Minhan Chen , Louis Hsu , Joseph Natonio , Karl D. Selander , Michael A. Sorna , Steven J. Zier
IPC分类号： H03K5/19
CPC分类号： H04L25/0274 , H04L25/0296
摘要： A signal detector and method to detect the presence or absence of an incoming differential signal. The method nullifies the DC off-set of the signal detector so that it can detect a signal within a very narrow window. The common mode levels of the signal and reference paths are used for calibration which is done automatically by use of an embedded algorithm residing in a digital block. The calibration range and resolution are predetermined to cope with the technology, modeling, design methodology and human error.
摘要翻译：一种用于检测输入差分信号的存在或不存在的信号检测器和方法。该方法使信号检测器的DC偏移无效，使得其可以在非常窄的窗口内检测信号。信号和参考路径的共模电平用于通过使用位于数字块中的嵌入式算法自动完成的校准。预定校准范围和分辨率，以应对技术，建模，设计方法和人为错误。

7. 发明申请

US20070271054A1 Signal Detector with Calibration Circuit Arrangement 有权
标题翻译：具有校准电路布置的信号检测器
公开(公告)号：US20070271054A1
公开(公告)日：2007-11-22
申请号：US11383821
申请日：2006-05-17
申请人： Minhan Chen , Louis Hsu , Joseph Natonio , Karl D. Selander , Michael A. Sorna , Steven J. Zier
发明人： Minhan Chen , Louis Hsu , Joseph Natonio , Karl D. Selander , Michael A. Sorna , Steven J. Zier
IPC分类号： G06F19/00
CPC分类号： H04L25/0274 , H04L25/0296
摘要： A signal detector and method detect the presence or absence of an incoming differential signal. The method nullifies the DC off-set of the signal detector so that it can detect a signal within a very narrow window. The common mode levels of the signal and reference paths are used for calibration which is done automatically by use of an embedded algorithm residing in a digital block. The calibration range and resolution are predetermined to cope with the technology, modeling, design methodology and human error.
摘要翻译：信号检测器和方法检测输入差分信号的存在或不存在。该方法使信号检测器的DC偏移无效，使得其可以在非常窄的窗口内检测信号。信号和参考路径的共模电平用于通过使用位于数字块中的嵌入式算法自动完成的校准。预定校准范围和分辨率，以应对技术，建模，设计方法和人为错误。

8. 发明授权

US06937054B2 Programmable peaking receiver and method 有权
标题翻译：可编程峰值接收机和方法
公开(公告)号：US06937054B2
公开(公告)日：2005-08-30
申请号：US10250043
申请日：2003-05-30
申请人： Louis L. Hsu , Karl D. Selander , Michael A. Sorna , William F. Washburn , Huihao H. Xu , Steven J. Zier
发明人： Louis L. Hsu , Karl D. Selander , Michael A. Sorna , William F. Washburn , Huihao H. Xu , Steven J. Zier
IPC分类号： H04L25/02 , H03K19/003
CPC分类号： H04L25/0272 , H04L25/0278 , H04L25/0294 , H04L25/03885
摘要： Methods and structures are disclosed herein for programmably adjusting a peaking function of a differential signal receiver. The disclosed method includes inputting a pair of differential signals to a pair of input transistors coupled to conduct currents differentially between a pair of load impedances and a pair of tail transistors. The impedance of an adjustable shunt impedance element between the tail transistors of the receiver is varied by programming signal input, such that higher current is conducted over a peaking range of frequencies. In a disclosed structural embodiment, an integrated circuit is provided having a programmable peaking receiver. The programmable peaking receiver includes a pair of input transistors coupled to conduct differentially according to a pair of differential inputs applied to the pair of input transistors. Each of the input transistors produces an output in accordance with the differential input applied thereto. The programmable peaking receiver also includes a pair of tail transistors, coupled to draw current from the input transistors, and a programmably adjustable impedance element coupled between current-conducting nodes of the tail transistors. The impedance of the programmably adjustable impedance element is thereby adjustable in response to programming signal input to adjust a peaking function of the programmable peaking receiver.
摘要翻译：本文公开了可编程地调节差分信号接收器的峰值功能的方法和结构。所公开的方法包括将一对差分信号输入到耦合以在一对负载阻抗和一对尾部晶体管之间差分地传导电流的一对输入晶体管。接收器的尾部晶体管之间的可调节分流阻抗元件的阻抗由编程信号输入变化，使得在峰值范围的频率上进行更高的电流。在公开的结构实施例中，提供了具有可编程峰值接收器的集成电路。可编程峰值接收器包括一对输入晶体管，其被耦合以根据施加到该对输入晶体管的一对差分输入进行差分导通。每个输入晶体管根据施加到其上的差分输入产生输出。可编程峰值接收器还包括耦合以从输入晶体管抽取电流的一对尾部晶体管，以及耦合在尾部晶体管的导电节点之间的可编程可调阻抗元件。可编程可调阻抗元件的阻抗因此可响应于编程信号输入而调节，以调节可编程峰值接收器的峰值功能。

9. 发明授权

US08410835B1 Leakage tolerant phase locked loop circuit device 有权
标题翻译：泄漏容限锁相环电路器件
公开(公告)号：US08410835B1
公开(公告)日：2013-04-02
申请号：US13342453
申请日：2012-01-03
申请人： Michael A. Sorna , Pradeep Thiagarajan
发明人： Michael A. Sorna , Pradeep Thiagarajan
IPC分类号： H03L7/06
CPC分类号： H03L7/101 , H03L7/0891 , H03L7/093
摘要： Leakage tolerant phase locked loop (PLL) circuit devices and methods of locking phases of output phase signals to a phase of a reference signal using a leakage tolerant PLL circuit device are provided. Embodiments include a PLL circuit device comprising: a primary loop and a secondary correction circuit. The primary loop includes a phase detector, an error controller, a voltage controlled oscillator (VCO), and feedback divider. The secondary correction circuit is configured to generate and provide a secondary error-frequency signal to the error controller. The secondary correction circuit is configured to generate the secondary error-frequency signal in response to detecting a particular edge of a divided VCO output signal. The primary loop is configured to control a frequency adjustment based on at least one of a first error-frequency-increase signal, a first error-frequency-decrease signal, and the secondary error-frequency signal.
摘要翻译：提供了泄漏容限锁相环（PLL）电路装置以及使用泄漏容限PLL电路装置将输出相位信号的相位锁定到参考信号的相位的方法。实施例包括PLL电路装置，其包括：主回路和二次校正电路。主回路包括相位检测器，误差控制器，压控振荡器（VCO）和反馈分压器。二次校正电路被配置为产生并向误差控制器提供次级错误频率信号。二次校正电路被配置为响应于检测到分压的VCO输出信号的特定边缘而产生次级错误频率信号。主回路被配置为基于第一误差频率增大信号，第一误差 - 频率降低信号和次级错误频率信号中的至少一个来控制频率调整。

10. 发明授权

US08040813B2 Apparatus and method for reduced loading of signal transmission elements 有权
标题翻译：信号传输元件负载减小的装置和方法
公开(公告)号：US08040813B2
公开(公告)日：2011-10-18
申请号：US10908959
申请日：2005-06-02
申请人： Louis L. Hsu , Karl D. Selander , Michael A. Sorna , Daniel W. Storaska
发明人： Louis L. Hsu , Karl D. Selander , Michael A. Sorna , Daniel W. Storaska
IPC分类号： G01R31/08 , G06F11/00 , G08C15/00 , H04J1/16 , H04J3/14 , H04L1/00 , H04L12/26 , H03K17/16 , G05F1/00 , H03K5/01 , H03K9/00 , H03K5/00 , H03K19/0175 , G01N30/86
CPC分类号： G06F13/4072
摘要： An apparatus is provided which includes a common signal node operable to conduct a first signal, a first circuit coupled to the common signal node to utilize the first signal and a signal-handling element coupled to the common signal node. The signal-handling element includes an isolating circuit coupled to the first conductor, a second conductor operable to conduct an output of the isolating circuit, and a signal-handling circuit coupled to the second conductor. The signal-handling circuit is operable to perform a signal-handling function in response to the output of the isolating circuit. By virtue of the isolating circuit, the signal-handling circuit and the first circuit are isolated from the second conductor and the signal-handling circuit. Preferably, the achieved isolation permits a communication signal included in the first signal to be conducted within a communication apparatus with less capacitance, and producing less return loss of that signal.
摘要翻译：提供一种装置，其包括可操作以传导第一信号的公共信号节点，耦合到公共信号节点以利用第一信号的第一电路和耦合到公共信号节点的信号处理元件。信号处理元件包括耦合到第一导体的隔离电路，可操作以导通隔离电路的输出的第二导体和耦合到第二导体的信号处理电路。信号处理电路可操作以响应于隔离电路的输出执行信号处理功能。通过隔离电路，信号处理电路和第一电路与第二导体和信号处理电路隔离。优选地，所实现的隔离允许包含在第一信号中的通信信号在具有较小电容的通信设备内传导，并且产生较小的该信号的回波损耗。

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