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1. 发明授权

US07456835B2 Register based queuing for texture requests 有权
标题翻译：基于注册排队的纹理请求
公开(公告)号：US07456835B2
公开(公告)日：2008-11-25
申请号：US11339937
申请日：2006-01-25
申请人： John Erik Lindholm , John R. Nickolls , Simon S. Moy , Brett W. Coon
发明人： John Erik Lindholm , John R. Nickolls , Simon S. Moy , Brett W. Coon
IPC分类号： G06T11/40 , G06T15/00 , G06T1/00 , G09G5/00
CPC分类号： G06T11/60 , G09G5/363
摘要： A graphics processing unit can queue a large number of texture requests to balance out the variability of texture requests without the need for a large texture request buffer. A dedicated texture request buffer queues the relatively small texture commands and parameters. Additionally, for each queued texture command, an associated set of texture arguments, which are typically much larger than the texture command, are stored in a general purpose register. The texture unit retrieves texture commands from the texture request buffer and then fetches the associated texture arguments from the appropriate general purpose register. The texture arguments may be stored in the general purpose register designated as the destination of the final texture value computed by the texture unit. Because the destination register must be allocated for the final texture value as texture commands are queued, storing the texture arguments in this register does not consume any additional registers.
摘要翻译：图形处理单元可以排队大量纹理请求，以平衡纹理请求的可变性，而不需要大的纹理请求缓冲区。专用纹理请求缓冲区排队相对较小的纹理命令和参数。另外，对于每个排队的纹理命令，通常比纹理命令大得多的一组相关的纹理参数存储在通用寄存器中。纹理单元从纹理请求缓冲区中检索纹理命令，然后从相应的通用寄存器获取相关的纹理参数。纹理参数可以存储在指定为由纹理单元计算的最终纹理值的目的地的通用寄存器中。因为当纹理命令排队时，必须为目标寄存器分配最终纹理值，所以将纹理参数存储在该寄存器中不消耗任何其他寄存器。

2. 发明授权

US07864185B1 Register based queuing for texture requests 有权
标题翻译：基于注册排队的纹理请求
公开(公告)号：US07864185B1
公开(公告)日：2011-01-04
申请号：US12256848
申请日：2008-10-23
申请人： John Erik Lindholm , John R. Nickolls , Simon S. Moy , Brett W. Coon
发明人： John Erik Lindholm , John R. Nickolls , Simon S. Moy , Brett W. Coon
IPC分类号： G06T11/40 , G06T15/00 , G06T15/20 , G06T1/00
CPC分类号： G06T11/60 , G09G5/363
摘要： A graphics processing unit can queue a large number of texture requests to balance out the variability of texture requests without the need for a large texture request buffer. A dedicated texture request buffer queues the relatively small texture commands and parameters. Additionally, for each queued texture command, an associated set of texture arguments, which are typically much larger than the texture command, are stored in a general purpose register. The texture unit retrieves texture commands from the texture request buffer and then fetches the associated texture arguments from the appropriate general purpose register. The texture arguments may be stored in the general purpose register designated as the destination of the final texture value computed by the texture unit. Because the destination register must be allocated for the final texture value as texture commands are queued, storing the texture arguments in this register does not consume any additional registers.
摘要翻译：图形处理单元可以排队大量纹理请求，以平衡纹理请求的可变性，而不需要大的纹理请求缓冲区。专用纹理请求缓冲区排队相对较小的纹理命令和参数。另外，对于每个排队的纹理命令，通常比纹理命令大得多的一组相关的纹理参数存储在通用寄存器中。纹理单元从纹理请求缓冲区中检索纹理命令，然后从相应的通用寄存器获取相关的纹理参数。纹理参数可以存储在指定为由纹理单元计算的最终纹理值的目的地的通用寄存器中。因为当纹理命令排队时，必须为目标寄存器分配最终纹理值，所以将纹理参数存储在该寄存器中不消耗任何其他寄存器。

3. 发明授权

US07027062B2 Register based queuing for texture requests 有权
公开(公告)号：US07027062B2
公开(公告)日：2006-04-11
申请号：US10789735
申请日：2004-02-27
申请人： John Erik Lindholm , John R. Nickolls , Simon S. Moy , Brett W. Coon
发明人： John Erik Lindholm , John R. Nickolls , Simon S. Moy , Brett W. Coon
IPC分类号： G06T11/40
CPC分类号： G06T11/60 , G09G5/363
摘要： A graphics processing unit can queue a large number of texture requests to balance out the variability of texture requests without the need for a large texture request buffer. A dedicated texture request buffer queues the relatively small texture commands and parameters. Additionally, for each queued texture command, an associated set of texture arguments, which are typically much larger than the texture command, are stored in a general purpose register. The texture unit retrieves texture commands from the texture request buffer and then fetches the associated texture arguments from the appropriate general purpose register. The texture arguments may be stored in the general purpose register designated as the destination of the final texture value computed by the texture unit. Because the destination register must be allocated for the final texture value as texture commands are queued, storing the texture arguments in this register does not consume any additional registers.

4. 发明申请

US20080143730A1 HIERARCHICAL PROCESSOR ARRAY 有权
标题翻译：分层处理器阵列
公开(公告)号：US20080143730A1
公开(公告)日：2008-06-19
申请号：US11933993
申请日：2007-11-01
申请人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
发明人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
IPC分类号： G06F15/00
CPC分类号： G06T1/20 , G06F9/3851 , G06F9/3887 , G06F9/5044 , G06T15/005
摘要： Apparatuses and methods are presented for a hierarchical processor. The processor comprises, at a first level of hierarchy, a plurality of similarly structured first level components, wherein each of the plurality of similarly structured first level components includes at least one combined function module capable of performing multiple classes of graphics operations, each of the multiple classes of graphics operations being associated with a different stage of graphics processing. The processor comprises, at a second level of hierarchy, a plurality of similarly structured second level components positioned within each one of the plurality of similarly structured first level components, wherein each of the plurality of similarly structured second level components is capable of carrying out different operations from the multiple classes of graphics operations, wherein each first level component is adapted to distribute work to the plurality of similarly structured second level components positioned within the first level component.
摘要翻译：为分级处理器提供了设备和方法。所述处理器在第一级别包括多个类似结构的第一级组件，其中所述多个类似结构的第一级组件中的每一个包括能够执行多类图形操作的至少一个组合功能模块，每个组件与不同阶段的图形处理相关联的多类图形操作。处理器在第二层次上包括定位在多个类似结构的第一级组件中的每一个内的多个类似结构的第二级组件，其中多个类似结构的第二级组件中的每一个能够执行不同的来自多类图形操作的操作，其中每个第一级组件适于将工作分配到定位在第一级组件内的多个相似结构的第二级组件。

5. 发明授权

US08237705B2 Hierarchical processor array 有权
标题翻译：分层处理器阵列
公开(公告)号：US08237705B2
公开(公告)日：2012-08-07
申请号：US13270215
申请日：2011-10-10
申请人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
发明人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
IPC分类号： G06T5/00 , G06T15/50 , G06T15/10 , G06T1/20
CPC分类号： G06T1/20 , G06F9/3851 , G06F9/3887 , G06F9/5044 , G06T15/005
摘要： Apparatuses and methods are presented for a hierarchical processor. The processor comprises, at a first level of hierarchy, a plurality of similarly structured first level components, wherein each of the plurality of similarly structured first level components includes at least one combined function module capable of performing multiple classes of graphics operations, each of the multiple classes of graphics operations being associated with a different stage of graphics processing. The processor comprises, at a second level of hierarchy, a plurality of similarly structured second level components positioned within each one of the plurality of similarly structured first level components, wherein each of the plurality of similarly structured second level components is capable of carrying out different operations from the multiple classes of graphics operations, wherein each first level component is adapted to distribute work to the plurality of similarly structured second level components positioned within the first level component.
摘要翻译：为分级处理器提供了设备和方法。所述处理器在第一级别包括多个类似结构的第一级组件，其中所述多个类似结构的第一级组件中的每一个包括能够执行多类图形操作的至少一个组合功能模块，每个组件与不同阶段的图形处理相关联的多类图形操作。处理器在第二层次上包括定位在多个类似结构的第一级组件中的每一个内的多个类似结构的第二级组件，其中多个类似结构的第二级组件中的每一个能够执行不同的来自多类图形操作的操作，其中每个第一级组件适于将工作分配到定位在第一级组件内的多个相似结构的第二级组件。

6. 发明申请

US20120026175A1 HIERARCHICAL PROCESSOR ARRAY 有权
标题翻译：分层处理器阵列
公开(公告)号：US20120026175A1
公开(公告)日：2012-02-02
申请号：US13270215
申请日：2011-10-10
申请人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
发明人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
IPC分类号： G06T1/00
CPC分类号： G06T1/20 , G06F9/3851 , G06F9/3887 , G06F9/5044 , G06T15/005
摘要： Apparatuses and methods are presented for a hierarchical processor. The processor comprises, at a first level of hierarchy, a plurality of similarly structured first level components, wherein each of the plurality of similarly structured first level components includes at least one combined function module capable of performing multiple classes of graphics operations, each of the multiple classes of graphics operations being associated with a different stage of graphics processing. The processor comprises, at a second level of hierarchy, a plurality of similarly structured second level components positioned within each one of the plurality of similarly structured first level components, wherein each of the plurality of similarly structured second level components is capable of carrying out different operations from the multiple classes of graphics operations, wherein each first level component is adapted to distribute work to the plurality of similarly structured second level components positioned within the first level component.
摘要翻译：为分级处理器提供了设备和方法。所述处理器在第一级别包括多个类似结构的第一级组件，其中所述多个类似结构的第一级组件中的每一个包括能够执行多类图形操作的至少一个组合功能模块，每个组件多种图形操作与不同阶段的图形处理相关联。处理器在第二层次上包括定位在多个类似结构的第一级组件中的每一个内的多个类似结构的第二级组件，其中多个类似结构的第二级组件中的每一个能够执行不同的来自多类图形操作的操作，其中每个第一级组件适于将工作分配到定位在第一级组件内的多个相似结构的第二级组件。

7. 发明授权

US08077174B2 Hierarchical processor array 有权
标题翻译：分层处理器阵列
公开(公告)号：US08077174B2
公开(公告)日：2011-12-13
申请号：US11933993
申请日：2007-11-01
申请人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
发明人： John Erik Lindholm , John S. Montrym , Emmett M. Kilgariff , Simon S. Moy , Sean Jeffrey Treichler , Brett W. Coon , David Kirk , John Danskin
IPC分类号： G06T5/00 , G06T15/50 , G06T15/10 , G06T1/20
CPC分类号： G06T1/20 , G06F9/3851 , G06F9/3887 , G06F9/5044 , G06T15/005
摘要： Apparatuses and methods are presented for a hierarchical processor. The processor comprises, at a first level of hierarchy, a plurality of similarly structured first level components, wherein each of the plurality of similarly structured first level components includes at least one combined function module capable of performing multiple classes of graphics operations, each of the multiple classes of graphics operations being associated with a different stage of graphics processing. The processor comprises, at a second level of hierarchy, a plurality of similarly structured second level components positioned within each one of the plurality of similarly structured first level components, wherein each of the plurality of similarly structured second level components is capable of carrying out different operations from the multiple classes of graphics operations, wherein each first level component is adapted to distribute work to the plurality of similarly structured second level components positioned within the first level component.
摘要翻译：为分级处理器提供了设备和方法。所述处理器在第一级别包括多个类似结构的第一级组件，其中所述多个类似结构的第一级组件中的每一个包括能够执行多类图形操作的至少一个组合功能模块，每个组件与不同阶段的图形处理相关联的多类图形操作。处理器在第二层次上包括定位在多个类似结构的第一级组件中的每一个内的多个类似结构的第二级组件，其中多个类似结构的第二级组件中的每一个能够执行不同的来自多类图形操作的操作，其中每个第一级组件适于将工作分配到定位在第一级组件内的多个相似结构的第二级组件。

8. 发明授权

US07339592B2 Simulating multiported memories using lower port count memories 有权
标题翻译：使用较低端口数存储器模拟多端口存储器
公开(公告)号：US07339592B2
公开(公告)日：2008-03-04
申请号：US10889730
申请日：2004-07-13
申请人： John Erik Lindholm , Ming Y. Siu , Simon S. Moy , Samuel Liu , John R. Nickolls
发明人： John Erik Lindholm , Ming Y. Siu , Simon S. Moy , Samuel Liu , John R. Nickolls
IPC分类号： G06F12/02 , G06F13/00 , G09G5/36
CPC分类号： G06F9/3012 , G06F9/30123 , G06F9/30167 , G06F9/3824 , G06F9/3851 , G06F9/3885
摘要： An apparatus and method for simulating a multiported memory using lower port count memories as banks. A portion of memory is allocated for storing data associated with a thread. The portion of memory allocated to a thread may be stored in a single bank or in multiple banks. A collector unit coupled to each bank gathers source operands needed to process a program instruction as the source operands output from one or more banks. The collector unit outputs the source operands to an execution unit when all of the source operands needed to process the program instruction have been gathered.
摘要翻译：一种使用较低端口计数存储器作为存储体来模拟多端口存储器的装置和方法。分配存储器的一部分用于存储与线程相关联的数据。分配给线程的内存部分可以存储在单个银行或多个银行中。耦合到每个组的收集器单元收集处理程序指令所需的源操作数，作为从一个或多个存储体输出的源操作数。当处理程序指令所需的所有源操作数已经被收集时，收集器单元将源操作数输出到执行单元。

9. 发明申请

US20100122067A1 ACROSS-THREAD OUT-OF-ORDER INSTRUCTION DISPATCH IN A MULTITHREADED MICROPROCESSOR 审中-公开
标题翻译：多功能微处理器中的交叉螺纹指令分配
公开(公告)号：US20100122067A1
公开(公告)日：2010-05-13
申请号：US12690225
申请日：2010-01-20
申请人： John Erik Lindholm , Brett Coon , Simon S. Moy
发明人： John Erik Lindholm , Brett Coon , Simon S. Moy
IPC分类号： G06F9/312
CPC分类号： G06F9/3802 , G06F9/3851
摘要： Instruction dispatch in a multithreaded microprocessor such as a graphics processor is not constrained by an order among the threads. Instructions for each thread are fetched, and a dispatch circuit determines which instructions in the buffer are ready to execute. The dispatch circuit may issue any ready instruction for execution, and an instruction from one thread may be issued prior to an instruction from another thread regardless of which instruction was fetched first. If multiple functional units are available, multiple instructions can be dispatched in parallel.
摘要翻译：诸如图形处理器的多线程微处理器中的指令调度不受线程之间的顺序约束。提取每个线程的指令，调度电路确定缓冲区中的哪些指令准备好执行。调度电路可以发出任何可执行的指令，并且可以在来自另一线程的指令之前发出来自一个线程的指令，而不管首先获取哪个指令。如果有多个功能单元可用，则可以并行调度多个指令。

10. 发明授权

US07676657B2 Across-thread out-of-order instruction dispatch in a multithreaded microprocessor 有权
标题翻译：在多线程微处理器中进行跨线程无序指令调度
公开(公告)号：US07676657B2
公开(公告)日：2010-03-09
申请号：US11548272
申请日：2006-10-10
申请人： John Erik Lindholm , Brett Coon , Simon S. Moy
发明人： John Erik Lindholm , Brett Coon , Simon S. Moy
IPC分类号： G06F9/00
CPC分类号： G06F9/3802 , G06F9/3851
摘要： Instruction dispatch in a multithreaded microprocessor such as a graphics processor is not constrained by an order among the threads. Instructions for each thread are fetched, and a dispatch circuit determines which instructions in the buffer are ready to execute. The dispatch circuit may issue any ready instruction for execution, and an instruction from one thread may be issued prior to an instruction from another thread regardless of which instruction was fetched first. If multiple functional units are available, multiple instructions can be dispatched in parallel.
摘要翻译：诸如图形处理器的多线程微处理器中的指令调度不受线程之间的顺序约束。提取每个线程的指令，调度电路确定缓冲区中的哪些指令准备好执行。调度电路可以发出任何可执行的指令，并且可以在来自另一线程的指令之前发出来自一个线程的指令，而不管首先获取哪个指令。如果有多个功能单元可用，则可以并行调度多个指令。

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