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1. 发明授权

US06289428B1 Superscaler processor and method for efficiently recovering from misaligned data addresses 失效
标题翻译：超标量处理器和方法可以有效地从不对齐的数据地址中恢复
公开(公告)号：US06289428B1
公开(公告)日：2001-09-11
申请号：US09366599
申请日：1999-08-03
申请人： John Edward Derrick , Hung Qui Le , David James Shippy , Larry Edward Thatcher
发明人： John Edward Derrick , Hung Qui Le , David James Shippy , Larry Edward Thatcher
IPC分类号： G06F1202
CPC分类号： G06F9/30043 , G06F9/3824 , G06F12/04
摘要： A superscalar processor and method are disclosed for efficiently recovering from misaligned data addresses. The processor includes a memory device partitioned into a plurality of addressable memory units. Each of the plurality of addressable memory units has a width of a first plurality of bytes. A determination is made regarding whether a data address included within a memory access instruction is misaligned. The data address is misaligned if it includes a first data segment located in a first addressable memory unit and a second data segment located in a second addressable memory unit where the first and second data segments are separated by an addressable memory unit boundary. In response to a determination that the data address is misaligned, a first internal instruction is executed which accesses the first memory unit and obtains the first data segment. A second internal instruction is executed which accesses the second memory unit and obtains the second data segment. The first and second data segments are merged together. All of the instructions executed by the processor are constrained by the memory boundary and do not access memory across the memory boundary.
摘要翻译：公开了一种超标量处理器和方法，用于从未对准的数据地址有效地恢复。处理器包括划分成多个可寻址存储器单元的存储器件。多个可寻址存储器单元中的每一个具有第一多个字节的宽度。确定存储器访问指令中包括的数据地址是否不对齐。如果数据地址包括位于第一可寻址存储器单元中的第一数据段和位于第二可寻址存储器单元中的第二数据段，其中第一和第二数据段由可寻址存储器单元边界分隔，则该数据地址未对准。响应于确定数据地址未对准，执行访问第一存储器单元并获得第一数据段的第一内部指令。执行访问第二存储器单元并获得第二数据段的第二内部指令。第一和第二数据段合并在一起。由处理器执行的所有指令都受到存储器边界的约束，并且不会跨越存储器边界访问存储器。

2. 发明授权

US06442675B1 Compressed string and multiple generation engine 失效
标题翻译：压缩字符串和多代引擎
公开(公告)号：US06442675B1
公开(公告)日：2002-08-27
申请号：US09363464
申请日：1999-07-29
申请人： John Edward Derrick , Lee Evan Eisen , Hung Qui Le
发明人： John Edward Derrick , Lee Evan Eisen , Hung Qui Le
IPC分类号： G06F938
CPC分类号： G06F9/30043 , G06F9/3017
摘要： A generalized, programmable dataflow state-machine is provided to receive information about a particular string instruction. The string instruction is parsed into all the operations contained in the string instruction. The operations that make up the string instruction are routed to parallel functional units and executed. The state-machine manipulates the size of the operations in the string instruction and whether or not the instructions need to be generated.
摘要翻译：提供通用的可编程数据流状态机以接收关于特定字符串指令的信息。字符串指令被解析为字符串指令中包含的所有操作。构成字符串指令的操作被路由到并行功能单元并执行。状态机在字符串指令中操作操作的大小以及是否需要生成指令。

3. 发明授权

US06286094B1 Method and system for optimizing the fetching of dispatch groups in a superscalar processor 有权
标题翻译：用于优化超标量处理器中调度组的获取的方法和系统
公开(公告)号：US06286094B1
公开(公告)日：2001-09-04
申请号：US09263663
申请日：1999-03-05
申请人： John Edward Derrick , Lee Evan Eisen , Hung Qui Le , Brian R. Konigsburg
发明人： John Edward Derrick , Lee Evan Eisen , Hung Qui Le , Brian R. Konigsburg
IPC分类号： G06F930
CPC分类号： G06F9/382 , G06F9/3836 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3857
摘要： A method and system for determining if a dispatch slot is required in a processing system is disclosed. The method and system comprises a plurality of predecode bits to provide routing information and utilizing the predecode bits to allow instructions to be directed to specific decode slots and to obey dispatch constraints without examining the instructions. The purpose of this precode encoding system scheme is to provide the most information possible about the grouping of the instructions without increasing the complexity of the logic which uses this information for decode and group formation. In a preferred embodiment, pre-decode bits for each instruction that may be issued in parallel are analyzed and the multiplexer controls are retained for each of the possible starting positions within the stream of instructions.
摘要翻译：公开了一种用于确定处理系统中是否需要调度槽的方法和系统。所述方法和系统包括多个预解码比特，以提供路由信息并利用所述预解码比特来允许指令被引导到特定解码时隙，并且在不检查指令的情况下服从调度约束。该预编码系统方案的目的是为了提供关于指令分组的可能性最大的信息，而不增加使用该信息进行解码和组形成的逻辑的复杂性。在优选实施例中，分析可以并行发出的每个指令的预解码位，并且为指令流内的每个可能的起始位置保留多路复用器控制。

4. 发明授权

US06345356B1 Method and apparatus for software-based dispatch stall mechanism for scoreboarded IOPs 失效
标题翻译：用于记分板的IOP的基于软件的调度失速机制的方法和装置
公开(公告)号：US06345356B1
公开(公告)日：2002-02-05
申请号：US09354498
申请日：1999-07-16
申请人： John Edward Derrick , Lee Evan Eisen , Hung Qui Le , Robert Greg McDonald
发明人： John Edward Derrick , Lee Evan Eisen , Hung Qui Le , Robert Greg McDonald
IPC分类号： G06F9312
CPC分类号： G06F9/3836 , G06F9/30018 , G06F9/30079 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A dummy instruction is issued, followed by several groups of No Operations (NOPs). The instruction sequencer unit (ISU) detects the dummy instruction and stalls the pipeline until the scoreboard indicates the XER count is valid. After a read from a scoreboarded Special Purpose Register (SPR), No Operation—Internal Operations (NOP—IOPs) are inserted between write and read SPR IOPs to allow an ISU scoreboard mechanism to be activated before being tested by a read SPR IOP. A read-write-read sequence is utilized: a dummy read of the string count field from a scoreboarded SPR, writing that value back to the same SPR and then performing a read of the SPR once again. A predetermined number of dummy IOPs follow the initial dummy read to prevent the value of the string count field from being read too soon.
摘要翻译：发出虚拟指令，其次是几组无操作（NOP）。指令定序器单元（ISU）检测虚拟指令并停止流水线，直到记分板指示XER计数有效。从记分板专用寄存器（SPR）读取后，在写入和读取SPR IOP之间插入无操作内部操作（NOP-IOP），以允许在读取SPR IOP测试之前激活ISU记分板机制。使用读写读取序列：从记分板SPR中读取字符串计数字段，将该值写回相同的SPR，然后再次执行SPR的读取。预定数量的虚拟IOP跟随初始伪读取，以防止字串计数字段的值被读取太快。

5. 发明授权

US06430678B1 Scoreboard mechanism for serialized string operations utilizing the XER 失效
标题翻译：使用XER的串行字符串操作的记分板机制
公开(公告)号：US06430678B1
公开(公告)日：2002-08-06
申请号：US09363463
申请日：1999-07-29
申请人： James Allan Kahle , Hung Qui Le , Lee Evan Eisen , John Edward Derrick , Robert William Hay
发明人： James Allan Kahle , Hung Qui Le , Lee Evan Eisen , John Edward Derrick , Robert William Hay
IPC分类号： G06F930
CPC分类号： G06F9/30018 , G06F9/3017 , G06F9/325 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3867
摘要： An XER scoreboard function is provided by utilizing the instruction sequencer unit scoreboard. A scoreboard bit is set if the XER is being used by a previous instruction. If a new instruction is fetched that uses the XER, a dummy read to the XER is generated to test the scoreboard bit to determine if the scoreboard bit is set. If the scoreboard bit is not set when the dummy read is executed, the X-form string proceeds to execution. If the scoreboard bit is set when the dummy is executed, the pipeline is stalled until the scoreboard bit is cleared, and then the X-form string padded with generated padding IOPs (Dummy or NOPs) is executed. After an accessing instruction is executed, the scoreboard bit is cleared.
摘要翻译：通过使用指令排序器单元记分板提供XER记分板功能。如果XER由前一条指令使用，记分板位将被置位。如果获取使用XER的新指令，则生成对XER的虚拟读取以测试记分板位以确定记分板位是否设置。如果执行虚拟读取时记分板位未设置，则X形式的字符串将继续执行。如果在执行虚拟机时设置了记分板位，则流水线停止，直到记分板位被清除，然后执行填充有生成的填充IOP（虚拟或NOP）的X形式字符串。执行访问指令后，记分板位被清除。

6. 发明授权

US06425069B1 Optimization of instruction stream execution that includes a VLIW dispatch group 有权
标题翻译：优化包含VLIW调度组的指令流执行
公开(公告)号：US06425069B1
公开(公告)日：2002-07-23
申请号：US09263664
申请日：1999-03-05
申请人： Larry Edward Thatcher , John Edward Derrick
发明人： Larry Edward Thatcher , John Edward Derrick
IPC分类号： G06F1500
CPC分类号： G06F9/3853 , G06F9/3834
摘要： A method and system for optimizing execution of an instruction stream which includes a very long instruction word (VLIW) dispatch group in which ordering is not maintained is disclosed. The method and system comprises examining an access which initiated a flush operation; capturing an indice related to the flush operation; and causing all storage access instructions related to this indice to be dispatched as single-IOP groups until the indice is updated. Storage access to address space which is safe such as Guarded (G=1) or Direct Store (E=DS) must be handled in a non-speculative manner such that operations which could potentially go to volatile I/O devices or control locations that do not get processed out of order. Since the address is not known in the front end of the processor, this can only be determined by the load store unit or functional block which performs translation. Therefore, if a flush occurs for these conditions, in accordance with the present invention the value of the base register (RA) is latched and subsequent loads and stores which use this base register are decoded in a “safe” manner until an instruction is decoded which would change the base register value (safe means an internal instruction sequence which can be executed in order without repeating any accesses). The value of multiple base registers can be tracked in this manner, though the preferred embodiment would not use more than two, one of the base registers could be for input and one could be for output streams.
摘要翻译：公开了一种优化执行指令流的方法和系统，该方法和系统包括不维护顺序的非常长的指令字（VLIW）调度组。该方法和系统包括检查启动冲洗操作的访问; 捕获与冲洗操作相关的指示; 并将与此Indice相关的所有存储访问指令作为单IOP组发送，直到更新指示符。必须以不推测的方式来处理诸如保护（G = 1）或直接存储（E = DS）等安全的地址空间的存储访问，以使可能进入易失性I / O设备或控制位置的操作不要处理乱序。由于地址在处理器的前端是未知的，所以这只能由加载存储单元或执行翻译的功能块来确定。因此，如果对于这些条件发生冲突，根据本发明，基本寄存器（RA）的值被锁存，并且使用该基本寄存器的后续加载和存储以“安全”的方式被解码，直到指令被解码这将改变基址寄存器值（安全是指可以顺序执行而不重复任何访问的内部指令序列）。可以以这种方式跟踪多个基站寄存器的值，尽管优选实施例不会使用多于两个的基本寄存器中的一个可以用于输入，一个可以用于输出流。

7. 发明授权

US06574727B1 Method and apparatus for instruction sampling for performance monitoring and debug 失效
标题翻译：用于性能监控和调试的指令采样方法和装置
公开(公告)号：US06574727B1
公开(公告)日：2003-06-03
申请号：US09435069
申请日：1999-11-04
申请人： Joel Roger Davidson , John Edward Derrick , Alexander Erik Mericas
发明人： Joel Roger Davidson , John Edward Derrick , Alexander Erik Mericas
IPC分类号： G06F900
CPC分类号： G06F9/3836 , G06F9/3017 , G06F9/3857 , G06F11/348 , G06F2201/88
摘要： A method and apparatus for selecting an instruction to be monitored within a pipelined processor in a data processing system is presented. A plurality of instructions are fetched, and the plurality of instructions are matched against at least one match condition to generate instructions that are eligible for sampling. The match conditions may include matching the opcode of an instruction, the pre-decode bits of an instruction, a type of instruction, or other conditions. The matched instructions may be marked using a match bit that accompanies the instruction through the selection process. The instructions eligible for sampling are then sampled to generate a sampled instruction. A sampled instruction may be marked with a sample bit that accompanies the instruction through the instruction execution process in order to monitor the sampled instruction while it is executing within the pipelined processor.
摘要翻译：提出了一种在数据处理系统中选择流水线处理器内要监视的指令的方法和装置。获取多个指令，并且将多个指令与至少一个匹配条件进行匹配，以生成符合抽样要求的指令。匹配条件可以包括匹配指令的操作码，指令的预解码位，指令的类型或其他条件。可以使用通过选择过程伴随指令的匹配位来标记匹配的指令。然后对符合抽样要求的指令进行采样以产生采样指令。采样指令可以通过指令执行过程伴随指令的采样位进行标记，以便在流水线处理器中执行时监视采样指令。

8. 发明授权

US06304959B1 Simplified method to generate BTAGs in a decode unit of a processing system 失效
标题翻译：在处理系统的解码单元中生成BTAG的简化方法
公开(公告)号：US06304959B1
公开(公告)日：2001-10-16
申请号：US09263669
申请日：1999-03-05
申请人： Brian R. Konigsburg , John Edward Derrick , David Stephen Levitan
发明人： Brian R. Konigsburg , John Edward Derrick , David Stephen Levitan
IPC分类号： G06F938
CPC分类号： G06F9/3804 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857
摘要： A method and system for assigning unique branch tag (BTAG) values in a decode unit in a processing system are disclosed. The method and system comprise providing at least one BTAG value and incrementing the at least one BTAG value for each fetch group as required. The method includes allowing the decode unit to generate the appropriate BTAG values for all dispatch groups formed by instructions within the same fetch group. In the preferred implementation, the BTAG values comprise a major branch tag and two minor branch tags, a count branch tag, and a link branch tag. The “seed” value for each of the BTAGs is provided each time a branch redirection occurs. Because the branches are passed to the decode unit with little or no processing by the instruction fetch unit, and conditions can cause the branch execution to be delayed, more branches could be decoded and processed than the number of branch entry queues in the instruction fetch unit. Therefore the value of the next entry in the branch entry queue is broadcast to the decode unit and whenever the current branch in the last stage of the decode unit is identical to the broadcast value, the decode unit ceases to process any output instructions until the broadcast value changes.
摘要翻译：公开了一种用于在处理系统中的解码单元中分配唯一分支标签（BTAG）值的方法和系统。该方法和系统包括提供至少一个BTAG值并根据需要递增每个获取组的至少一个BTAG值。该方法包括允许解码单元为由同一取出组内的指令形成的所有调度组生成适当的BTAG值。在优选实现中，BTAG值包括主要分支标签和两个次要分支标签，计数分支标签和链接分支标签。每次发生分支重定向时都提供每个BTAG的“种子”值。由于分支通过指令获取单元很少或不处理地被传递到解码单元，并且条件可以导致分支执行被延迟，所以可以比指令获取单元中的分支输入队列的数量更多的分支被解码和处理。因此，分支输入队列中的下一个条目的值被广播到解码单元，并且每当解码单元的最后一级中的当前分支与广播值相同时，解码单元停止处理任何输出指令直到广播价值变化。

9. 发明授权

US06385719B1 Method and apparatus for synchronizing parallel pipelines in a superscalar microprocessor 失效
标题翻译：用于在超标量微处理器中同步并行管线的方法和装置
公开(公告)号：US06385719B1
公开(公告)日：2002-05-07
申请号：US09345719
申请日：1999-06-30
申请人： John Edward Derrick , Brian R. Konigsburg , Lee Evan Eisen , David Stephen Levitan
发明人： John Edward Derrick , Brian R. Konigsburg , Lee Evan Eisen , David Stephen Levitan
IPC分类号： G06F938
CPC分类号： G06F9/3804 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： A transfer tag is generated by the Instruction Fetch Unit and passed to the decode unit in the instruction pipeline with each group of instructions fetched during a branch prediction by a fetcher. Individual instructions within the fetched group for the branch pipeline are assigned a concatenated version (group tag concatenated with instruction lane) of the transfer tag which is used to match on requests to flush any newer instructions. All potential instruction or Internal Operation latches in the decode pipeline must perform a match and if a match is encountered, all valid bits associated with newer instructions or internal operations upstream from the match are cleared. The transfer tag representing the next instruction to be processed in the branch pipeline is passed to the Instruction Dispatch Unit. The Instruction Dispatch Unit queries the branch pipeline to compare its transfer tag with transfer tags of instructions in the branch pipeline. If the transfer tag matches a branch instruction tag the Instruction Decode Unit is stalled until the branch instruction is processed thus, providing a synchronizing method for the parallel pipelines.
摘要翻译：传送标签由指令提取单元生成，并在指令流水线中传送给解码单元，每个指令组由读取器在分支预测期间取出。为分支流水线提取的组中的单独指令被分配用于匹配在刷新任何较新指令的请求上的传送标签的级联版本（组标签与指令通道连接）。解码流水线中的所有潜在指令或内部操作锁存器必须执行匹配，并且如果遇到匹配，将清除与较新指令相关联的所有有效位或匹配上游的内部操作。表示在分支管线中要处理的下一条指令的传送标签被传递到指令调度单元。指令调度单元查询分支流水线以将其传输标签与分支流水线中的指令的传输标签进行比较。如果转移标签与分支指令标签匹配，则指令解码单元停止，直到处理分支指令为止，为并行管线提供同步方法。

10. 发明授权

US5906659A Computer system buffers for providing concurrency between CPU accesses, local bus accesses, and memory accesses 失效
标题翻译：用于提供CPU访问，本地总线访问和内存访问之间并发性的计算机系统缓冲区
公开(公告)号：US5906659A
公开(公告)日：1999-05-25
申请号：US911174
申请日：1997-08-14
申请人： John Edward Derrick , William R. Greer , Christopher Michael Herring
发明人： John Edward Derrick , William R. Greer , Christopher Michael Herring
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4059
摘要： Buffers are provided in a computer system to allow posting data to the buffers, followed by concurrent operation by different portions of the computer system. A CPU buffer is provided to buffer CPU accesses, a CPU-to-PCI buffer is provided to buffer CPU accesses to the PCI local bus, and a memory buffer is provided to buffer CPU accesses to main memory. This configuration allows the CPU-to-PCI buffer to write data concurrently with the memory buffer accessing data from main memory.
摘要翻译：在计算机系统中提供缓冲器以允许将数据发布到缓冲器，随后由计算机系统的不同部分进行并发操作。提供CPU缓冲器以缓冲CPU访问，提供CPU至PCI缓冲器以缓冲CPU对PCI本地总线的访问，并提供存储缓冲区以缓冲CPU对主存储器的访问。该配置允许CPU到PCI缓冲器与存储缓冲区并发地访问来自主存储器的数据。

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