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1. 发明申请

US20110177660A1 DEEP TRENCH CAPACITOR FOR SOI CMOS DEVICES FOR SOFT ERROR IMMUNITY 有权
标题翻译：用于软错误免疫的SOI CMOS器件的深度TRENCH电容器
公开(公告)号：US20110177660A1
公开(公告)日：2011-07-21
申请号：US13075271
申请日：2011-03-30
申请人： John E. Barth, JR. , Kerry Bernstein , Ethan H. Cannon , Francis R. White
发明人： John E. Barth, JR. , Kerry Bernstein , Ethan H. Cannon , Francis R. White
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0629 , H01L27/10861 , H01L29/66181
摘要： A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device, and is located adjacent to the gate of the semiconductor device. The semiconductor structure increases a critical charge Qcrit, thereby reducing a soft error rate (SER) of the semiconductor device.
摘要翻译：公开了半导体结构。半导体结构包括有源半导体层，具有设置在有源半导体层顶部的栅极的半导体器件以及设置在有源半导体层内的源极和漏极区域以及主体/沟道区域，具有第一和第二所述第一侧与所述有源半导体层相邻，与所述绝缘体层的所述第二侧相邻配置的衬底，设置在所述半导体器件的所述主体/沟道区域下方的深沟槽电容器。深沟槽电容器与半导体器件的主体/沟道区电连接并接触半导体器件的主体/沟道区，并且位于半导体器件的栅极附近。半导体结构增加了临界电荷Qcrit，从而降低了半导体器件的软错误率（SER）。

2. 发明申请

US20090224304A1 SOFT ERROR PROTECTION STRUCTURE EMPLOYING A DEEP TRENCH 失效
标题翻译：使用深度感应器的软错误保护结构
公开(公告)号：US20090224304A1
公开(公告)日：2009-09-10
申请号：US12045190
申请日：2008-03-10
申请人： Ethan H. Cannon , John E. Barth, JR. , Kerry Bernstein
发明人： Ethan H. Cannon , John E. Barth, JR. , Kerry Bernstein
IPC分类号： H01L27/105 , H01L21/8232
CPC分类号： H01L29/66181 , G11C5/005 , H01L21/765 , H01L27/0629 , H01L27/11 , H01L29/945
摘要： A deep trench containing a doped semiconductor fill portion having a first conductivity type doping and surrounded by a buried plate layer having a second conductivity type doping at a lower portion is formed in a semiconductor layer having a doping of the first conductivity type. A doped well of the second conductivity type abutting the buried plate layer is formed. The doped semiconductor fill portion functions as a temporary reservoir for electrical charges of the first conductivity type that are generated by a radiation particle, and the buried plate layer functions as a temporary reservoir for electrical charges of the second conductivity type. The buried plate layer and the doped semiconductor fill portion forms a capacitor, and provides protection from soft errors to devices formed in the semiconductor layer or the doped well.
摘要翻译：在具有第一导电类型的掺杂的半导体层中形成包含掺杂半导体填充部分的深沟槽，该掺杂半导体填充部分具有第一导电类型掺杂并被由下部具有第二导电类型掺杂的掩埋板包围。形成与掩埋板层相邻的第二导电类型的掺杂阱。掺杂半导体填充部分用作由辐射颗粒产生的第一导电类型的电荷的临时储存器，并且掩埋板层用作第二导电类型的电荷的临时储存器。掩埋板层和掺杂半导体填充部分形成电容器，并且提供对软错误的保护以防止在半导体层或掺杂阱中形成的器件。

3. 发明申请

US20110177659A1 SOI BODY CONTACT USING E-DRAM TECHNOLOGY 有权
标题翻译： SOI身体接触使用电子DRAM技术
公开(公告)号：US20110177659A1
公开(公告)日：2011-07-21
申请号：US13075552
申请日：2011-03-30
申请人： John E. Barth, JR. , Kerry Bernstein , Francis R. White
发明人： John E. Barth, JR. , Kerry Bernstein , Francis R. White
IPC分类号： H01L21/336
CPC分类号： H01L29/78615
摘要： A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a body contact disposed under the body/channel region and in the insulator layer. The body contact electrically connects with and contacts with the body/channel region of the semiconductor device and the substrate, to thereby form an ohmic contact and to eliminate floating body effects.
摘要翻译：公开了半导体结构。半导体结构包括有源半导体层，具有设置在有源半导体层顶部的栅极的半导体器件以及设置在有源半导体层内的源极和漏极区域以及主体/沟道区域，具有第一和第二所述第一侧与所述有源半导体层相邻，与所述绝缘体层的第二侧相邻配置的基板，设置在所述主体/沟道区域的下方以及所述绝缘体层的主体接触部。体接触与半导体器件和衬底的主体/沟道区域电连接并与其接触，从而形成欧姆接触并消除浮体效应。

4. 发明申请

US20100052053A1 SOI BODY CONTACT USING E-DRAM TECHNOLOGY 有权
标题翻译： SOI身体接触使用电子DRAM技术
公开(公告)号：US20100052053A1
公开(公告)日：2010-03-04
申请号：US12200482
申请日：2008-08-28
申请人： John E. Barth, JR. , Kerry Bernstein , Francis R. White
发明人： John E. Barth, JR. , Kerry Bernstein , Francis R. White
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/78615
摘要： A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a body contact disposed under the body/channel region and in the insulator layer. The body contact electrically connects with and contacts with the body/channel region of the semiconductor device and the substrate, to thereby form an ohmic contact and to eliminate floating body effects.
摘要翻译：公开了半导体结构。半导体结构包括有源半导体层，具有设置在有源半导体层顶部的栅极的半导体器件以及设置在有源半导体层内的源极和漏极区域以及主体/沟道区域，具有第一和第二所述第一侧与所述有源半导体层相邻，与所述绝缘体层的第二侧相邻配置的基板，设置在所述主体/沟道区域的下方以及所述绝缘体层的主体接触部。体接触与半导体器件和衬底的主体/沟道区域电连接并与其接触，从而形成欧姆接触并消除浮体效应。

5. 发明申请

US20100052108A1 VERTICAL THROUGH-SILICON VIA FOR A SEMICONDUCTOR STRUCTURE 有权
标题翻译：通过半导体结构的垂直硅
公开(公告)号：US20100052108A1
公开(公告)日：2010-03-04
申请号：US12201580
申请日：2008-08-29
申请人： John E. Barth, JR. , Kerry Bernstein
发明人： John E. Barth, JR. , Kerry Bernstein
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/481 , H01L23/5223 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor structure includes at least one silicon substrate having first and second planar surfaces, and at least one through silicon via filled with a conductive material and extending vertically through the first planar surface of the at least one silicon substrate to the second planar surface thereof. The through silicon via forms a vertical interconnection between a plurality of electronic circuits and an amount of dielectric insulation surrounding the through silicon via is varied based on a defined function of the through silicon via.
摘要翻译：半导体结构包括具有第一和第二平面表面的至少一个硅衬底，以及填充有导电材料并且至少穿过至少一个硅衬底的第一平坦表面垂直延伸到其第二平坦表面的至少一个穿硅通孔。穿通硅通孔在多个电子电路之间形成垂直互连，并且围绕穿过硅通孔的绝缘绝缘体的量基于硅通孔的限定功能而变化。

6. 发明申请

US20100052100A1 DEEP TRENCH ELECTROSTATIC DISCHARGE (ESD) PROTECT DIODE FOR SILICON-ON-INSULATOR (SOI) DEVICES 有权
标题翻译：用于硅绝缘体（SOI）器件的深度放电静电放电（ESD）保护二极管
公开(公告)号：US20100052100A1
公开(公告)日：2010-03-04
申请号：US12201462
申请日：2008-08-29
申请人： John E. Barth, JR. , Kerry Bernstein
发明人： John E. Barth, JR. , Kerry Bernstein
IPC分类号： H01L29/8605 , H01L21/02
CPC分类号： H01L29/861 , H01L21/761 , H01L21/76264 , H01L23/535 , H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure is disclosed. The semiconductor structure includes a bulk substrate of a first polarity type, a buried insulator layer disposed on the bulk substrate, an active semiconductor layer disposed on top of the buried insulator layer including a shallow trench isolation region and a diffusion region of the first polarity type, a band region of a second polarity type disposed directly beneath the buried insulator layer and forming a conductive path, a well region of the second polarity type disposed in the bulk substrate and in contact with the band region, a deep trench filled with a conductive material of the first polarity type disposed within the well region, and an electrostatic discharge (ESD) protect diode defined by a junction between a lower portion of the deep trench and the well region.
摘要翻译：公开了半导体结构。半导体结构包括第一极性类型的体基板，设置在体基板上的掩埋绝缘体层，设置在包括浅沟槽隔离区域和第一极性类型的扩散区域的掩埋绝缘体层的顶部上的有源半导体层设置在掩埋绝缘体层正下方并形成导电路径的第二极性类型的带区域，设置在本体衬底中并与带区接触的第二极性类型的阱区，填充有导电的深沟槽设置在阱区内的第一极性类型的材料以及由深沟槽的下部和阱区之间的接合部限定的静电放电（ESD）保护二极管。

7. 发明申请

US20120083091A1 DEEP TRENCH ELECTROSTATIC DISCHARGE (ESD) PROTECT DIODE FOR SILICON-ON-INSULATOR (SOI) DEVICES 失效
标题翻译：用于硅绝缘体（SOI）器件的深度放电静电放电（ESD）保护二极管
公开(公告)号：US20120083091A1
公开(公告)日：2012-04-05
申请号：US13324486
申请日：2011-12-13
申请人： John E. Barth, JR. , Kerry Bernstein
发明人： John E. Barth, JR. , Kerry Bernstein
IPC分类号： H01L21/02
CPC分类号： H01L29/861 , H01L21/761 , H01L21/76264 , H01L23/535 , H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor includes a bulk substrate of a first polarity type, a buried insulator layer disposed on the bulk substrate, an active semiconductor layer disposed on top of the buried insulator layer including a shallow trench isolation region and a diffusion region of the first polarity type, a band region of a second polarity type disposed directly beneath the buried insulator layer and forming a conductive path, a well region of the second polarity type disposed in the bulk substrate and in contact with the band region, a deep trench filled with a conductive material of the first polarity type disposed within the well region, and an electrostatic discharge (ESD) protect diode defined by a junction between a lower portion of the deep trench and the well region.
摘要翻译：半导体包括第一极性类型的体基板，设置在体基板上的掩埋绝缘体层，设置在包括浅沟槽隔离区和第一极性类型的扩散区的掩埋绝缘体层的顶部上的有源半导体层，第二极性类型的带区域直接设置在掩埋绝缘体层的正下方并形成导电路径，第二极性类型的阱区域布置在本体衬底中并与带区域接触，填充有导电材料的深沟槽设置在阱区内的第一极性类型和由深沟槽的下部与阱区之间的接合部限定的静电放电（ESD）保护二极管。

8. 发明申请

US20130262792A1 MEMORY DEVICE SUPPORT OF DYNAMICALLY CHANGING FREQUENCY IN MEMORY SYSTEMS 审中-公开
标题翻译：记忆体系中动态变化频率的记忆体设备支持
公开(公告)号：US20130262792A1
公开(公告)日：2013-10-03
申请号：US13431108
申请日：2012-03-27
申请人： John E. Barth, JR. , Joab D. Henderson , Ryan J. Pennington , Anuwat Saetow , Robert B. Tremaine , Kenneth L. Wright
发明人： John E. Barth, JR. , Joab D. Henderson , Ryan J. Pennington , Anuwat Saetow , Robert B. Tremaine , Kenneth L. Wright
IPC分类号： G06F12/00
CPC分类号： G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： An embodiment is a method includes writing a first set of memory device parameters to a first mode register in a memory device, wherein the first set of memory device parameters correspond to a first frequency, monitoring selected parameters for the memory system while the memory device operates at the first frequency and predicting a second frequency that the memory device will operate at subsequent to the first frequency, the predicting being based on the monitored selected parameters. The method further includes writing a second set of memory device parameters to second mode register in the memory device, receiving a frequency change request at a memory controller associated with the memory device, the frequency change request to operate at a new frequency and updating the first mode register with the second set of memory device parameters from the second mode register responsive to the new frequency being equal to the second frequency.
摘要翻译：实施例是一种方法，包括将第一组存储器件参数写入存储器件中的第一模式寄存器，其中第一组存储器件参数对应于第一频率，在存储器件操作期间监视存储器系统的选定参数在第一频率处，并且预测存储器设备将在第一频率之后操作的第二频率，所述预测基于所监视的所选择的参数。该方法还包括将第二组存储器件参数写入存储器件中的第二模式寄存器，在与存储器件相关联的存储器控制器处接收频率改变请求，频率改变请求以新频率操作并更新第一模式寄存器，响应于新频率等于第二频率，来自第二模式寄存器的第二组存储器件参数。

9. 发明申请

US20110267916A1 VDD PRE-SET OF DIRECT SENSE DRAM 有权
标题翻译：直流感测DRAM的VDD预置
公开(公告)号：US20110267916A1
公开(公告)日：2011-11-03
申请号：US12770976
申请日：2010-04-30
申请人： John E. Barth, JR.
发明人： John E. Barth, JR.
IPC分类号： G11C5/14
CPC分类号： G11C11/4091
摘要： A direct sense memory array architecture and method of operation includes a plurality of memory cells where a bit-line restore voltage level is optimized to reduce memory cell leakage during a first inactive period, and a bit-line preset voltage level is optimized for signal sensing during a second active period. The architecture includes a sense head having of a pair of cross coupled gated inverters. Each of the gated inverters is responsive to a first and second gate control signal which can independently gate a power supply to the inverter circuit within each gated inverter. During the second active period, a first gated inverter senses the data state on the first bit-line, and a second gated inverter performs a preset and write-back function on the first bit-line.
摘要翻译：直接读出存储器阵列结构和操作方法包括多个存储器单元，其中位线恢复电压电平被优化以在第一非活动时段期间减少存储器单元泄漏，并且位线预设电压电平被优化用于信号感测在第二个活跃期间。该架构包括具有一对交叉耦合门控反相器的感测头。每个门控逆变器响应于第一和第二门控制信号，该第一和第二门控制信号可以独立地对每个门控逆变器内的逆变器电路的电源供电。在第二活动期间，第一选通逆变器检测第一位线上的数据状态，第二门控反相器在第一位线上执行预置和回写功能。

10. 发明申请

US20100001788A1 SYSTEM TO EVALUATE CHARGE PUMP OUTPUTS AND ASSOCIATED METHODS 审中-公开
标题翻译：评估充电泵输出和相关方法的系统
公开(公告)号：US20100001788A1
公开(公告)日：2010-01-07
申请号：US12168136
申请日：2008-07-06
申请人： John E. Barth, JR. , John A. Fifield , Fadi H. Gebara , Jente B. Kuang , Michael Sperling
发明人： John E. Barth, JR. , John A. Fifield , Fadi H. Gebara , Jente B. Kuang , Michael Sperling
IPC分类号： G05F3/02 , G05F1/10
CPC分类号： H02M3/07
摘要： A system to evaluate charge pump output may include a comparator to compare a charge pump output voltage to a reference voltage to generate a comparison result. The system may also include a divider to divide down a clock signal. The system may further include a logical conjunction unit to operate on the comparison result and the divided down clock signal.
摘要翻译：用于评估电荷泵输出的系统可以包括比较器，用于将电荷泵输出电压与参考电压进行比较以产生比较结果。该系统还可以包括用于分频时钟信号的分频器。该系统还可以包括对比较结果和划分的下降时钟信号进行操作的逻辑连接单元。

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