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1. 发明申请

US20080247245A1 WRITE CONTROL METHOD FOR A MEMORY ARRAY CONFIGURED WITH MULTIPLE MEMORY SUBARRAYS 失效
标题翻译：用于配置多个存储器子选项的存储器阵列的写控制方法
公开(公告)号：US20080247245A1
公开(公告)日：2008-10-09
申请号：US12139675
申请日：2008-06-16
申请人： John D. Davis , Paul A. Bunce , Donald W. Plass , Kenneth J. Reyer
发明人： John D. Davis , Paul A. Bunce , Donald W. Plass , Kenneth J. Reyer
IPC分类号： G11C7/22
CPC分类号： G11C11/413 , G11C7/18
摘要： Write control circuitry and control method are provided for a memory array configured with multiple memory subarrays. The write control circuitry includes multiple subarray write controllers associated with the multiple memory subarrays, each subarray write controller selectively enabling a local write control signal to its associated memory subarray. The selectively enabling is responsive to a received subarray select signal, wherein only one subarray select signal is active at a time. At least some subarray write controllers are powered at least in part via a switched power node, wherein powering of the switched power node is distributively implemented among the subarray write controllers. In one example, the distributively implemented powering of the switched power node is accomplished via multiple inverters distributed among the subarray write controllers, each inverter having an output coupled to the switched power node, and an input coupled to receive a global write enable signal.
摘要翻译：为配置有多个存储器子阵列的存储器阵列提供写控制电路和控制方法。写控制电路包括与多个存储器子阵列相关联的多个子阵列写控制器，每个子阵列写控制器选择性地使本地写控制信号到其相关的存储器子阵列。选择性地使能响应于接收的子阵列选择信号，其中一次只有一个子阵列选择信号是有效的。至少一些子阵列写控制器至少部分地通过交换式电源节点供电，其中，在子阵列写入控制器之间分配地实现切换的功率节点的供电。在一个示例中，通过分布在子阵列写控制器之间的多个反相器实现开关电源节点的分布式实现的供电，每个反相器具有耦合到开关电源节点的输出，以及耦合以接收全局写使能信号的输入。

2. 发明授权

US07283417B2 Write control circuitry and method for a memory array configured with multiple memory subarrays 失效
标题翻译：用于配置有多个存储器子阵列的存储器阵列的写控制电路和方法
公开(公告)号：US07283417B2
公开(公告)日：2007-10-16
申请号：US11054059
申请日：2005-02-09
申请人： John D. Davis , Paul A. Bunce , Donald W. Plass , Kenneth J. Reyer
发明人： John D. Davis , Paul A. Bunce , Donald W. Plass , Kenneth J. Reyer
IPC分类号： G11C8/00
CPC分类号： G11C11/413 , G11C7/18
摘要： Write control circuitry and control method are provided for a memory array configured with multiple memory subarrays. The write control circuitry includes multiple subarray write controllers associated with the multiple memory subarrays, each subarray write controller selectively enabling a local write control signal to its associated memory subarray. The selectively enabling is responsive to a received subarray select signal, wherein only one subarray select signal is active at a time. At least some subarray write controllers are powered at least in part via a switched power node, wherein powering of the switched power node is distributively implemented among the subarray write controllers. In one example, the distributively implemented powering of the switched power node is accomplished via multiple inverters distributed among the subarray write controllers, each inverter having an output coupled to the switched power node, and an input coupled to receive a global write enable signal.
摘要翻译：为配置有多个存储器子阵列的存储器阵列提供写控制电路和控制方法。写控制电路包括与多个存储器子阵列相关联的多个子阵列写控制器，每个子阵列写控制器选择性地使本地写控制信号到其相关的存储器子阵列。选择性地使能响应于接收的子阵列选择信号，其中一次只有一个子阵列选择信号是有效的。至少一些子阵列写控制器至少部分地通过交换式电源节点供电，其中，在子阵列写入控制器之间分配地实现切换的功率节点的供电。在一个示例中，通过分布在子阵列写控制器之间的多个反相器实现开关电源节点的分布式实现的供电，每个反相器具有耦合到开关电源节点的输出，以及耦合以接收全局写使能信号的输入。

3. 发明授权

US07688650B2 Write control method for a memory array configured with multiple memory subarrays 失效
标题翻译：用多个存储器子阵列配置的存储器阵列的写控制方法
公开(公告)号：US07688650B2
公开(公告)日：2010-03-30
申请号：US12139675
申请日：2008-06-16
申请人： John D. Davis , Paul A. Bunce , Donald W. Plass , Kenneth J. Reyer
发明人： John D. Davis , Paul A. Bunce , Donald W. Plass , Kenneth J. Reyer
IPC分类号： G11C7/00 , G11C7/22
CPC分类号： G11C11/413 , G11C7/18
摘要： Write control circuitry and control method are provided for a memory array configured with multiple memory subarrays. The write control circuitry includes multiple subarray write controllers associated with the multiple memory subarrays, each subarray write controller selectively enabling a local write control signal to its associated memory subarray. The selectively enabling is responsive to a received subarray select signal, wherein only one subarray select signal is active at a time. At least some subarray write controllers are powered at least in part via a switched power node, wherein powering of the switched power node is distributively implemented among the subarray write controllers. In one example, the distributively implemented powering of the switched power node is accomplished via multiple inverters distributed among the subarray write controllers, each inverter having an output coupled to the switched power node, and an input coupled to receive a global write enable signal.
摘要翻译：为配置有多个存储器子阵列的存储器阵列提供写控制电路和控制方法。写控制电路包括与多个存储器子阵列相关联的多个子阵列写控制器，每个子阵列写控制器选择性地使本地写控制信号到其相关的存储器子阵列。选择性地使能响应于接收的子阵列选择信号，其中一次只有一个子阵列选择信号是有效的。至少一些子阵列写控制器至少部分地通过交换式电源节点供电，其中，在子阵列写入控制器之间分配地实现切换的功率节点的供电。在一个示例中，通过分布在子阵列写控制器之间的多个反相器实现开关电源节点的分布式实现的供电，每个反相器具有耦合到开关电源节点的输出，以及耦合以接收全局写使能信号的输入。

4. 发明授权

US07471590B2 Write control circuitry and method for a memory array configured with multiple memory subarrays 失效
标题翻译：用于配置有多个存储器子阵列的存储器阵列的写控制电路和方法
公开(公告)号：US07471590B2
公开(公告)日：2008-12-30
申请号：US11762833
申请日：2007-06-14
申请人： John D. Davis , Paul A. Bunce , Donald W. Plass , Kenneth J Reyer
发明人： John D. Davis , Paul A. Bunce , Donald W. Plass , Kenneth J Reyer
IPC分类号： G11C8/00
CPC分类号： G11C11/413 , G11C7/18
摘要： Write control circuitry and control method are provided for a memory array configured with multiple memory subarrays. The write control circuitry includes multiple subarray write controllers associated with the multiple memory subarrays, each subarray write controller selectively enabling a local write control signal to its associated memory subarray. The selectively enabling is responsive to a received subarray select signal, wherein only one subarray select signal is active at a time. At least some subarray write controllers are powered at least in part via a switched power node, wherein powering of the switched power node is distributively implemented among the subarray write controllers. In one example, the distributively implemented powering of the switched power node is accomplished via multiple inverters distributed among the subarray write controllers, each inverter having an output coupled to the switched power node, and an input coupled to receive a global write enable signal.
摘要翻译：为配置有多个存储器子阵列的存储器阵列提供写控制电路和控制方法。写控制电路包括与多个存储器子阵列相关联的多个子阵列写控制器，每个子阵列写控制器选择性地使本地写控制信号到其相关的存储器子阵列。选择性地使能响应于接收的子阵列选择信号，其中一次只有一个子阵列选择信号是有效的。至少一些子阵列写控制器至少部分地通过交换式电源节点供电，其中，在子阵列写入控制器之间分配地实现切换的功率节点的供电。在一个示例中，通过分布在子阵列写控制器之间的多个反相器实现开关电源节点的分布式实现的供电，每个反相器具有耦合到开关电源节点的输出，以及耦合以接收全局写使能信号的输入。

5. 发明授权

US07299374B2 Clock control method and apparatus for a memory array 有权
标题翻译：用于存储器阵列的时钟控制方法和装置
公开(公告)号：US07299374B2
公开(公告)日：2007-11-20
申请号：US11050580
申请日：2005-02-03
申请人： James W. Dawson , Paul A. Bunce , Donald W. Plass , Kenneth J. Reyer
发明人： James W. Dawson , Paul A. Bunce , Donald W. Plass , Kenneth J. Reyer
IPC分类号： G06F1/08 , G06F1/04
CPC分类号： G06F1/04 , G11C7/22 , G11C7/222 , G11C7/227
摘要： A clock control method and apparatus are provided employing a clock control circuit which generates an array clock for a memory array from a system clock and a reset control signal. The reset control signal is one of a plurality of input control signals to the clock control circuit. When the system clock is below a predefined frequency threshold, the reset control signal is an array tracking reset signal, wherein the active pulse width of the array clock is system clock frequency independent, and when the system clock is above the predefined frequency threshold, the reset control signal is a mid-cycle reset signal, meaning that the active pulse width of the array clock is system clock frequency dependent. A bypass signal is provided as a third input control signal, which when active causes the clock control circuit to output an array clock which mirrors the system clock.
摘要翻译：提供了一种时钟控制方法和装置，其采用从系统时钟和复位控制信号产生用于存储器阵列的阵列时钟的时钟控制电路。复位控制信号是到时钟控制电路的多个输入控制信号之一。当系统时钟低于预定频率阈值时，复位控制信号是阵列跟踪复位信号，其中阵列时钟的有效脉冲宽度是系统时钟频率无关的，当系统时钟高于预定频率阈值时，复位控制信号是中周期复位信号，意味着阵列时钟的有效脉冲宽度取决于系统时钟。提供旁路信号作为第三输入控制信号，当有效时，时钟控制电路输出反映系统时钟的阵列时钟。

6. 发明授权

US07233542B2 Method and apparatus for address generation 有权
标题翻译：用于地址生成的方法和装置
公开(公告)号：US07233542B2
公开(公告)日：2007-06-19
申请号：US11056048
申请日：2005-02-11
申请人： Paul A. Bunce , John D. Davis , Donald W. Plass
发明人： Paul A. Bunce , John D. Davis , Donald W. Plass
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C8/16
摘要： A system for generating one or more common address signals for multi-port memory arrays. The system includes circuitry receiving one or more read address signal; circuitry receiving one or more write address signal; circuitry receiving an array clock signal; circuitry receiving one or more enable signal; and circuitry generating the common address signals in response to the enable signal, the array clock signal and one of the read address signal and write address signal.
摘要翻译：一种用于为多端口存储器阵列产生一个或多个公共地址信号的系统。该系统包括接收一个或多个读取地址信号的电路; 接收一个或多个写入地址信号的电路; 接收阵列时钟信号的电路; 接收一个或多个使能信号的电路; 以及响应于使能信号，阵列时钟信号和读地址信号和写入地址信号之一产生公共地址信号的电路。

7. 发明授权

US07102944B1 Programmable analog control of a bitline evaluation circuit 失效
公开(公告)号：US07102944B1
公开(公告)日：2006-09-05
申请号：US11056049
申请日：2005-02-11
申请人： Paul A. Bunce , John D. Davis , Donald W. Plass
发明人： Paul A. Bunce , John D. Davis , Donald W. Plass
IPC分类号： G11C7/00
CPC分类号： G11C7/18 , G11C7/12 , G11C11/419
摘要： The invention may comprise circuit for programmable control of a discharge deactivation signal when interfacing local bitlines to a global bitline or other circuit. The invention may also comprise a method for programmable ground circuit control for control of a discharge signal deactivation when interfacing local bitlines to a global bitline via a bitline evaluation discharge device comprising: providing input logic states to inputs of a controller circuit; outputting an adjustable ground value from the controller circuit; and controlling the bitline evaluation discharge device with the adjustable ground value.

8. 发明授权

US07266737B2 Method for enabling scan of defective ram prior to repair 有权
标题翻译：修复前能够对有缺陷的公牛进行扫描的方法
公开(公告)号：US07266737B2
公开(公告)日：2007-09-04
申请号：US11180416
申请日：2005-07-13
申请人： Paul A. Bunce , John D. Davis , Patrick J. Meaney , Donald W. Plass
发明人： Paul A. Bunce , John D. Davis , Patrick J. Meaney , Donald W. Plass
IPC分类号： G11C29/00
CPC分类号： G11C29/48 , G01R31/318533 , G11C29/88 , G11C2029/3202
摘要： A semiconductor memory circuit enabling replacement of defective memory elements and associated circuitry with non-defective spare elements of the RAM and associated circuitry, is scanned to enable replacement of a defective RAM element prior to repair of the RAM. A set of set/reset latches are coupled to receive the signal from the memory elements, and a multiplexer control circuit coupled to receive a shift signal and a ram_inhibit signal from a multiplexer to provide specific input signals to the multiplexer components. When a scan operation begins an active clock signal sets a set/reset latch to ram_inhibit mode and this blocks the memory elements from influencing the state of memory output latches, whereby when an memory operation begins, an active clocking signal will reset the set/reset latch into system mode to cause the multiplexers pass appropriate signals from the memory elements to the output latches, and the spare memory element is activated to replace a defective memory element.
摘要翻译：扫描能够用RAM和关联电路的无缺陷备用元件替换缺陷存储器元件和相关电路的半导体存储器电路，以便在修复RAM之前更换有缺陷的RAM元件。耦合一组置位/复位锁存器以接收来自存储器元件的信号，以及多路复用器控制电路，其被耦合以从多路复用器接收移位信号和ram_inhibit信号以向多路复用器部件提供特定的输入信号。当扫描操作开始时，活动时钟信号将设置/复位锁存器设置为ram_inhibit模式，并且阻止存储器元件影响存储器输出锁存器的状态，由此当存储器操作开始时，有源时钟信号将复位置位/复位锁存到系统模式以使多路复用器将适当的信号从存储器元件传递到输出锁存器，并且备用存储器元件被激活以替换有缺陷的存储器元件。

9. 发明申请

US20070033459A1 Method for enabling scan of defective ram prior to repair 有权
公开(公告)号：US20070033459A1
公开(公告)日：2007-02-08
申请号：US11180416
申请日：2005-07-13
申请人： Paul A. Bunce , John D. Davis , Patrick J. Meaney , Donald W. Plass
发明人： Paul A. Bunce , John D. Davis , Patrick J. Meaney , Donald W. Plass
IPC分类号： G01R31/28
CPC分类号： G11C29/48 , G01R31/318533 , G11C29/88 , G11C2029/3202
摘要： A semiconductor memory circuit enabling replacement of defective memory elements and associated circuitry with non-defective spare elements of the RAM and associated circuitry, is scanned to enable replacement of a defective RAM element prior to repair of the RAM. A set of set/reset latches are coupled to receive the signal from the memory elements, and a multiplexer control circuit coupled to receive a shift signal and a ram_inhibit signal from a multiplexer to provide specific input signals to the multiplexer components. When a scan operation begins an active clock signal sets a set/reset latch to ram_inhibit mode and this blocks the memory elements from influencing the state of memory output latches, whereby when an memory operation begins, an active clocking signal will reset the set/reset latch into system mode to cause the multiplexers pass appropriate signals from the memory elements to the output latches, and the spare memory element is activated to replace a defective memory element.

10. 发明授权

US07075855B1 Memory output timing control circuit with merged functions 失效
标题翻译：具有合并功能的存储器输出定时控制电路
公开(公告)号：US07075855B1
公开(公告)日：2006-07-11
申请号：US11053612
申请日：2005-02-08
申请人： Paul A. Bunce , John D. Davis , Donald W. Plass
发明人： Paul A. Bunce , John D. Davis , Donald W. Plass
IPC分类号： G11C8/00
CPC分类号： G11C11/413 , G11C7/12 , G11C29/846
摘要： An output timing control circuit for use with a memory array. The output timing control circuit includes a redundancy decode circuit and a bit column output circuit. The bit column output circuit includes a first bit column output gate and a second bit column output gate, each bit column output gate is coupled to a bitline in the memory array. A precharge circuit is coupled to an output of the first bit column output gate and the second bit column output gate. The precharge circuit is responsive to a port enable signal. The redundancy decode circuit receives the port enable signal and a fuse signal and activates one of the first bit column output gate and the second bit column output gate.
摘要翻译：一种与存储器阵列一起使用的输出定时控制电路。输出定时控制电路包括冗余解码电路和位列输出电路。位列输出电路包括第一位列输出栅极和第二位列输出栅极，每个位列输出栅极耦合到存储器阵列中的位线。预充电电路耦合到第一位列输出栅极和第二位列输出栅极的输出端。预充电电路响应端口使能信号。冗余解码电路接收端口使能信号和熔丝信号，并激活第一位列输出栅极和第二位列输出栅极之一。

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