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1. 发明授权

US08599642B2 Port enable signal generation for gating a memory array device output 有权
标题翻译：用于门控存储器阵列器件输出的端口使能信号生成
公开(公告)号：US08599642B2
公开(公告)日：2013-12-03
申请号：US12822021
申请日：2010-06-23
申请人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar J. Vora
发明人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar J. Vora
IPC分类号： G11C8/18 , G06F1/04
CPC分类号： G06F1/10 , G11C11/419
摘要： A method of generating a dynamic port enable signal for gating memory array data to an output node includes generating a programmable leading edge clock signal derivation of an input dynamic clock signal; generating a programmable trailing edge clock signal derivation of the input dynamic clock signal, wherein the leading edge clock signal derivation and the trailing edge clock signal derivation are independently programmable with respect to one another; and gating the generated programmable leading and trailing edge clock signal derivations with a static input enable signal so as to generate the port enable signal such that, when inactive, the port enable signal prevents early memory array data from being coupled to the output node.
摘要翻译：产生用于将存储器阵列数据门控到输出节点的动态端口使能信号的方法包括产生输入动态时钟信号的可编程前沿时钟信号导出; 产生所述输入动态时钟信号的可编程后沿时钟信号导出，其中所述前沿时钟信号导出和所述后沿时钟信号导出可相对于彼此独立地可编程; 以及利用静态输入使能信号选通产生的可编程前导和后沿时钟信号导出，以便产生端口使能信号，使得当非活动时，端口使能信号防止早期存储器阵列数据耦合到输出节点。

2. 发明申请

US20110320851A1 PORT ENABLE SIGNAL GENERATION FOR GATING A MEMORY ARRAY DEVICE OUTPUT 有权
标题翻译：端口使能信号生成用于获取存储器阵列设备输出
公开(公告)号：US20110320851A1
公开(公告)日：2011-12-29
申请号：US12822021
申请日：2010-06-23
申请人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar Vora
发明人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar Vora
IPC分类号： G06F1/12 , G06F1/04
CPC分类号： G06F1/10 , G11C11/419
摘要： A method of generating a dynamic port enable signal for gating memory array data to an output node includes generating a programmable leading edge clock signal derivation of an input dynamic clock signal; generating a programmable trailing edge clock signal derivation of the input dynamic clock signal, wherein the leading edge clock signal derivation and the trailing edge clock signal derivation are independently programmable with respect to one another; and gating the generated programmable leading and trailing edge clock signal derivations with a static input enable signal so as to generate the port enable signal such that, when inactive, the port enable signal prevents early memory array data from being coupled to the output node.
摘要翻译：产生用于将存储器阵列数据门控到输出节点的动态端口使能信号的方法包括产生输入动态时钟信号的可编程前沿时钟信号导出; 产生所述输入动态时钟信号的可编程后沿时钟信号导出，其中所述前沿时钟信号导出和所述后沿时钟信号导出可相对于彼此独立地可编程; 以及利用静态输入使能信号选通产生的可编程前导和后沿时钟信号导出，以便产生端口使能信号，使得当非活动时，端口使能信号防止早期存储器阵列数据耦合到输出节点。

3. 发明申请

US20110317496A1 JAM LATCH FOR LATCHING MEMORY ARRAY OUTPUT DATA 失效
标题翻译：用于锁定内存阵列输出数据的JAM LATCH
公开(公告)号：US20110317496A1
公开(公告)日：2011-12-29
申请号：US12822038
申请日：2010-06-23
申请人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar Vora
发明人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar Vora
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/106 , G11C11/413
摘要： A jam latch device for a data node includes a feed forward inverter having an input coupled to the data node; a feedback inverter having an input connected to an output of the feed forward inverter with an output of the feedback inverter connected to the data node; an isolation device that selectively decouples the feedback inverter from a power supply rail, the isolation device controlled by a clock signal of a reset device that resets the data node to a first logic state such that decoupling of the feedback inverter from the power supply rail coincides with resetting the data node to the first logic state; and a margin test device that selectively increases pull down strength of the feedback inverter.
摘要翻译：用于数据节点的卡锁装置包括：前馈反相器，其具有耦合到数据节点的输入; 反馈逆变器，其具有连接到所述前馈逆变器的输出的输入端，所述反馈反相器的输出连接到所述数据节点; 隔离装置，其将反馈反相器与电源轨选择性地分离，该隔离装置由复位装置的时钟信号控制，该复位装置将数据节点复位到第一逻辑状态，使得反馈反相器与电源轨的解耦一致将数据节点重置为第一逻辑状态; 以及选择性地增加反馈逆变器的下拉强度的余量测试装置。

4. 发明授权

US07085173B1 Write driver circuit for memory array 失效
标题翻译：为存储器阵列写入驱动电路
公开(公告)号：US07085173B1
公开(公告)日：2006-08-01
申请号：US11054270
申请日：2005-02-09
申请人： Paul A. Bunce , John D. Davis , Donald W. Plass
发明人： Paul A. Bunce , John D. Davis , Donald W. Plass
IPC分类号： G11C7/10
CPC分类号： G11C7/1048 , G11C7/1078 , G11C7/1096
摘要： Embodiments of the invention include a circuit for interfacing local bitlines to a global bitline. The circuit includes an interface line coupled to a local bitline through a local bitline device. A global output device has an input coupled to the interface line and an output coupled to the global bitline. A clamping device is coupled to the interface line, the clamping device coupling the interface line to ground in response to a data in signal. A memory having the circuit is also disclosed.
摘要翻译：本发明的实施例包括用于将本地位线与全局位线接口的电路。该电路包括通过本地位线装置耦合到本地位线的接口线。全局输出设备具有耦合到接口线的输入和耦合到全局位线的输出。夹紧装置耦合到接口线，夹紧装置响应于信号中的数据将接口线耦合到地。还公开了一种具有该电路的存储器。

5. 发明授权

US07023759B1 System and method for synchronizing memory array signals 失效
标题翻译：用于同步存储器阵列信号的系统和方法
公开(公告)号：US07023759B1
公开(公告)日：2006-04-04
申请号：US11054495
申请日：2005-02-09
申请人： Paul A. Bunce , John D. Davis , Donald W. Plass
发明人： Paul A. Bunce , John D. Davis , Donald W. Plass
IPC分类号： G11C8/18
CPC分类号： G11C11/418 , G11C8/08 , G11C8/18
摘要： A method of generating access signals for a memory array. The method includes receiving a synchronization signal and generating a wordline select signal in response to the synchronization signal. A local precharge signal is generated in response to the synchronization signal. A precharge signal is generated in response to the synchronization signal, the precharge signal being a row signal for regulating memory array read operations. A write signal is generated in response to the synchronization signal, the write signal being a row signal for regulating memory array write operations.
摘要翻译：一种产生存储器阵列的存取信号的方法。该方法包括接收同步信号并响应于同步信号产生字线选择信号。响应于同步信号产生局部预充电信号。响应于同步信号产生预充电信号，预充电信号是用于调节存储器阵列读取操作的行信号。响应于同步信号产生写入信号，写入信号是用于调节存储器阵列写入操作的行信号。

6. 发明授权

US08351278B2 Jam latch for latching memory array output data 失效
标题翻译：用于锁存存储器阵列输出数据的卡锁
公开(公告)号：US08351278B2
公开(公告)日：2013-01-08
申请号：US12822038
申请日：2010-06-23
申请人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar J. Vora
发明人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar J. Vora
IPC分类号： G11C7/10
CPC分类号： G11C7/1051 , G11C7/106 , G11C11/413
摘要： A jam latch device for a data node includes a feed forward inverter having an input coupled to the data node; a feedback inverter having an input connected to an output of the feed forward inverter with an output of the feedback inverter connected to the data node; an isolation device that selectively decouples the feedback inverter from a power supply rail, the isolation device controlled by a clock signal of a reset device that resets the data node to a first logic state such that decoupling of the feedback inverter from the power supply rail coincides with resetting the data node to the first logic state; and a margin test device that selectively increases pull down strength of the feedback inverter.
摘要翻译：用于数据节点的卡锁装置包括：前馈反相器，其具有耦合到数据节点的输入; 反馈逆变器，其具有连接到所述前馈逆变器的输出的输入端，所述反馈反相器的输出连接到所述数据节点; 隔离装置，其将反馈反相器与电源轨选择性地分离，该隔离装置由复位装置的时钟信号控制，该复位装置将数据节点复位到第一逻辑状态，使得反馈反相器与电源轨的解耦一致将数据节点重置为第一逻辑状态; 以及选择性地增加反馈逆变器的下拉强度的余量测试装置。

7. 发明申请

US20080247245A1 WRITE CONTROL METHOD FOR A MEMORY ARRAY CONFIGURED WITH MULTIPLE MEMORY SUBARRAYS 失效
标题翻译：用于配置多个存储器子选项的存储器阵列的写控制方法
公开(公告)号：US20080247245A1
公开(公告)日：2008-10-09
申请号：US12139675
申请日：2008-06-16
申请人： John D. Davis , Paul A. Bunce , Donald W. Plass , Kenneth J. Reyer
发明人： John D. Davis , Paul A. Bunce , Donald W. Plass , Kenneth J. Reyer
IPC分类号： G11C7/22
CPC分类号： G11C11/413 , G11C7/18
摘要： Write control circuitry and control method are provided for a memory array configured with multiple memory subarrays. The write control circuitry includes multiple subarray write controllers associated with the multiple memory subarrays, each subarray write controller selectively enabling a local write control signal to its associated memory subarray. The selectively enabling is responsive to a received subarray select signal, wherein only one subarray select signal is active at a time. At least some subarray write controllers are powered at least in part via a switched power node, wherein powering of the switched power node is distributively implemented among the subarray write controllers. In one example, the distributively implemented powering of the switched power node is accomplished via multiple inverters distributed among the subarray write controllers, each inverter having an output coupled to the switched power node, and an input coupled to receive a global write enable signal.
摘要翻译：为配置有多个存储器子阵列的存储器阵列提供写控制电路和控制方法。写控制电路包括与多个存储器子阵列相关联的多个子阵列写控制器，每个子阵列写控制器选择性地使本地写控制信号到其相关的存储器子阵列。选择性地使能响应于接收的子阵列选择信号，其中一次只有一个子阵列选择信号是有效的。至少一些子阵列写控制器至少部分地通过交换式电源节点供电，其中，在子阵列写入控制器之间分配地实现切换的功率节点的供电。在一个示例中，通过分布在子阵列写控制器之间的多个反相器实现开关电源节点的分布式实现的供电，每个反相器具有耦合到开关电源节点的输出，以及耦合以接收全局写使能信号的输入。

8. 发明授权

US07233542B2 Method and apparatus for address generation 有权
标题翻译：用于地址生成的方法和装置
公开(公告)号：US07233542B2
公开(公告)日：2007-06-19
申请号：US11056048
申请日：2005-02-11
申请人： Paul A. Bunce , John D. Davis , Donald W. Plass
发明人： Paul A. Bunce , John D. Davis , Donald W. Plass
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C8/16
摘要： A system for generating one or more common address signals for multi-port memory arrays. The system includes circuitry receiving one or more read address signal; circuitry receiving one or more write address signal; circuitry receiving an array clock signal; circuitry receiving one or more enable signal; and circuitry generating the common address signals in response to the enable signal, the array clock signal and one of the read address signal and write address signal.
摘要翻译：一种用于为多端口存储器阵列产生一个或多个公共地址信号的系统。该系统包括接收一个或多个读取地址信号的电路; 接收一个或多个写入地址信号的电路; 接收阵列时钟信号的电路; 接收一个或多个使能信号的电路; 以及响应于使能信号，阵列时钟信号和读地址信号和写入地址信号之一产生公共地址信号的电路。

9. 发明授权

US07210084B2 Integrated system logic and ABIST data compression for an SRAM directory 失效
标题翻译：用于SRAM目录的集成系统逻辑和ABIST数据压缩
公开(公告)号：US07210084B2
公开(公告)日：2007-04-24
申请号：US10413612
申请日：2003-04-14
申请人： Paul A. Bunce , John D. Davis , Thomas J. Knips , Donald Plass
发明人： Paul A. Bunce , John D. Davis , Thomas J. Knips , Donald Plass
IPC分类号： G11C29/30 , G11C29/24
CPC分类号： G11C29/40 , G11C11/41
摘要： ABIST apparatus with integrated directory compare logic functionality, and ABIST error detection functionality. The apparatus includes two subsystems NOR'ed together. The first subsystem is for bit-wise logically ANDing corresponding array valid bits and tag valid inputs, generating “0” for a match and “1” for a mis-match, and logically ORing the bit-wise result to generate a “1” hit if there are any bit-wise mismatches. The second subsystem further receives ABIST control logic as an input to either: (a). combine array valid bits tag valid inputs to produce valid output, or (b) compare array valid bits with tag valid inputs. The apparatus further includes logical NOR functionality for the outputs of the first and second subsystems.
摘要翻译：具有集成目录比较逻辑功能的ABIST设备和ABIST错误检测功能。该装置包括NORs在一起的两个子系统。第一个子系统用于逐位逻辑地对应阵列有效位和标签有效输入，为匹配产生“0”，为了匹配而产生“1”，逻辑上对位逐次结果产生“1” 如果有任何比特错配，则打。第二子系统进一步接收ABIST控制逻辑作为输入：（a）。组合数组有效位标签有效输入以产生有效输出，或（b）将数组有效位与标签有效输入进行比较。该装置还包括用于第一和第二子系统的输出的逻辑NOR功能。

10. 发明授权

US07102944B1 Programmable analog control of a bitline evaluation circuit 失效
公开(公告)号：US07102944B1
公开(公告)日：2006-09-05
申请号：US11056049
申请日：2005-02-11
申请人： Paul A. Bunce , John D. Davis , Donald W. Plass
发明人： Paul A. Bunce , John D. Davis , Donald W. Plass
IPC分类号： G11C7/00
CPC分类号： G11C7/18 , G11C7/12 , G11C11/419
摘要： The invention may comprise circuit for programmable control of a discharge deactivation signal when interfacing local bitlines to a global bitline or other circuit. The invention may also comprise a method for programmable ground circuit control for control of a discharge signal deactivation when interfacing local bitlines to a global bitline via a bitline evaluation discharge device comprising: providing input logic states to inputs of a controller circuit; outputting an adjustable ground value from the controller circuit; and controlling the bitline evaluation discharge device with the adjustable ground value.

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